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| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-08-24 16:27:13 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-09-02 13:10:41 +0200 |
| commit | 9c05620b49718544ba163c2ccc3c5a6b1f0bc8b0 (patch) | |
| tree | 808e67b4fe56cadbcb036f52b8321af906853a53 /tools/perf/scripts/python/stackcollapse.py | |
| parent | cb388bd530cc518b0e245fb4eabc40f3de538e4f (diff) | |
perf/x86: Use x86_perf_regs in NMI handlers
Support for sampling additional register state in NMI context
(e.g. vector registers and SSP) requires an x86-specific register
container. The generic pt_regs structure cannot represent all of
the required x86 register data, so switch x86 NMI handlers to
x86_perf_regs.
pt_regs is still passed to x86_pmu_handle_irq(), so there is no
functional change to existing handling.
AMD IBS NMI handling does not use x86_pmu_handle_irq(), so this
conversion does not apply to IBS. IBS support for extended register
sampling can be added separately in follow-up patches.
Co-developed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260824082731.1013973-6-dapeng1.mi@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions