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| author | Dapeng Mi <dapeng1.mi@linux.intel.com> | 2026-08-24 16:27:17 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-09-02 13:10:42 +0200 |
| commit | c09466807467860f4d92b05bd4ca7db96f654ed0 (patch) | |
| tree | f90ce6d77a93179dca4e3d2ad7d09ff5ae9f5e02 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 05fe8825796e6b5557656c6c984486f0e66154fe (diff) | |
perf/x86/intel: Centralize PERF_PMU_CAP_EXTENDED_REGS updates
PERF_PMU_CAP_EXTENDED_REGS is currently updated in multiple paths:
intel_ds_pebs_init() and __intel_update_pmu_caps() for adaptive and
architectural PEBS. This split makes the capability flow harder to
reason about and is awkward for upcoming XSAVES-based SIMD register
sampling, which also needs consistent capability setup and validation.
Refactor the update logic into a single helper,
__intel_update_pmu_xregs_caps(), so adaptive and architectural PEBS
share one implementation.
Call this helper from intel_update_pmu_caps() to keep PMU capability
handling centralized in one place and avoid duplicated or conflicting
updates.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260824082731.1013973-10-dapeng1.mi@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions