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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2026-07-31 14:40:57 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-10-01 15:53:29 +0200 |
| commit | dbfca36538f00e51b97836cc8ede02e6bd8e561a (patch) | |
| tree | 8f2adbba15a02298f3db6cc888d69c297a19d8eb /tools/perf/scripts/python/stackcollapse.py | |
| parent | fd6377c033ef58740e2898a96cabb442157aee0a (diff) | |
ARM: tegra: tf701t: Configure CPU DFLL clock node
Enable DFLL for ASUS TF701T since it is now supported by Tegra114.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions