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authorShawn Guo <shengchao.guo@oss.qualcomm.com>2026-09-14 11:14:06 +0800
committerBjorn Andersson <andersson@kernel.org>2026-09-17 22:15:16 -0500
commit5e97460df08d194acb20861d1c58d7f55f8bb9bf (patch)
tree0e53a4d63a5a6de8d3ee1a0848d6887bd9ae176a /tools/perf/scripts/python/syscall-counts.py
parente62df36f34949aebe016c5c81e34baa7a9eca427 (diff)
arm64: dts: qcom: Add device tree for Nord SoC series
Add base device tree include (nord.dtsi) for the Nord SoC series describing the core hardware components: - 18 Oryon (qcom,oryon-1-5) cores in three clusters, with PSCI-based power management and CPU/cluster idle states - ARM GICv3 interrupt controller with ITS - TLMM GPIO/pinctrl controller - 8 TSENS thermal sensors with thermal zones - 3 APPS SMMU-500 instances - 3 QUPv3 GENI SE QUP blocks - PDP SCMI channel and mailbox - Watchdog, Crypto, TRNG and TCSR - Reserved memory, CMD-DB and firmware SCM - PSCI and architected timers Co-developed-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com> Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260914031412.140856-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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