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| author | Frank Zhu <frankzhu@zhaoxin.com> | 2026-09-10 19:54:13 +0800 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2026-09-11 09:35:56 -0700 |
| commit | 1a0abfad6c8096dfb00aa5a764d92819ff749103 (patch) | |
| tree | e8d362dec62cd2227bddf0aa79ac65810df70c0f /tools/perf/scripts/python/task-analyzer.py | |
| parent | 658d82c07e78eaa153991ca72326637a6cc6ce92 (diff) | |
KVM: selftests: Add Zhaoxin CPU support to nested exceptions test
When vectoring an injected #SS through the empty L2 IDT, Zhaoxin CPUs
report the resulting #GP with the IDT bit set and EXT clear. Zhaoxin
sets EXT only for interrupt delivery and selected guest-mode events; #SS
delivery is not one of those cases.
Expect error code 0x62 when running the test on Zhaoxin CPUs.
Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Link: https://patch.msgid.link/20260910115414.3015260-9-ewanhai-oc@zhaoxin.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions