diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2026-08-05 08:59:09 -0700 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-10-04 17:02:28 +0000 |
| commit | 1c5499e67303a9393388197fb14b39ed06a3dc55 (patch) | |
| tree | 6854152511f8ab1650c4453014156342b76d0b85 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 2e4fe234c72d65a09bbfd421240a0cfd7c8046a2 (diff) | |
perf/cxl: Validate the hardware-reported counter width
cxl_pmu_parse_caps() takes the Counter Width straight from the CPMU
Capability register without a bounds check. The Counter Data register is 64
bits wide, so a device reporting 0 or more than 64 is reporting nonsense,
and GENMASK_ULL(width - 1, 0) in the read path then shifts out of range.
That is undefined behaviour, and a UBSAN splat where it is enabled.
Reject a counter width outside 1..64 at probe.
Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
Reported-by: sashiko-bot@kernel.org
Closes: https://sashiko.dev/#/patchset/20260715191454.459673-1-dave@stgolabs.net?part=1
Assisted-by: Claude:claude-opus-4-8
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions