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| author | Brandon Brnich <b-brnich@ti.com> | 2026-09-21 13:48:48 -0500 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2026-09-28 11:56:19 -0500 |
| commit | 86ab93a198114653faf0fef11a88d4a240f5adf4 (patch) | |
| tree | 1b6ac157b23ae00ff2e7dbc6ea9eff4fecabda05 /tools/perf/scripts/python/task-analyzer.py | |
| parent | b4824bac766e1696a31c54c14541b65e33eb683f (diff) | |
arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node
The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.
Signed-off-by: Brandon Brnich <b-brnich@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Link: https://patch.msgid.link/20260921184850.3810018-3-b-brnich@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions