arm64: dts: renesas: beacon: Specify ethernet PHY reset timings

The KSZ9131RNX reference manual [1] DS00002841D page 131 FIGURE 6-2:
POWER SEQUENCE TIMING INTERNAL REGULATORS does not indicate how long
should the system wait after deassertion of the PHY reset and before
starting communication with the PHY via MDIO. Opt for the same value
as used for KSZ9031RNX, which is 300 us.

The KSZ9131RNX reference manual [1] DS00002841D page 131 FIGURE 6-2:
POWER SEQUENCE TIMING INTERNAL REGULATORS row tSR Stable supply
voltages to de-assertion of reset is at minimum 10 ms. Set DT
property reset-assert-us to 10ms because the KSZ9131RNX RM does
not explicitly spell out how long the reset has to be asserted,
but this at least covers the worst case scenario.

[1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/00002841D.pdf

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260714130539.11287-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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