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| author | kai zhang <zhangkai.cool@gmail.com> | 2026-10-07 22:15:58 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-10-07 16:45:19 -0500 |
| commit | e7b44579a6b4495c03720da49f2eeaf13a94ba69 (patch) | |
| tree | 7450db1db078db8076048c98262b14915ca5ce73 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 0b9df403ddfa6949ecd05bb7b218a5e685a5d016 (diff) | |
PCI/P2PDMA: Add Intel Xeon E3 v4/E5 v4/E7 v4 host bridge to allowlist
For P2P paths routed through a host bridge, the P2PDMA core consults an
allowlist of known-good hardware. Add Intel 8086:6f00 with
REQ_SAME_HOST_BRIDGE so the entry permits peers only below the same host
bridge.
The bridge was tested on a single-socket Intel Xeon E5-2697A v4 system
with two PCIe GPUs below different Root Ports of the same host bridge.
Without the allowlist entry, peer access was rejected before a transfer
was issued. With the entry, 64 MiB peer transfers completed in both
directions with data integrity verified while the IOMMU used translated
mode.
Assisted-by: LLM
Signed-off-by: kai zhang <zhangkai.cool@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20261007141558.59852-1-zhangkai.cool@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions