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authorAndrea Pesaresi <andreapesaresi82@gmail.com>2026-08-29 17:19:55 +0200
committerAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>2026-09-08 09:12:12 +0200
commit1cf18e4b9815beaf0439c5b57b65b45151c82ad7 (patch)
treea2418aecc707f275352ad00da765030fc522bade /tools/perf/scripts/python
parent69c1a4fd5272df1d745d6bcc3c613843ebecec61 (diff)
arm64: dts: mediatek: mt7986: correct timer frequency
The MT7986 architected timer runs at 12,986,200 Hz rather than 13 MHz. Firmware reports 13 MHz through CNTFRQ_EL0, causing the system clock to run slow by about 1062 ppm. This exceeds the kernel's 500 ppm NTP correction limit and leaves clock discipline saturated. The corrected rate comes from MediaTek's downstream OpenWrt feed, where it is applied to both MT7986A and MT7986B. Since upstream mt7986b.dtsi includes mt7986a.dtsi, add it once to the common timer node so the architected timer driver uses the actual counter rate. Fixes: 50137c150f5f ("arm64: dts: mediatek: add basic mt7986 support") Cc: stable@vger.kernel.org Link: https://github.com/mediatek/mtk-openwrt-feeds/commit/6a4c41c41410cd5042ad10c39da6593ba036283c Link: https://github.com/openwrt/openwrt/issues/24789 Signed-off-by: Andrea Pesaresi <andreapesaresi82@gmail.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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