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| author | Jonas Jelonek <jonas@jonasjelonek.de> | 2026-09-21 21:31:45 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-09-22 12:46:28 +0200 |
| commit | 1f82e6956faacc6e0c1b402838ba188e19af5a3c (patch) | |
| tree | b941cab443cb71a18fded0903a4c1f3ae8b8c803 /tools/perf/scripts/python | |
| parent | a124a7c33d24dff2ee4311b560424209098ea78e (diff) | |
spi: realtek-rtl: add support for second CS
The initial driver assumed that the controller's second chip select was
vestigial because none of the devices examined at the time used it. This
does not hold for all hardware: there are devices with a peripheral
connected to CS1. Since the controller only advertises one chip select
and keeps CS1 permanently deasserted, those peripherals cannot be used.
Advertise both native chip selects and select the appropriate CSBx bit in
->set_cs(). Build the initial SFCSR control value from zero. The
datasheet specifies CHIP_SEL for MMIO mode only, so keep it clear for
this PIO driver and set only the two active-low CSB bits to leave both
lines deasserted.
Rename the callback argument from "active" to "level" while touching this
code. ->set_cs() receives the physical line level, not a logical assertion
state: after applying SPI_CS_HIGH, the core passes false to drive the line
low and true to drive it high. The CSBx bits directly encode that level,
and the native outputs are active-low, so clear the selected bit for a
low/asserted line and set it for a high/deasserted line.
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
Link: https://patch.msgid.link/20260921213145.671282-1-jonas@jonasjelonek.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
