diff options
| author | Jiaxing Hu <gahing@gahingwoo.com> | 2026-08-19 18:47:07 +1200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-08-31 15:37:44 +0200 |
| commit | 3bcd04b3e009fdd5b051c95f31c742bc9257fcb9 (patch) | |
| tree | 0a66d2d63a321e3babc210905d5725807105a617 /tools/perf/scripts/python | |
| parent | a3827558c623db5a4f7033f3cffe214577470df9 (diff) | |
arm64: dts: rockchip: fix an error and a typo in the CM5-IO comment
Two mistakes in the CM5-IO header comment.
The USB-C line names combphy0, but combphy0 is the M.2 PCIe lane, as the
comment above &combphy0_ps says. The USB-C SuperSpeed path is the USBDP
PHY.
The USB-A count is also wrong: the carrier has four ports, not two. The
RTS5411S USB 3.0 hub fans the single USB3 lane out to four downstream
USB-A ports.
Comment only, no functional change.
Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
Link: https://patch.msgid.link/20260819064707.1667292-1-gahing@gahingwoo.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions