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authorSascha Bischoff <Sascha.Bischoff@arm.com>2026-09-04 11:54:05 +0000
committerMarc Zyngier <maz@kernel.org>2026-09-14 10:49:09 +0100
commit53e9639e758524ab1f92b836d0fc4f023e762903 (patch)
treed1288f4c4b3b5c27ecc08af30393829e35ac9f4e /tools/perf/scripts/python
parenta7f442da926bae29563f456e5df6e59d44ff77ee (diff)
Documentation: KVM: Add the VGICv5 IRS save/restore sequences
Document the ordering requirements for saving and restoring the GICv5 IRS state. The IST state is exposed through KVM_DEV_ARM_VGIC_GRP_IST and is copied to or from userspace-provided buffers. Saving the ISTs therefore does not update guest memory, so userspace does not need to serialize guest memory after saving the IST state. On restore, userspace must create the vCPUs, configure the IRS address, restore the number of SPIs, and initialize the VGIC before restoring IRS state. The IRS MMIO registers may be restored in any order, but the final IRS_IDR* state and the IRS_IST_CFGR/IRS_IST_BASER state that describes any LPI IST must be restored before KVM_DEV_ARM_VGIC_GRP_IST. KVM uses that state to validate the userspace IST buffers and allocate any host LPI IST. The IRS_*_STATUSR registers are observational state in KVM. Userspace may save them for validation or debugging, but they are not required as restore input and do not need to be replayed. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Link: https://patch.msgid.link/20260904113404.4051341-40-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org>
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