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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-09-25 10:53:29 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-09-28 13:26:39 +0200 |
| commit | 6c09280e00e4bb7a43badcec9dec8d41fbb9b5e0 (patch) | |
| tree | 8ffec9f800b2b5bcbfe75218b06ff3bafe064a6e /tools/perf/scripts/python | |
| parent | cee9395acd8043be0644b25c34bfa86623f2b935 (diff) | |
dt-bindings: clock: renesas,r8a78000-cpg: Add MSIOF clocks
Add definitions for the functional clock parents of the
Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas
R-Car X5H (R8A78000) SoC:
- MSO_SCP_MAIN is the functional clock parent for MSIOF[0-3],
- MSOCK_PERW_BUS is the functional clock parent for MSIOF[4-7].
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/9a5f4e324e3b67d367f850264cbaf7e830cec182.1790325809.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions