spi: ma35d1: Add Nuvoton MA35D1 SPI controller support

Add support for the SPI controller found in the Nuvoton MA35D1 SoC.

The driver supports SPI host mode using polling-based PIO transfers,
with SPI modes 0 through 3, LSB-first operation, and word sizes from
8 to 32 bits.

Support the two native chip-select outputs as well as GPIO chip selects
through the SPI core GPIO descriptor support.

Configure the SPI clock divider according to the hardware requirement
that only odd CLKDIV register values are valid, ensuring that the
generated SPI clock does not exceed the requested transfer frequency.

The controller must be disabled before changing CTL, CLKDIV, SSCTL or
FIFOCTL. Avoid unnecessary enable/disable cycles by reconfiguring the
controller only when the transfer settings change.

Add system sleep support using the SPI core suspend and resume helpers.
The MA35D1 SPI registers are retained across power-down and deep sleep,
so no hardware state restoration is required after resume.

Signed-off-by: Chi-Wen Weng <cwweng@nuvoton.com>
Link: https://patch.msgid.link/20261001131818.110028-3-cwweng.linux@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

0 files changed, 0 insertions, 0 deletions