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| author | Roman Li <Roman.Li@amd.com> | 2025-04-03 13:49:03 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-04-21 11:28:30 -0400 |
| commit | e15d09f510d0303b53e556a73fa4236744c19695 (patch) | |
| tree | 57463f646777234a3f6e8c8b69404a1bd75b61c6 /tools/perf/scripts/python | |
| parent | cd74ce1f0cddffb3f36d0995d0f61e89f0010738 (diff) | |
drm/amd/display: enable phy-ssc reduction by default
[Why]
Reduction of phy-ssc is needed to support DP2 high pixel clock on dcn35x/36.
There's a special flag to enable it in dmub hw params.
[How]
Set hbr3_phy_ssc to true for dcn35, dcn351 and dcn36.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions