diff options
| author | Jack Yu <jack.yu@realtek.com> | 2026-09-24 10:05:10 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-09-24 19:32:31 +0100 |
| commit | eb169cc54b87fc2c633c2343c6060c5955efb69d (patch) | |
| tree | 1f98b33c3351c66aca9b4ac2feae576781e5a61f /tools/perf/scripts/python | |
| parent | 92871abc1302b852b88d86114115f8fd6b50b9b9 (diff) | |
ASoC: rt1320: make SRAM registers readable to stop being cached
rt1320_volatile_register() marks the SRAM ranges 0x10000000-0x10008fff
and 0x1000c000-0x1000dfff as volatile, but regmap only honors that flag
for a readable register and these ranges were missing from
rt1320_readable_register(). They were therefore cached at probe and
replayed over SoundWire on every runtime resume, delaying the
first PCM open after autosuspend by about a second.
Make the ranges readable so the volatile flag takes effect and the SRAM
is no longer cached. Exclude 0x1000d000-0x1000d7ff from both callbacks,
since rt1320_rae_load() deliberately caches that tuning-tool window.
Signed-off-by: Jack Yu <jack.yu@realtek.com>
Link: https://patch.msgid.link/20260924020510.3551163-1-jack.yu@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
