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authorQiang Yu <qiang.yu@oss.qualcomm.com>2026-08-25 19:59:22 -0700
committerBjorn Andersson <andersson@kernel.org>2026-08-31 11:10:07 -0500
commitf4526f9ee3146224d94907b38c712177d9c74df7 (patch)
tree08466d34d51736739bad5779974e9cf4f3da1de7 /tools/perf/scripts/python
parent5d9046549e433257f7fcc5d59a9a449c8c11dd84 (diff)
arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy
Unlike Glymur, Mahua only has PCIe3b wired up; there is no PCIe3a controller and no shared Gen5x8 PHY block. Delete the inherited pcie3a and pcie3_phy nodes, and add a dedicated pcie3b_phy using the existing qcom,glymur-qmp-gen5x4-pcie-phy compatible. Point pcie3b_port0's phys and the GCC pipe clock parent array at &pcie3b_phy instead of the deleted &pcie3_phy. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260825-glymur_linkmode_0826-v10-3-56ab597d77e4@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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