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| author | Adrian Hunter <adrian.hunter@intel.com> | 2023-03-20 20:35:17 +0200 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2023-03-20 19:25:40 -0300 |
| commit | 052072f69f28864cebaeb6ca9dc2c9825b72c834 (patch) | |
| tree | 4cc3714f511e99fd561a54b7022d8e9f76a31e5f /tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h | |
| parent | 34f576c95d1bd1be3f123c2d1f3db084e5e72583 (diff) | |
perf intel-pt: Add support for new branch instructions ERETS and ERETU
Intel Flexible Return and Event Delivery (FRED) adds instructions ERETS
(return to supervisor) and ERETU (return to user). Intel PT instruction
decoder needs to know about these instructions because they are
branch instructions. Similar to IRET instructions, when the decoder
encounters one of these instructions it will match it to a TIP (target
instruction pointer) packet that informs what the branch destination is.
The existing "x86 instruction decoder - new instructions" test can be
used to test the result e.g.
$ perf test -v ins |& grep eret
Decoded ok: f2 0f 01 ca erets
Decoded ok: f3 0f 01 ca eretu
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20230320183517.15099-2-adrian.hunter@intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h')
| -rw-r--r-- | tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h index e3338b56a75f..7fb7fe3a1566 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h +++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h @@ -25,6 +25,8 @@ enum intel_pt_insn_op { INTEL_PT_OP_SYSCALL, INTEL_PT_OP_SYSRET, INTEL_PT_OP_VMENTRY, + INTEL_PT_OP_ERETS, + INTEL_PT_OP_ERETU, }; enum intel_pt_insn_branch { |