diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi index ab5279c4ff59..f18fb628b66c 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-osm.dtsi @@ -455,7 +455,7 @@ /* OSM SPI_B */ &lpspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi_b>, <&pinctrl_spi_b_cs0>; + pinctrl-0 = <&pinctrl_spi_b>, <&pinctrl_spi_b_cs0_gpio>; cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>, <&som_gpio_expander_0 15 GPIO_ACTIVE_LOW>; @@ -475,7 +475,7 @@ /* OSM SPI_A */ &lpspi4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi_a>, <&pinctrl_spi_a_cs0>; + pinctrl-0 = <&pinctrl_spi_a>, <&pinctrl_spi_a_cs0_gpio>; cs-gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; }; @@ -791,6 +791,11 @@ fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x31e>; /* OSM F19 */ }; + /* OSM SPI_B_CS0# */ + pinctrl_spi_b_cs0_gpio: gpio1io9grp { + fsl,pins = <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x3fe>; /* OSM AA23 */ + }; + /* OSM PWM_0 as GPIO */ pinctrl_pwm0_gpio: gpio2io12grp { fsl,pins = <IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x31e>; /* OSM E18 */ @@ -816,6 +821,11 @@ fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e>; /* OSM K17 */ }; + /* OSM SPI_A_CS0# */ + pinctrl_spi_a_cs0_gpio: gpio5io14grp { + fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x3fe>; /* OSM Y15 */ + }; + /* OSM GPIO_A_1 */ pinctrl_gpio_a1: gpio5io1grp { fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x31e>; /* OSM E17 */ @@ -882,10 +892,6 @@ }; /* OSM SPI_B */ - pinctrl_spi_b_cs0: lpspi1cs0grp { - fsl,pins = <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x3fe>; /* OSM AA23 */ - }; - pinctrl_spi_b: lpspi1grp { fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x3fe>, /* OSM Y21 */ <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x3fe>, /* OSM Y23 */ @@ -893,10 +899,6 @@ }; /* OSM SPI_A */ - pinctrl_spi_a_cs0: lpspi4cs0grp { - fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x3fe>; /* OSM Y15 */ - }; - pinctrl_spi_a: lpspi4grp { fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x3fe>, /* OSM U16 */ <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x3fe>, /* OSM V15 */ |