diff options
| -rw-r--r-- | drivers/phy/freescale/phy-fsl-lynx-28g.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c index 01589a2bfe74..be804f9b7d5e 100644 --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c @@ -166,6 +166,18 @@ #define LNaRECR4_EQ_BIN_DATA GENMASK(8, 0) /* bit 9 is reserved */ #define LNaRECR4_EQ_BIN_DATA_SGN BIT(8) +#define LNaRCCR0(lane) (0x800 + (lane) * 0x100 + 0x68) +#define LNaRCCR0_CAL_EN BIT(31) +#define LNaRCCR0_MEAS_EN BIT(30) +#define LNaRCCR0_CAL_BIN_SEL BIT(28) +#define LNaRCCR0_CAL_DC3_DIS BIT(27) +#define LNaRCCR0_CAL_DC2_DIS BIT(26) +#define LNaRCCR0_CAL_DC1_DIS BIT(25) +#define LNaRCCR0_CAL_DC0_DIS BIT(24) +#define LNaRCCR0_CAL_AC3_OV_EN BIT(15) +#define LNaRCCR0_CAL_AC3_OV GENMASK(11, 8) +#define LNaRCCR0_CAL_AC2_OV_EN BIT(7) + #define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74) #define LNaRSCCR0_SMP_OFF_EN BIT(31) #define LNaRSCCR0_SMP_OFF_OV_EN BIT(30) @@ -180,6 +192,15 @@ #define LNaRSCCR0_SMP_AUTOZ_EG1R GENMASK(5, 4) #define LNaRSCCR0_SMP_AUTOZ_EG1F GENMASK(1, 0) +#define LNaTTLCR0(lane) (0x800 + (lane) * 0x100 + 0x80) +#define LNaTTLCR0_TTL_FLT_SEL GENMASK(29, 24) +#define LNaTTLCR0_TTL_SLO_PM_BYP BIT(22) +#define LNaTTLCR0_STALL_DET_DIS BIT(21) +#define LNaTTLCR0_INACT_MON_DIS BIT(20) +#define LNaTTLCR0_CDR_OV GENMASK(18, 16) +#define LNaTTLCR0_DATA_IN_SSC BIT(15) +#define LNaTTLCR0_CDR_MIN_SMP_ON GENMASK(1, 0) + #define LNaTCSR0(lane) (0x800 + (lane) * 0x100 + 0xa0) #define LNaTCSR0_SD_STAT_OBS_EN BIT(31) #define LNaTCSR0_SD_LPBK_SEL GENMASK(29, 28) @@ -286,6 +307,10 @@ struct lynx_28g_proto_conf { /* LNaRSCCR0 */ int smp_autoz_d1r; int smp_autoz_eg1r; + /* LNaRCCR0 */ + int rccr0; + /* LNaTTLCR0 */ + int ttlcr0; }; static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = { @@ -316,6 +341,9 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = { .spare_in = 0, .smp_autoz_d1r = 0, .smp_autoz_eg1r = 0, + .rccr0 = LNaRCCR0_CAL_EN, + .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP | + LNaTTLCR0_DATA_IN_SSC, }, [LANE_MODE_USXGMII] = { .proto_sel = LNaGCR0_PROTO_SEL_XFI, @@ -344,6 +372,9 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = { .spare_in = 0, .smp_autoz_d1r = 2, .smp_autoz_eg1r = 0, + .rccr0 = LNaRCCR0_CAL_EN, + .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP | + LNaTTLCR0_DATA_IN_SSC, }, [LANE_MODE_10GBASER] = { .proto_sel = LNaGCR0_PROTO_SEL_XFI, @@ -372,6 +403,9 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = { .spare_in = 0, .smp_autoz_d1r = 2, .smp_autoz_eg1r = 0, + .rccr0 = LNaRCCR0_CAL_EN, + .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP | + LNaTTLCR0_DATA_IN_SSC, }, }; @@ -829,6 +863,9 @@ static void lynx_28g_lane_change_proto_conf(struct lynx_28g_lane *lane, FIELD_PREP(LNaRSCCR0_SMP_AUTOZ_EG1R, conf->smp_autoz_eg1r), LNaRSCCR0_SMP_AUTOZ_D1R | LNaRSCCR0_SMP_AUTOZ_EG1R); + + lynx_28g_lane_write(lane, LNaRCCR0, conf->rccr0); + lynx_28g_lane_write(lane, LNaTTLCR0, conf->ttlcr0); } static int lynx_28g_lane_disable_pcvt(struct lynx_28g_lane *lane, |