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-rw-r--r--Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml80
-rw-r--r--arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts5
-rw-r--r--arch/riscv/boot/dts/sophgo/cv180x.dtsi42
-rw-r--r--arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts5
-rw-r--r--arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts5
-rw-r--r--arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts36
-rw-r--r--arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts24
-rw-r--r--arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts36
-rw-r--r--arch/riscv/boot/dts/sophgo/sg2042.dtsi112
9 files changed, 345 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml
new file mode 100644
index 000000000000..b2e8e0cb4ea6
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/sophgo/sophgo,cv1800b-top-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV18XX/SG200X SoC top system controller
+
+maintainers:
+ - Inochi Amaoto <inochiama@outlook.com>
+
+description:
+ The Sophgo CV18XX/SG200X SoC top misc system controller provides
+ register access to configure related modules.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: sophgo,cv1800b-top-syscon
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ dma-router@154:
+ $ref: /schemas/dma/sophgo,cv1800b-dmamux.yaml#
+ unevaluatedProperties: false
+
+ phy@48:
+ $ref: /schemas/phy/sophgo,cv1800b-usb2-phy.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sophgo,cv1800.h>
+
+ syscon@3000000 {
+ compatible = "sophgo,cv1800b-top-syscon", "syscon", "simple-mfd";
+ reg = <0x03000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy@48 {
+ compatible = "sophgo,cv1800b-usb2-phy";
+ reg = <0x48 0x4>;
+ #phy-cells = <0>;
+ clocks = <&clk CLK_USB_125M>,
+ <&clk CLK_USB_33K>,
+ <&clk CLK_USB_12M>;
+ clock-names = "app", "stb", "lpm";
+ resets = <&rst 58>;
+ };
+
+ dma-router@154 {
+ compatible = "sophgo,cv1800b-dmamux";
+ reg = <0x154 0x8>, <0x298 0x4>;
+ #dma-cells = <2>;
+ dma-masters = <&dmac>;
+ };
+ };
+
+...
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
index 9feb520eaec4..0e6d79e6e3a4 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
+++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
@@ -100,3 +100,8 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usb {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index ccdb45498653..1b2b1969a648 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -25,6 +25,32 @@
#size-cells = <1>;
ranges;
+ syscon: syscon@3000000 {
+ compatible = "sophgo,cv1800b-top-syscon",
+ "syscon", "simple-mfd";
+ reg = <0x03000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ usbphy: phy@48 {
+ compatible = "sophgo,cv1800b-usb2-phy";
+ reg = <0x48 0x4>;
+ #phy-cells = <0>;
+ clocks = <&clk CLK_USB_125M>,
+ <&clk CLK_USB_33K>,
+ <&clk CLK_USB_12M>;
+ clock-names = "app", "stb", "lpm";
+ resets = <&rst RST_COMBO_PHY0>;
+ };
+
+ dmamux: dma-router@154 {
+ compatible = "sophgo,cv1800b-dmamux";
+ reg = <0x154 0x8>, <0x298 0x4>;
+ #dma-cells = <2>;
+ dma-masters = <&dmac>;
+ };
+ };
+
rst: reset-controller@3003000 {
compatible = "sophgo,cv1800b-reset";
reg = <0x3003000 0x1000>;
@@ -406,6 +432,22 @@
status = "disabled";
};
+ usb: usb@4340000 {
+ compatible = "sophgo,cv1800b-usb";
+ reg = <0x04340000 0x10000>;
+ clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>;
+ clock-names = "otg", "utmi";
+ g-np-tx-fifo-size = <32>;
+ g-rx-fifo-size = <536>;
+ g-tx-fifo-size = <768 512 512 384 128 128>;
+ interrupts = <SOC_PERIPHERAL_IRQ(14) IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbphy>;
+ phy-names = "usb2-phy";
+ resets = <&rst RST_USB>;
+ reset-names = "dwc2";
+ status = "disabled";
+ };
+
rtc@5025000 {
compatible = "sophgo,cv1800b-rtc", "syscon";
reg = <0x5025000 0x2000>;
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
index 4a5835fa9e96..aedf79f47407 100644
--- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
+++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
@@ -86,3 +86,8 @@
&uart0 {
status = "okay";
};
+
+&usb {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
index 86a712b953a5..b1853770d017 100644
--- a/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
@@ -93,3 +93,8 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usb {
+ dr_mode = "host";
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
index 3320bc1dd2c6..b116dfa904cd 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
@@ -164,6 +164,18 @@
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc1 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
@@ -238,6 +250,30 @@
status = "okay";
};
+&spifmc0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
index 46980e41b886..b2ceae2d8829 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
@@ -152,6 +152,18 @@
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc1 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
@@ -226,6 +238,18 @@
status = "okay";
};
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index ef3a602172b1..54d8386bf9c0 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -128,6 +128,18 @@
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
+&pcie_rc3 {
+ status = "okay";
+};
+
&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
@@ -138,6 +150,30 @@
status = "okay";
};
+&spifmc0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index c5e49709b308..ec99da39150f 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -68,6 +68,30 @@
interrupt-parent = <&intc>;
ranges;
+ spifmc0: spi@7000180000 {
+ compatible = "sophgo,sg2042-spifmc-nor";
+ reg = <0x70 0x00180000 0x0 0x1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkgen GATE_CLK_AHB_SF>;
+ interrupt-parent = <&intc>;
+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstgen RST_SF0>;
+ status = "disabled";
+ };
+
+ spifmc1: spi@7002180000 {
+ compatible = "sophgo,sg2042-spifmc-nor";
+ reg = <0x70 0x02180000 0x0 0x1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkgen GATE_CLK_AHB_SF>;
+ interrupt-parent = <&intc>;
+ interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstgen RST_SF1>;
+ status = "disabled";
+ };
+
i2c0: i2c@7030005000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30005000 0x0 0x1000>;
@@ -240,6 +264,94 @@
#clock-cells = <1>;
};
+ pcie_rc0: pcie@7060000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60000000 0x0 0x00800000>,
+ <0x40 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc1: pcie@7060800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60800000 0x0 0x00800000>,
+ <0x44 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc2: pcie@7062000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62000000 0x0 0x00800000>,
+ <0x48 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc3: pcie@7062800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62800000 0x0 0x00800000>,
+ <0x4c 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
generated by cgit v1.2.3 (git 2.0.4) at 2025-12-24 15:51:20 +0000