diff options
| -rw-r--r-- | Documentation/trace/events-pci-controller.rst | 42 | ||||
| -rw-r--r-- | Documentation/trace/index.rst | 1 | ||||
| -rw-r--r-- | MAINTAINERS | 2 | ||||
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-dw-rockchip.c | 111 | ||||
| -rw-r--r-- | drivers/pci/trace.c | 1 | ||||
| -rw-r--r-- | include/trace/events/pci_controller.h | 58 |
6 files changed, 215 insertions, 0 deletions
diff --git a/Documentation/trace/events-pci-controller.rst b/Documentation/trace/events-pci-controller.rst new file mode 100644 index 000000000000..cb9f71592973 --- /dev/null +++ b/Documentation/trace/events-pci-controller.rst @@ -0,0 +1,42 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Subsystem Trace Points: PCI Controller +====================================== + +Overview +======== +The PCI controller tracing system provides tracepoints to monitor controller +level information for debugging purpose. The events normally show up here: + + /sys/kernel/tracing/events/pci_controller + +Cf. include/trace/events/pci_controller.h for the events definitions. + +Available Tracepoints +===================== + +pcie_ltssm_state_transition +--------------------------- + +Monitors PCIe LTSSM state transition including state and rate information +:: + + pcie_ltssm_state_transition "dev: %s state: %s rate: %s\n" + +**Parameters**: + +* ``dev`` - PCIe controller instance +* ``state`` - PCIe LTSSM state +* ``rate`` - PCIe date rate + +**Example Usage**: + +.. code-block:: shell + + # Enable the tracepoint + echo 1 > /sys/kernel/debug/tracing/events/pci_controller/pcie_ltssm_state_transition/enable + + # Monitor events (the following output is generated when a device is linking) + cat /sys/kernel/debug/tracing/trace_pipe + kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s diff --git a/Documentation/trace/index.rst b/Documentation/trace/index.rst index 338bc4d7cfab..5715a32866ab 100644 --- a/Documentation/trace/index.rst +++ b/Documentation/trace/index.rst @@ -55,6 +55,7 @@ applications. events-nmi events-msr events-pci + events-pci-controller boottime-trace histogram histogram-design diff --git a/MAINTAINERS b/MAINTAINERS index 36eb8aa2de0d..581658840e67 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20403,9 +20403,11 @@ C: irc://irc.oftc.net/linux-pci T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git F: Documentation/ABI/testing/debugfs-pcie-ptm F: Documentation/devicetree/bindings/pci/ +F: Documentation/trace/events-pci-controller.rst F: drivers/pci/controller/ F: drivers/pci/pci-bridge-emul.c F: drivers/pci/pci-bridge-emul.h +F: include/trace/events/pci_controller.h PCI PEER-TO-PEER DMA (P2PDMA) M: Bjorn Helgaas <bhelgaas@google.com> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 8db27199cfa6..731d93663cca 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -22,6 +22,8 @@ #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset.h> +#include <linux/workqueue.h> +#include <trace/events/pci_controller.h> #include "../../pci.h" #include "pcie-designware.h" @@ -73,6 +75,20 @@ #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4) #define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5) +/* Debug FIFO information */ +#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 +#define PCIE_CLIENT_DBG_EN 0xffff0007 +#define PCIE_CLIENT_DBG_DIS 0xffff0000 +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 +#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 +#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c +#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 +#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 +#define PCIE_DBG_FIFO_RATE_MASK GENMASK(22, 20) +#define PCIE_DBG_FIFO_L1SUB_MASK GENMASK(10, 8) +#define PCIE_DBG_LTSSM_HISTORY_CNT 64 + /* Hot Reset Control Register */ #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_LTSSM_APP_DLY2_EN BIT(1) @@ -98,6 +114,7 @@ struct rockchip_pcie { struct irq_domain *irq_domain; const struct rockchip_pcie_of_data *data; bool supports_clkreq; + struct delayed_work trace_work; }; struct rockchip_pcie_of_data { @@ -208,6 +225,96 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci) return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK; } +#ifdef CONFIG_TRACING +static void rockchip_pcie_ltssm_trace_work(struct work_struct *work) +{ + struct rockchip_pcie *rockchip = container_of(work, + struct rockchip_pcie, + trace_work.work); + struct dw_pcie *pci = &rockchip->pci; + enum dw_pcie_ltssm state; + u32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val; + + if (!trace_pcie_ltssm_state_transition_enabled()) + goto skip_trace; + + for (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) { + val = rockchip_pcie_readl_apb(rockchip, + PCIE_CLIENT_DBG_FIFO_STATUS); + rate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val); + l1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val); + val = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val); + + /* + * Hardware Mechanism: The ring FIFO employs two tracking + * counters: + * - 'last-read-point': maintains the user's last read position + * - 'last-valid-point': tracks the HW's last state update + * + * Software Handling: When two consecutive LTSSM states are + * identical, it indicates invalid subsequent data in the FIFO. + * In this case, we skip the remaining entries. The dual counter + * design ensures that on the next state transition, reading can + * resume from the last user position. + */ + if ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3) + break; + + state = prev_val = val; + if (val == DW_PCIE_LTSSM_L1_IDLE) { + if (l1ss == 2) + state = DW_PCIE_LTSSM_L1_2; + else if (l1ss == 1) + state = DW_PCIE_LTSSM_L1_1; + } + + trace_pcie_ltssm_state_transition(dev_name(pci->dev), + dw_pcie_ltssm_status_string(state), + ((rate + 1) > pci->max_link_speed) ? + PCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate); + } + +skip_trace: + schedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000)); +} + +static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip, + bool enable) +{ + if (enable) { + rockchip_pcie_writel_apb(rockchip, + PCIE_CLIENT_DBG_TRANSITION_DATA, + PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0); + rockchip_pcie_writel_apb(rockchip, + PCIE_CLIENT_DBG_TRANSITION_DATA, + PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1); + rockchip_pcie_writel_apb(rockchip, + PCIE_CLIENT_DBG_TRANSITION_DATA, + PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0); + rockchip_pcie_writel_apb(rockchip, + PCIE_CLIENT_DBG_TRANSITION_DATA, + PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1); + rockchip_pcie_writel_apb(rockchip, + PCIE_CLIENT_DBG_EN, + PCIE_CLIENT_DBG_FIFO_MODE_CON); + + INIT_DELAYED_WORK(&rockchip->trace_work, + rockchip_pcie_ltssm_trace_work); + schedule_delayed_work(&rockchip->trace_work, 0); + } else { + rockchip_pcie_writel_apb(rockchip, + PCIE_CLIENT_DBG_DIS, + PCIE_CLIENT_DBG_FIFO_MODE_CON); + cancel_delayed_work_sync(&rockchip->trace_work); + } +} +#else +static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip, + bool enable) +{ +} +#endif + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -291,6 +398,9 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci) * 100us as we don't know how long should the device need to reset. */ msleep(PCIE_T_PVPERL_MS); + + rockchip_pcie_ltssm_trace(rockchip, true); + gpiod_set_value_cansleep(rockchip->rst_gpio, 1); return 0; @@ -301,6 +411,7 @@ static void rockchip_pcie_stop_link(struct dw_pcie *pci) struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); rockchip_pcie_disable_ltssm(rockchip); + rockchip_pcie_ltssm_trace(rockchip, false); } static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) diff --git a/drivers/pci/trace.c b/drivers/pci/trace.c index cf11abca8602..c1da9d3d39d6 100644 --- a/drivers/pci/trace.c +++ b/drivers/pci/trace.c @@ -9,3 +9,4 @@ #define CREATE_TRACE_POINTS #include <trace/events/pci.h> +#include <trace/events/pci_controller.h> diff --git a/include/trace/events/pci_controller.h b/include/trace/events/pci_controller.h new file mode 100644 index 000000000000..a4b387cf52a6 --- /dev/null +++ b/include/trace/events/pci_controller.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM pci_controller + +#if !defined(_TRACE_HW_EVENT_PCI_CONTROLLER_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_HW_EVENT_PCI_CONTROLLER_H + +#include <uapi/linux/pci_regs.h> +#include <linux/tracepoint.h> + +#define RATE \ + EM(PCIE_SPEED_2_5GT, "2.5 GT/s") \ + EM(PCIE_SPEED_5_0GT, "5.0 GT/s") \ + EM(PCIE_SPEED_8_0GT, "8.0 GT/s") \ + EM(PCIE_SPEED_16_0GT, "16.0 GT/s") \ + EM(PCIE_SPEED_32_0GT, "32.0 GT/s") \ + EM(PCIE_SPEED_64_0GT, "64.0 GT/s") \ + EMe(PCI_SPEED_UNKNOWN, "Unknown") + + +#undef EM +#undef EMe +#define EM(a, b) TRACE_DEFINE_ENUM(a); +#define EMe(a, b) TRACE_DEFINE_ENUM(a); + +RATE + +#undef EM +#undef EMe +#define EM(a, b) {a, b}, +#define EMe(a, b) {a, b} + +TRACE_EVENT(pcie_ltssm_state_transition, + TP_PROTO(const char *dev_name, const char *state, u32 rate), + TP_ARGS(dev_name, state, rate), + + TP_STRUCT__entry( + __string(dev_name, dev_name) + __string(state, state) + __field(u32, rate) + ), + + TP_fast_assign( + __assign_str(dev_name); + __assign_str(state); + __entry->rate = rate; + ), + + TP_printk("dev: %s state: %s rate: %s", + __get_str(dev_name), __get_str(state), + __print_symbolic(__entry->rate, RATE) + ) +); + +#endif /* _TRACE_HW_EVENT_PCI_CONTROLLER_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> |