diff options
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_wa.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_wa.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 10 |
3 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c index b2e71fa61c0a..a00af39f7538 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.c +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c @@ -72,6 +72,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, return IS_DISPLAY_VERx100(display, 1100, 1400); case INTEL_DISPLAY_WA_15018326506: return display->platform.battlemage; + case INTEL_DISPLAY_WA_14025769978: + return DISPLAY_VER(display) == 35; default: drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name); break; diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h index f648b00cb97d..a68c0bb7e516 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.h +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h @@ -27,6 +27,7 @@ enum intel_display_wa { INTEL_DISPLAY_WA_14011503117, INTEL_DISPLAY_WA_22014263786, INTEL_DISPLAY_WA_15018326506, + INTEL_DISPLAY_WA_14025769978, }; bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 18ad621f4b8a..155b308ed66f 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -964,8 +964,14 @@ static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg, lockdep_assert_held(&display->fbc.sys_cache.lock); - /* Cache read enable is set by default */ - reg |= FBC_SYS_CACHE_READ_ENABLE; + /* + * Wa_14025769978: + * Fixes: SoC hardware issue in read caching + * Workaround: disable cache read setting which is enabled by default. + */ + if (!intel_display_wa(display, 14025769978)) + /* Cache read enable is set by default */ + reg |= FBC_SYS_CACHE_READ_ENABLE; intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg); |