diff options
| -rw-r--r-- | arch/arm64/Kconfig | 5 | ||||
| -rw-r--r-- | arch/arm64/include/asm/fpsimdmacros.h | 38 |
2 files changed, 20 insertions, 23 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fe60738e5943..378e50fef247 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2247,10 +2247,15 @@ config ARM64_SVE booting the kernel. If unsure and you are not observing these symptoms, you should assume that it is safe to say Y. +config AS_HAS_SME + # Supported by LLVM 13+ and binutils 2.38+ + def_bool $(as-instr,.arch_extension sme) + config ARM64_SME bool "ARM Scalable Matrix Extension support" default y depends on ARM64_SVE + depends on AS_HAS_SME help The Scalable Matrix Extension (SME) is an extension to the AArch64 execution state which utilises a substantial subset of the SVE diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h index 4ba23e493cb6..4a9bf46e5291 100644 --- a/arch/arm64/include/asm/fpsimdmacros.h +++ b/arch/arm64/include/asm/fpsimdmacros.h @@ -149,47 +149,39 @@ pfalse p\np\().b .endm -/* SME instruction encodings for non-SME-capable assemblers */ -/* (pre binutils 2.38/LLVM 13) */ +/* Deprecated macros for SME instructions */ /* RDSVL X\nx, #\imm */ .macro _sme_rdsvl nx, imm - _check_general_reg \nx - _check_num (\imm), -0x20, 0x1f - .inst 0x04bf5800 \ - | (\nx) \ - | (((\imm) & 0x3f) << 5) + .arch_extension sme + rdsvl x\nx, #\imm .endm /* * STR (vector from ZA array): - * STR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL] + * STR ZA[W\nw, #\offset], [X\nxbase, #\offset, MUL VL] */ .macro _sme_str_zav nw, nxbase, offset=0 - _sme_check_wv \nw - _check_general_reg \nxbase - _check_num (\offset), -0x100, 0xff - .inst 0xe1200000 \ - | (((\nw) & 3) << 13) \ - | ((\nxbase) << 5) \ - | ((\offset) & 7) + .arch_extension sme + str za[w\nw, #\offset], [x\nxbase, #\offset, MUL VL] .endm /* * LDR (vector to ZA array): - * LDR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL] + * LDR ZA[w\nw, #\offset], [X\nxbase, #\offset, MUL VL] */ .macro _sme_ldr_zav nw, nxbase, offset=0 - _sme_check_wv \nw - _check_general_reg \nxbase - _check_num (\offset), -0x100, 0xff - .inst 0xe1000000 \ - | (((\nw) & 3) << 13) \ - | ((\nxbase) << 5) \ - | ((\offset) & 7) + .arch_extension sme + ldr za[w\nw, #\offset], [x\nxbase, #\offset, MUL VL] .endm /* + * SME2 instruction encodings for older assemblers. + * Supported by binutils 2.41+. + * Supported by LLVM 16+ + */ + +/* * LDR (ZT0) * * LDR ZT0, nx |