diff options
Diffstat (limited to 'Documentation/devicetree/bindings/display/msm')
11 files changed, 256 insertions, 615 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 97993feda193..a212f335d5ff 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,sa8775p-dp - qcom,sc7180-dp - qcom,sc7280-dp - qcom,sc7280-edp diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index b1bd372996d5..ab884e236429 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -125,6 +125,7 @@ allOf: enum: - qcom,adreno-gmu-635.0 - qcom,adreno-gmu-660.1 + - qcom,adreno-gmu-663.0 then: properties: reg: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml new file mode 100644 index 000000000000..58f8a01f29c7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -0,0 +1,241 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA87755P Display MDSS + +maintainers: + - Mahadevan <quic_mahap@quicinc.com> + +description: + SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DP interfaces and EDP etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sa8775p-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sa8775p-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sa8775p-dp + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sa8775p-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + + resets = <&dispcc_core_bcr>; + power-domains = <&dispcc_gdsc>; + + clocks = <&dispcc_ahb_clk>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc_mdp_clk>; + + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sa8775p-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_mdp_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdss0_mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss0>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + }; + + mdss0_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + displayport-controller@af54000 { + compatible = "qcom,sa8775p-dp"; + + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>; + + interrupt-parent = <&mdss0>; + interrupts = <12>; + + clocks = <&dispcc_mdss_ahb_clk>, + <&dispcc_dptx0_aux_clk>, + <&dispcc_dptx0_link_clk>, + <&dispcc_dptx0_link_intf_clk>, + <&dispcc_dptx0_pixel0_clk>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>; + + phys = <&mdss0_edp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index b0fbe86219d1..6902795b4e2c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -7,13 +7,21 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU on SC7280 maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Neil Armstrong <neil.armstrong@linaro.org> + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> - Krishna Manikandan <quic_mkrishn@quicinc.com> $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sc7280-dpu + enum: + - qcom,sc7280-dpu + - qcom,sc8280xp-dpu + - qcom,sm8350-dpu + - qcom,sm8450-dpu + - qcom,sm8550-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml deleted file mode 100644 index d19e3bec4600..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml +++ /dev/null @@ -1,122 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SC8280XP Display Processing Unit - -maintainers: - - Bjorn Andersson <andersson@kernel.org> - -description: - Device tree bindings for SC8280XP Display Processing Unit. - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sc8280xp-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> - #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interconnect/qcom,sc8280xp.h> - #include <dt-bindings/power/qcom-rpmpd.h> - - display-controller@ae01000 { - compatible = "qcom,sc8280xp-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc0 DISP_CC_MDSS_AHB_CLK>, - <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc0 DISP_CC_MDSS_MDP_CLK>, - <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, - <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SC8280XP_MMCX>; - - interrupt-parent = <&mdss0>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - endpoint { - remote-endpoint = <&mdss0_dp0_in>; - }; - }; - - port@4 { - reg = <4>; - endpoint { - remote-endpoint = <&mdss0_dp1_in>; - }; - }; - - port@5 { - reg = <5>; - endpoint { - remote-endpoint = <&mdss0_dp3_in>; - }; - }; - - port@6 { - reg = <6>; - endpoint { - remote-endpoint = <&mdss0_dp2_in>; - }; - }; - }; - }; -... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml index 13146b3f053c..a88d22f30a60 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sm8150-dpu + enum: + - qcom,sm8150-dpu + - qcom,sm8250-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml deleted file mode 100644 index ffa5047e901f..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml +++ /dev/null @@ -1,99 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8250 Display DPU - -maintainers: - - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8250-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display ahb clock - - description: Display hf axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,dispcc-sm8250.h> - #include <dt-bindings/clock/qcom,gcc-sm8250.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interconnect/qcom,sm8250.h> - #include <dt-bindings/power/qcom,rpmhpd.h> - - display-controller@ae01000 { - compatible = "qcom,sm8250-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; -... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml deleted file mode 100644 index 96ef2d9c3512..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml +++ /dev/null @@ -1,120 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8350 Display DPU - -maintainers: - - Robert Foss <robert.foss@linaro.org> - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8350-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,dispcc-sm8350.h> - #include <dt-bindings/clock/qcom,gcc-sm8350.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interconnect/qcom,sm8350.h> - #include <dt-bindings/power/qcom,rpmhpd.h> - - display-controller@ae01000 { - compatible = "qcom,sm8350-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-460000000 { - opp-hz = /bits/ 64 <460000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; -... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml deleted file mode 100644 index 2a5d3daed0e1..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml +++ /dev/null @@ -1,139 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8450 Display DPU - -maintainers: - - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8450-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi - - description: Display sf axi - - description: Display ahb - - description: Display lut - - description: Display core - - description: Display vsync - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,sm8450-dispcc.h> - #include <dt-bindings/clock/qcom,gcc-sm8450.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/interconnect/qcom,sm8450.h> - #include <dt-bindings/power/qcom,rpmhpd.h> - - display-controller@ae01000 { - compatible = "qcom,sm8450-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-172000000{ - opp-hz = /bits/ 64 <172000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-325000000 { - opp-hz = /bits/ 64 <325000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-375000000 { - opp-hz = /bits/ 64 <375000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; -... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml deleted file mode 100644 index 16a541fca66f..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml +++ /dev/null @@ -1,133 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8550 Display DPU - -maintainers: - - Neil Armstrong <neil.armstrong@linaro.org> - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8550-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display AHB - - description: Display hf axi - - description: Display MDSS ahb - - description: Display lut - - description: Display core - - description: Display vsync - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,sm8550-dispcc.h> - #include <dt-bindings/clock/qcom,sm8550-gcc.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/power/qcom,rpmhpd.h> - - display-controller@ae01000 { - compatible = "qcom,sm8550-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-325000000 { - opp-hz = /bits/ 64 <325000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-375000000 { - opp-hz = /bits/ 64 <375000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-514000000 { - opp-hz = /bits/ 64 <514000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; -... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index c4087cc5abbd..01cf79bd754b 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -14,6 +14,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,x1e80100-dpu |