diff options
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
9 files changed, 201 insertions, 186 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index f5f03bf36413..9398aae49093 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -16,7 +16,9 @@ description: | properties: compatible: - const: nvidia,tegra124-emc + enum: + - nvidia,tegra114-emc + - nvidia,tegra124-emc reg: maxItems: 1 @@ -29,6 +31,9 @@ properties: items: - const: emc + interrupts: + maxItems: 1 + "#interconnect-cells": const: 0 @@ -164,153 +169,12 @@ patternProperties: nvidia,emc-configuration: description: EMC timing characterization data. These are the registers (see - section "15.6.2 EMC Registers" in the TRM) whose values need to + section "20.11.2 EMC Registers" in the Tegra114 TRM or section + "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to be specified, according to the board documentation. $ref: /schemas/types.yaml#/definitions/uint32-array - items: - - description: EMC_RC - - description: EMC_RFC - - description: EMC_RFC_SLR - - description: EMC_RAS - - description: EMC_RP - - description: EMC_R2W - - description: EMC_W2R - - description: EMC_R2P - - description: EMC_W2P - - description: EMC_RD_RCD - - description: EMC_WR_RCD - - description: EMC_RRD - - description: EMC_REXT - - description: EMC_WEXT - - description: EMC_WDV - - description: EMC_WDV_MASK - - description: EMC_QUSE - - description: EMC_QUSE_WIDTH - - description: EMC_IBDLY - - description: EMC_EINPUT - - description: EMC_EINPUT_DURATION - - description: EMC_PUTERM_EXTRA - - description: EMC_PUTERM_WIDTH - - description: EMC_PUTERM_ADJ - - description: EMC_CDB_CNTL_1 - - description: EMC_CDB_CNTL_2 - - description: EMC_CDB_CNTL_3 - - description: EMC_QRST - - description: EMC_QSAFE - - description: EMC_RDV - - description: EMC_RDV_MASK - - description: EMC_REFRESH - - description: EMC_BURST_REFRESH_NUM - - description: EMC_PRE_REFRESH_REQ_CNT - - description: EMC_PDEX2WR - - description: EMC_PDEX2RD - - description: EMC_PCHG2PDEN - - description: EMC_ACT2PDEN - - description: EMC_AR2PDEN - - description: EMC_RW2PDEN - - description: EMC_TXSR - - description: EMC_TXSRDLL - - description: EMC_TCKE - - description: EMC_TCKESR - - description: EMC_TPD - - description: EMC_TFAW - - description: EMC_TRPAB - - description: EMC_TCLKSTABLE - - description: EMC_TCLKSTOP - - description: EMC_TREFBW - - description: EMC_FBIO_CFG6 - - description: EMC_ODT_WRITE - - description: EMC_ODT_READ - - description: EMC_FBIO_CFG5 - - description: EMC_CFG_DIG_DLL - - description: EMC_CFG_DIG_DLL_PERIOD - - description: EMC_DLL_XFORM_DQS0 - - description: EMC_DLL_XFORM_DQS1 - - description: EMC_DLL_XFORM_DQS2 - - description: EMC_DLL_XFORM_DQS3 - - description: EMC_DLL_XFORM_DQS4 - - description: EMC_DLL_XFORM_DQS5 - - description: EMC_DLL_XFORM_DQS6 - - description: EMC_DLL_XFORM_DQS7 - - description: EMC_DLL_XFORM_DQS8 - - description: EMC_DLL_XFORM_DQS9 - - description: EMC_DLL_XFORM_DQS10 - - description: EMC_DLL_XFORM_DQS11 - - description: EMC_DLL_XFORM_DQS12 - - description: EMC_DLL_XFORM_DQS13 - - description: EMC_DLL_XFORM_DQS14 - - description: EMC_DLL_XFORM_DQS15 - - description: EMC_DLL_XFORM_QUSE0 - - description: EMC_DLL_XFORM_QUSE1 - - description: EMC_DLL_XFORM_QUSE2 - - description: EMC_DLL_XFORM_QUSE3 - - description: EMC_DLL_XFORM_QUSE4 - - description: EMC_DLL_XFORM_QUSE5 - - description: EMC_DLL_XFORM_QUSE6 - - description: EMC_DLL_XFORM_QUSE7 - - description: EMC_DLL_XFORM_ADDR0 - - description: EMC_DLL_XFORM_ADDR1 - - description: EMC_DLL_XFORM_ADDR2 - - description: EMC_DLL_XFORM_ADDR3 - - description: EMC_DLL_XFORM_ADDR4 - - description: EMC_DLL_XFORM_ADDR5 - - description: EMC_DLL_XFORM_QUSE8 - - description: EMC_DLL_XFORM_QUSE9 - - description: EMC_DLL_XFORM_QUSE10 - - description: EMC_DLL_XFORM_QUSE11 - - description: EMC_DLL_XFORM_QUSE12 - - description: EMC_DLL_XFORM_QUSE13 - - description: EMC_DLL_XFORM_QUSE14 - - description: EMC_DLL_XFORM_QUSE15 - - description: EMC_DLI_TRIM_TXDQS0 - - description: EMC_DLI_TRIM_TXDQS1 - - description: EMC_DLI_TRIM_TXDQS2 - - description: EMC_DLI_TRIM_TXDQS3 - - description: EMC_DLI_TRIM_TXDQS4 - - description: EMC_DLI_TRIM_TXDQS5 - - description: EMC_DLI_TRIM_TXDQS6 - - description: EMC_DLI_TRIM_TXDQS7 - - description: EMC_DLI_TRIM_TXDQS8 - - description: EMC_DLI_TRIM_TXDQS9 - - description: EMC_DLI_TRIM_TXDQS10 - - description: EMC_DLI_TRIM_TXDQS11 - - description: EMC_DLI_TRIM_TXDQS12 - - description: EMC_DLI_TRIM_TXDQS13 - - description: EMC_DLI_TRIM_TXDQS14 - - description: EMC_DLI_TRIM_TXDQS15 - - description: EMC_DLL_XFORM_DQ0 - - description: EMC_DLL_XFORM_DQ1 - - description: EMC_DLL_XFORM_DQ2 - - description: EMC_DLL_XFORM_DQ3 - - description: EMC_DLL_XFORM_DQ4 - - description: EMC_DLL_XFORM_DQ5 - - description: EMC_DLL_XFORM_DQ6 - - description: EMC_DLL_XFORM_DQ7 - - description: EMC_XM2CMDPADCTRL - - description: EMC_XM2CMDPADCTRL4 - - description: EMC_XM2CMDPADCTRL5 - - description: EMC_XM2DQPADCTRL2 - - description: EMC_XM2DQPADCTRL3 - - description: EMC_XM2CLKPADCTRL - - description: EMC_XM2CLKPADCTRL2 - - description: EMC_XM2COMPPADCTRL - - description: EMC_XM2VTTGENPADCTRL - - description: EMC_XM2VTTGENPADCTRL2 - - description: EMC_XM2VTTGENPADCTRL3 - - description: EMC_XM2DQSPADCTRL3 - - description: EMC_XM2DQSPADCTRL4 - - description: EMC_XM2DQSPADCTRL5 - - description: EMC_XM2DQSPADCTRL6 - - description: EMC_DSR_VTTGEN_DRV - - description: EMC_TXDSRVTTGEN - - description: EMC_FBIO_SPARE - - description: EMC_ZCAL_WAIT_CNT - - description: EMC_MRS_WAIT_CNT2 - - description: EMC_CTT - - description: EMC_CTT_DURATION - - description: EMC_CFG_PIPE - - description: EMC_DYN_SELF_REF_CONTROL - - description: EMC_QPOP + minItems: 97 + maxItems: 143 required: - clock-frequency @@ -318,9 +182,7 @@ patternProperties: - nvidia,emc-auto-cal-config2 - nvidia,emc-auto-cal-config3 - nvidia,emc-auto-cal-interval - - nvidia,emc-bgbias-ctl0 - nvidia,emc-cfg - - nvidia,emc-cfg-2 - nvidia,emc-ctt-term-ctrl - nvidia,emc-mode-1 - nvidia,emc-mode-2 @@ -344,6 +206,22 @@ required: - "#interconnect-cells" - operating-points-v2 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-emc + then: + patternProperties: + "^emc-timings-[0-9]+$": + patternProperties: + "^timing-[0-9]+$": + required: + - nvidia,emc-bgbias-ctl0 + - nvidia,emc-cfg-2 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 7b18b4d11e0a..f8747cebb680 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -19,7 +19,9 @@ description: | properties: compatible: - const: nvidia,tegra124-mc + enum: + - nvidia,tegra114-mc + - nvidia,tegra124-mc reg: maxItems: 1 @@ -64,29 +66,12 @@ patternProperties: nvidia,emem-configuration: $ref: /schemas/types.yaml#/definitions/uint32-array - description: | + description: Values to be written to the EMEM register block. See section - "15.6.1 MC Registers" in the TRM. - items: - - description: MC_EMEM_ARB_CFG - - description: MC_EMEM_ARB_OUTSTANDING_REQ - - description: MC_EMEM_ARB_TIMING_RCD - - description: MC_EMEM_ARB_TIMING_RP - - description: MC_EMEM_ARB_TIMING_RC - - description: MC_EMEM_ARB_TIMING_RAS - - description: MC_EMEM_ARB_TIMING_FAW - - description: MC_EMEM_ARB_TIMING_RRD - - description: MC_EMEM_ARB_TIMING_RAP2PRE - - description: MC_EMEM_ARB_TIMING_WAP2PRE - - description: MC_EMEM_ARB_TIMING_R2R - - description: MC_EMEM_ARB_TIMING_W2W - - description: MC_EMEM_ARB_TIMING_R2W - - description: MC_EMEM_ARB_TIMING_W2R - - description: MC_EMEM_ARB_DA_TURNS - - description: MC_EMEM_ARB_DA_COVERS - - description: MC_EMEM_ARB_MISC0 - - description: MC_EMEM_ARB_MISC1 - - description: MC_EMEM_ARB_RING1_THROTTLE + "20.11.1 MC Registers" in the Tegea114 TRM or + "15.6.1 MC Registers" in the Tegra124 TRM. + minItems: 18 + maxItems: 19 required: - clock-frequency diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 7b03b589168b..6c374e2b1543 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -32,6 +32,7 @@ properties: - nvidia,tegra186-mc - nvidia,tegra194-mc - nvidia,tegra234-mc + - nvidia,tegra238-mc - nvidia,tegra264-mc reg: @@ -269,6 +270,36 @@ allOf: - if: properties: compatible: + const: nvidia,tegra238-mc + then: + properties: + reg: + minItems: 10 + maxItems: 10 + description: 9 memory controller channels and 1 for stream-id registers + + reg-names: + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + + interrupts: + items: + - description: MC general interrupt + + interrupt-names: false + + - if: + properties: + compatible: const: nvidia,tegra264-mc then: properties: diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml index 55caf6905399..a33913fcd11f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml @@ -66,8 +66,8 @@ examples: - | memory-controller@7000f000 { compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400>, /* Controller registers */ - <0x58000000 0x02000000>; /* GART aperture */ + reg = <0x7000f000 0x400>, /* Controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ clocks = <&clock_controller 32>; clock-names = "mc"; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml index 4e4fb4acd7f9..7a653a011f03 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml @@ -52,6 +52,9 @@ properties: Should contain freqs and voltages and opp-supported-hw property, which is a bitfield indicating SoC speedo ID mask. +allOf: + - $ref: /schemas/thermal/thermal-cooling-devices.yaml + required: - compatible - reg @@ -59,7 +62,7 @@ required: - clock-names - nvidia,memory-controller -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -90,4 +93,5 @@ examples: operating-points-v2 = <&dvfs_opp_table>; #interconnect-cells = <0>; + #cooling-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml new file mode 100644 index 000000000000..268d5ff958f9 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra210 SoC Memory Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split + into two 32 bit channels to support LPDDR3 and LPDDR4 with x16 subpartitions. + The MC handles memory requests for 34-bit virtual addresses from internal + clients and arbitrates among them to allocate memory bandwidth. + + Up to 8 GiB of physical memory can be supported. Security features such as + encryption of traffic to and from DRAM via general security apertures are + available for video and other secure applications. + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + items: + - enum: + - nvidia,tegra210-mc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + clock-names: + items: + - const: mc + + "#iommu-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#iommu-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + memory-controller@70019000 { + compatible = "nvidia,tegra210-mc"; + reg = <0x70019000 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_MC>; + clock-names = "mc"; + + #iommu-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml index 8e3822314b25..30ad2a858844 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml @@ -13,7 +13,7 @@ description: | Renesas SoCs contain one or more memory controllers. These memory controllers differ from one SoC variant to another, and are called by different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller - (DBSC3)", or "SDRAM Bus State Controller (SBSC)"). + (DBSC3)", or "SDRAM Bus State Controller (SBSC)". properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml index 7a84f5bb7284..cdeca4c795f3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml @@ -30,6 +30,8 @@ properties: - enum: - renesas,r9a09g056-xspi # RZ/V2N - renesas,r9a09g057-xspi # RZ/V2H(P) + - renesas,r9a09g077-xspi # RZ/T2H + - renesas,r9a09g087-xspi # RZ/N2H - const: renesas,r9a09g047-xspi reg: @@ -53,28 +55,38 @@ properties: - const: err_pulse clocks: - items: - - description: AHB clock - - description: AXI clock - - description: SPI clock - - description: Double speed SPI clock + oneOf: + - items: + - description: AHB clock + - description: AXI clock + - description: SPI clock + - description: Double speed SPI clock + - items: + - description: AHB clock + - description: SPI clock clock-names: - items: - - const: ahb - - const: axi - - const: spi - - const: spix2 + oneOf: + - items: + - const: ahb + - const: axi + - const: spi + - const: spix2 + - items: + - const: ahb + - const: spi power-domains: maxItems: 1 resets: + minItems: 1 items: - description: Hardware reset - description: AXI reset reset-names: + minItems: 1 items: - const: hresetn - const: aresetn @@ -109,6 +121,34 @@ required: - '#address-cells' - '#size-cells' +if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-xspi + - renesas,r9a09g087-xspi +then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 +else: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + resets: + minItems: 2 + reset-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 783ac984d898..4cd5af38abce 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -128,7 +128,7 @@ examples: "mout_mx_mspll_ccore", "mout_mclk_cdrex"; operating-points-v2 = <&dmc_opp_table>; - devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; |