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-rw-r--r--arch/arm64/boot/dts/nvidia/Makefile1
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132-norrin.dts5
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts111
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi19
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-smaug.dts7
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234.dtsi60
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi4
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts12
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra264.dtsi669
13 files changed, 743 insertions, 153 deletions
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 72c0cb5efa47..736a3f8a923f 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb
+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-lenovo-thinkedge-se70.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
index 683ac124523b..1f5222d43e62 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
@@ -18,6 +18,11 @@
stdout-path = "serial0:115200n8";
};
+ firmware {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
new file mode 100644
index 000000000000..185ec60d85c1
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra194-p3668-0001.dtsi"
+
+#include <dt-bindings/gpio/tegra194-gpio.h>
+
+/ {
+ model = "Lenovo ThinkEdge SE70";
+ compatible = "lenovo,thinkedge-se70", "nvidia,p3668-0001", "nvidia,tegra194";
+
+ aliases {
+ mmc1 = "/bus@0/mmc@3440000";
+ };
+
+ bus@0 {
+ /* 40-pin expansion header custom pinmux configuration */
+ pinmux@2430000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_hdr40>;
+
+ pinmux_hdr40: pinmux-hdr40 {
+ pin7 {
+ nvidia,pins = "aud_mclk_ps4";
+ nvidia,function = "aud";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pin11 {
+ nvidia,pins = "uart1_rts_pr4";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pin12 {
+ nvidia,pins = "dap5_sclk_pt5";
+ nvidia,function = "i2s5";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pin35 {
+ nvidia,pins = "dap5_fs_pu0";
+ nvidia,function = "i2s5";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pin36 {
+ nvidia,pins = "uart1_cts_pr5";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pin38 {
+ nvidia,pins = "dap5_din_pt7";
+ nvidia,function = "i2s5";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pin40 {
+ nvidia,pins = "dap5_dout_pt6";
+ nvidia,function = "i2s5";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
+ /* Configure i2c bus clock to 400kHz for carrier board peripherals */
+ i2c@3160000 {
+ clock-frequency = <400000>;
+ };
+
+ /* SDMMC3: External Micro SD card slot */
+ mmc@3440000 {
+ bus-width = <4>;
+ cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-1-8-v;
+ vmmc-supply = <&vdd_3v3_sd>;
+ status = "okay";
+ };
+ };
+
+ /* Fixed 3.3V power supply regulator for external Micro SD slot */
+ vdd_3v3_sd: regulator-vdd-3v3-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA194_MAIN_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ /* System 5V main supply, referenced by SOM and USB nodes */
+ vdd_5v0_sys: regulator-vdd-5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index ea6f397a2792..5462200f1176 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -2170,7 +2170,7 @@
compatible = "realtek,rt5658";
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA194_MAIN_GPIO(S, 5) IRQ_TYPE_EDGE_RISING>;
clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,jd-src = <2>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
index 16cf4414de59..6f4879c49da2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
@@ -1159,7 +1159,7 @@
};
};
- asrc_out6_port: port@c {
+ asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 849694f751d9..5e510f77b538 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1722,7 +1722,7 @@
nvidia,apbmisc = <&apbmisc>;
};
- iommu@10000000 {
+ smmu_iso: iommu@10000000 {
compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
reg = <0x0 0x10000000 0x0 0x800000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
@@ -1795,7 +1795,7 @@
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
- status = "disabled";
+ status = "okay";
};
smmu: iommu@12000000 {
@@ -1962,6 +1962,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
+ iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <0>;
@@ -1980,6 +1981,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
+ iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <1>;
@@ -1998,6 +2000,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
+ iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <2>;
@@ -2016,6 +2019,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
+ iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
nvidia,head = <3>;
@@ -2382,6 +2386,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2434,6 +2439,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2486,6 +2492,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2538,6 +2545,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2583,6 +2591,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
@@ -2629,6 +2638,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2674,6 +2684,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
@@ -2723,6 +2734,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
bus-range = <0x0 0xff>;
@@ -2771,6 +2783,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <8000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
@@ -3163,6 +3176,8 @@
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 15
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
always-on;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index f0b8c2c80aa5..e0fde65a552b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -25,6 +25,11 @@
stdout-path = "serial0:115200n8";
};
+ firmware {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0xc0000000>;
@@ -1467,6 +1472,8 @@
gpio-controller;
#gpio-cells = <2>;
+ system-power-controller;
+
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi
index f6cad29355e6..420858a8f4a8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi
@@ -67,7 +67,7 @@
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA234_MAIN_GPIO(AC, 5) IRQ_TYPE_EDGE_RISING>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
index 9ce55b4d2de8..97cede1fcb70 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
@@ -75,7 +75,7 @@
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ interrupts = <TEGRA234_MAIN_GPIO(F, 3) IRQ_TYPE_EDGE_RISING>;
clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "mclk";
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 04a95b6658ca..5e29316a4d75 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -1765,7 +1765,7 @@
};
};
- asrc_out6_port: port@c {
+ asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
@@ -3605,7 +3605,7 @@
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
@@ -3647,7 +3647,7 @@
<&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
@@ -3689,7 +3689,7 @@
<&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
@@ -3731,7 +3731,7 @@
<&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
- clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
@@ -4083,7 +4083,7 @@
reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
<0x0 0x0f440000 0x0 0x200000>; /* GICR */
interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#redistributor-regions = <1>;
#interrupt-cells = <3>;
@@ -4532,6 +4532,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4586,6 +4587,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4640,6 +4642,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4686,6 +4689,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
@@ -4734,6 +4738,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4788,6 +4793,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4842,6 +4848,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4896,6 +4903,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -4937,6 +4945,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
@@ -4983,6 +4992,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5037,6 +5047,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5083,6 +5094,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
@@ -5131,6 +5143,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5177,6 +5190,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
@@ -5225,6 +5239,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <16000>;
bus-range = <0x0 0xff>;
@@ -5271,6 +5286,7 @@
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
+ aspm-l1-entry-delay-ns = <32000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
@@ -5339,7 +5355,7 @@
#size-cells = <0>;
cpu0_0: cpu@0 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x00000>;
@@ -5358,7 +5374,7 @@
};
cpu0_1: cpu@100 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x00100>;
@@ -5377,7 +5393,7 @@
};
cpu0_2: cpu@200 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x00200>;
@@ -5396,7 +5412,7 @@
};
cpu0_3: cpu@300 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x00300>;
@@ -5415,7 +5431,7 @@
};
cpu1_0: cpu@10000 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x10000>;
@@ -5434,7 +5450,7 @@
};
cpu1_1: cpu@10100 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x10100>;
@@ -5453,7 +5469,7 @@
};
cpu1_2: cpu@10200 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x10200>;
@@ -5472,7 +5488,7 @@
};
cpu1_3: cpu@10300 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x10300>;
@@ -5491,7 +5507,7 @@
};
cpu2_0: cpu@20000 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x20000>;
@@ -5510,7 +5526,7 @@
};
cpu2_1: cpu@20100 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x20100>;
@@ -5529,7 +5545,7 @@
};
cpu2_2: cpu@20200 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x20200>;
@@ -5548,7 +5564,7 @@
};
cpu2_3: cpu@20300 {
- compatible = "arm,cortex-a78";
+ compatible = "arm,cortex-a78ae";
device_type = "cpu";
reg = <0x20300>;
@@ -5869,10 +5885,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gic>;
always-on;
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
index 7e2c3e66c2ab..58cd81bc33d7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
@@ -9,6 +9,10 @@
};
bus@0 {
+ dma-controller@8400000 {
+ status = "okay";
+ };
+
serial@c4e0000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
index df6555b6d0e0..3bd4c4cf2871 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
@@ -8,4 +8,16 @@
/ {
model = "NVIDIA Jetson AGX Thor Developer Kit";
compatible = "nvidia,p4071-0000+p3834-0008", "nvidia,p3834-0008", "nvidia,tegra264";
+
+ bus@a800000000 {
+ /* PCIe C2 to enable Ethernet */
+ pci@8420000 {
+ status = "okay";
+ };
+
+ /* PCIe C5 to enable NVME */
+ pci@8480000 {
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 06d8357bdf52..013228a81723 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -50,6 +50,76 @@
status = "disabled";
};
+ hte_lic: hardware-timestamp@8380000 {
+ compatible = "nvidia,tegra264-gte-lic";
+ reg = <0x0 0x08380000 0x0 0x10000>;
+ interrupts = <GIC_SPI 0x00000268 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,int-threshold = <1>;
+ #timestamp-cells = <1>;
+ status = "disabled";
+ };
+
+ gpcdma: dma-controller@8400000 {
+ compatible = "nvidia,tegra264-gpcdma";
+ reg = <0x0 0x08400000 0x0 0x210000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu1 0x00000800>;
+ iommu-map = <1 &smmu1 0x801 31>;
+ dma-coherent;
+ dma-channel-mask = <0xfffffffe>;
+ status = "disabled";
+ };
+
+ hsp_top: hsp@8800000 {
+ compatible = "nvidia,tegra264-hsp";
+ reg = <0x0 0x08800000 0x0 0xd0000>;
+ interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "doorbell", "shared0", "shared1", "shared2",
+ "shared3", "shared4", "shared5", "shared6",
+ "shared7";
+ #mbox-cells = <2>;
+ };
+
aconnect@9000000 {
compatible = "nvidia,tegra264-aconnect",
"nvidia,tegra210-aconnect";
@@ -1945,7 +2015,7 @@
};
};
- asrc_out6_port: port@c {
+ asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
@@ -3207,66 +3277,16 @@
};
};
- gpcdma: dma-controller@8400000 {
- compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
- reg = <0x0 0x08400000 0x0 0x210000>;
- interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- iommus = <&smmu1 0x00000800>;
- dma-coherent;
- dma-channel-mask = <0xfffffffe>;
+ hte_aon: hardware-timestamp@c2b0000 {
+ compatible = "nvidia,tegra264-gte-aon";
+ reg = <0x0 0x0c2b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 0x00000226 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,int-threshold = <1>;
+ #timestamp-cells = <1>;
+ nvidia,gpio-controller = <&gpio_aon>;
status = "disabled";
};
- hsp_top: hsp@8800000 {
- compatible = "nvidia,tegra264-hsp";
- reg = <0x0 0x08800000 0x0 0xd0000>;
- interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "doorbell", "shared0", "shared1", "shared2",
- "shared3", "shared4", "shared5", "shared6",
- "shared7";
- #mbox-cells = <2>;
- };
-
rtc: rtc@c2c0000 {
compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x0c2c0000 0x0 0x10000>;
@@ -3277,50 +3297,6 @@
status = "disabled";
};
- gpio_main: gpio@c300000 {
- compatible = "nvidia,tegra264-gpio";
- reg = <0x00 0x0c300000 0x0 0x4000>,
- <0x00 0x0c310000 0x0 0x4000>;
- reg-names = "security", "gpio";
- wakeup-parent = <&pmc>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
serial@c4e0000 {
compatible = "nvidia,tegra264-utc";
reg = <0x0 0x0c4e0000 0x0 0x8000>,
@@ -3380,6 +3356,11 @@
status = "disabled";
};
+ pinmux_aon: pinmux@c7a2000 {
+ compatible = "nvidia,tegra264-pinmux-aon";
+ reg = <0x0 0x0c7a2000 0x0 0x2000>;
+ };
+
pmc: pmc@c800000 {
compatible = "nvidia,tegra264-pmc";
reg = <0x0 0x0c800000 0x0 0x100000>,
@@ -3437,7 +3418,7 @@
cmdqv1: cmdqv@5200000 {
compatible = "nvidia,tegra264-cmdqv";
reg = <0x00 0x5200000 0x0 0x830000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
@@ -3457,7 +3438,7 @@
cmdqv2: cmdqv@6200000 {
compatible = "nvidia,tegra264-cmdqv";
reg = <0x00 0x6200000 0x0 0x830000>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
@@ -3530,7 +3511,7 @@
cmdqv0: cmdqv@a200000 {
compatible = "nvidia,tegra264-cmdqv";
reg = <0x00 0xa200000 0x0 0x830000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
@@ -3550,7 +3531,7 @@
cmdqv4: cmdqv@b200000 {
compatible = "nvidia,tegra264-cmdqv";
reg = <0x00 0xb200000 0x0 0x830000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
@@ -3586,6 +3567,55 @@
status = "disabled";
};
+ pinmux_main: pinmux@c281000 {
+ compatible = "nvidia,tegra264-pinmux-main";
+ reg = <0x00 0x0c281000 0x0 0xc000>;
+ };
+
+ gpio_main: gpio@c300000 {
+ compatible = "nvidia,tegra264-gpio";
+ reg = <0x00 0x0c300000 0x0 0x4000>,
+ <0x00 0x0c310000 0x0 0x4000>;
+ reg-names = "security", "gpio";
+ wakeup-parent = <&pmc>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
i2c14: i2c@c410000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c410000 0x0 0x10000>;
@@ -3807,6 +3837,69 @@
};
};
+ /* VISION MMIO */
+ bus@8180000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>, /* MMIO (256 MiB) */
+ <0x100 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
+ <0x200 0x00000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
+
+ host1x@1200000 {
+ compatible = "nvidia,tegra264-host1x";
+ reg = <0x0 0x1200000 0x0 0x10000>,
+ <0x0 0x1210000 0x0 0x10000>,
+ <0x0 0x1240000 0x0 0x10000>;
+ reg-names = "common", "hypervisor", "vm";
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
+ "syncpt5", "syncpt6", "syncpt7", "host1x";
+ clocks = <&bpmp TEGRA264_CLK_HOST1X>;
+ clock-names = "host1x";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x000 0x00000000 0x00 0x08000000 0x00 0x01000000>,
+ <0x000 0x02800000 0x00 0x0a800000 0x00 0x00800000>;
+
+ interconnects = <&mc TEGRA264_MEMORY_CLIENT_HOST1XR &emc>;
+ interconnect-names = "dma-mem";
+ iommus = <&smmu1 TEGRA264_SID_HOST1X>;
+ dma-coherent;
+
+ /* Context isolation domains */
+ iommu-map = <0 &smmu1 (TEGRA264_SID_VIC + 1) 16>;
+
+ vic@50000 {
+ compatible = "nvidia,tegra264-vic";
+ reg = <0x0 0x50000 0x0 0x40000>;
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA264_CLK_VIC>;
+ clock-names = "vic";
+ resets = <&bpmp TEGRA264_RESET_VIC>;
+ reset-names = "vic";
+ power-domains = <&bpmp TEGRA264_POWER_DOMAIN_VIC>;
+ interconnects = <&mc TEGRA264_MEMORY_CLIENT_VICR &emc>,
+ <&mc TEGRA264_MEMORY_CLIENT_VICW &emc>;
+ interconnect-names = "dma-mem", "write";
+
+ iommus = <&smmu1 TEGRA264_SID_VIC>;
+ dma-coherent;
+ };
+ };
+ };
+
/* DISP_USB MMIO */
bus@8800000000 {
compatible = "simple-bus";
@@ -3831,7 +3924,7 @@
cmdqv3: cmdqv@6200000 {
compatible = "nvidia,tegra264-cmdqv";
reg = <0x00 0x6200000 0x0 0x830000>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
@@ -3862,6 +3955,11 @@
<0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
<0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
+ pinmux_uphy: pinmux@82e0000 {
+ compatible = "nvidia,tegra264-pinmux-uphy";
+ reg = <0x00 0x082e0000 0x0 0x4000>;
+ };
+
gpio_uphy: gpio@8300000 {
compatible = "nvidia,tegra264-gpio-uphy";
reg = <0x00 0x08300000 0x0 0x2000>,
@@ -4051,6 +4149,28 @@
};
};
+ bpmp: bpmp {
+ compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";
+ mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB
+ TEGRA_HSP_DB_MASTER_BPMP>;
+ memory-region = <&shmem_bpmp>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ i2c {
+ compatible = "nvidia,tegra186-bpmp-i2c";
+ nvidia,bpmp-bus-id = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ thermal {
+ compatible = "nvidia,tegra186-bpmp-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -4068,9 +4188,10 @@
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
+ next-level-cache = <&l2c0>;
};
- cpu1: cpu@1 {
+ cpu1: cpu@10000 {
compatible = "arm,neoverse-v3ae";
device_type = "cpu";
reg = <0x10000>;
@@ -4083,29 +4204,327 @@
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
+ next-level-cache = <&l2c1>;
};
- };
- bpmp: bpmp {
- compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";
- mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB
- TEGRA_HSP_DB_MASTER_BPMP>;
- memory-region = <&shmem_bpmp>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
+ cpu2: cpu@20000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x20000>;
- i2c {
- compatible = "nvidia,tegra186-bpmp-i2c";
- nvidia,bpmp-bus-id = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c2>;
};
- thermal {
- compatible = "nvidia,tegra186-bpmp-thermal";
- #thermal-sensor-cells = <1>;
+ cpu3: cpu@30000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x30000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c3>;
+ };
+
+ cpu4: cpu@40000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x40000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c4>;
+ };
+
+ cpu5: cpu@50000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x50000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c5>;
+ };
+
+ cpu6: cpu@60000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x60000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c6>;
};
+
+ cpu7: cpu@70000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x70000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c7>;
+ };
+
+ cpu8: cpu@80000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x80000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c8>;
+ };
+
+ cpu9: cpu@90000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0x90000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c9>;
+ };
+
+ cpu10: cpu@a0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xa0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c10>;
+ };
+
+ cpu11: cpu@b0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xb0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c11>;
+ };
+
+ cpu12: cpu@c0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xc0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c12>;
+ };
+
+ cpu13: cpu@d0000 {
+ compatible = "arm,neoverse-v3ae";
+ device_type = "cpu";
+ reg = <0xd0000>;
+
+ enable-method = "psci";
+
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2c13>;
+ };
+
+ l2c0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c2: l2-cache-2 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c3: l2-cache-3 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c4: l2-cache-4 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c5: l2-cache-5 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c6: l2-cache-6 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c7: l2-cache-7 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c8: l2-cache-8 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c9: l2-cache-9 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c10: l2-cache-10 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c11: l2-cache-11 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c12: l2-cache-12 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
+ l2c13: l2-cache-13 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+
};
pmu {
generated by cgit v1.2.3 (git 2.0.4) at 2026-09-25 00:50:11 +0000