diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779a0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 41 |
1 files changed, 34 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 2c3fb34abb28..4b101a6dc49d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a779a0"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { @@ -60,7 +61,7 @@ pmu_a76 { compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; /* External SCIF clock - to be overridden by boards that provide it */ @@ -72,7 +73,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -90,6 +90,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a779a0-wdt", "renesas,rcar-gen4-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A779A0_CLK_OSC>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1128>; + status = "disabled"; + }; + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779a0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, @@ -2327,6 +2337,23 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + gpu: gpu@fd000000 { + compatible = "renesas,r8a779a0-gpu", + "img,img-ge7800", + "img,img-rogue"; + reg = <0 0xfd000000 0 0x40000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>, + <&cpg CPG_CORE R8A779A0_CLK_S3D1>, + <&cpg CPG_MOD 0>; + clock-names = "core", "mem", "sys"; + power-domains = <&sysc R8A779A0_PD_3DG_A>, + <&sysc R8A779A0_PD_3DG_B>; + power-domain-names = "a", "b"; + resets = <&cpg 0>; + status = "disabled"; + }; + fcpvd0: fcp@fea10000 { compatible = "renesas,fcpv"; reg = <0 0xfea10000 0 0x200>; @@ -3086,11 +3113,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; |