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-rw-r--r--arch/alpha/include/asm/xor.h24
-rw-r--r--arch/arm/include/asm/xor.h21
-rw-r--r--arch/arm64/include/asm/xor.h24
-rw-r--r--arch/loongarch/include/asm/xor.h40
-rw-r--r--arch/powerpc/include/asm/xor.h29
-rw-r--r--arch/riscv/include/asm/xor.h19
-rw-r--r--arch/s390/include/asm/xor.h19
-rw-r--r--arch/sparc/include/asm/xor.h44
-rw-r--r--arch/um/include/asm/xor.h8
-rw-r--r--arch/x86/include/asm/xor.h43
10 files changed, 0 insertions, 271 deletions
diff --git a/arch/alpha/include/asm/xor.h b/arch/alpha/include/asm/xor.h
deleted file mode 100644
index e517be577a09..000000000000
--- a/arch/alpha/include/asm/xor.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <asm/special_insns.h>
-#include <asm-generic/xor.h>
-
-extern struct xor_block_template xor_block_alpha;
-extern struct xor_block_template xor_block_alpha_prefetch;
-
-/*
- * Force the use of alpha_prefetch if EV6, as it is significantly faster in the
- * cold cache case.
- */
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- if (implver() == IMPLVER_EV6) {
- xor_force(&xor_block_alpha_prefetch);
- } else {
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_32regs);
- xor_register(&xor_block_alpha);
- xor_register(&xor_block_alpha_prefetch);
- }
-}
diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h
deleted file mode 100644
index 989c55872ef6..000000000000
--- a/arch/arm/include/asm/xor.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2001 Russell King
- */
-#include <asm-generic/xor.h>
-#include <asm/neon.h>
-
-extern struct xor_block_template xor_block_arm4regs;
-extern struct xor_block_template xor_block_neon;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- xor_register(&xor_block_arm4regs);
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_32regs);
-#ifdef CONFIG_KERNEL_MODE_NEON
- if (cpu_has_neon())
- xor_register(&xor_block_neon);
-#endif
-}
diff --git a/arch/arm64/include/asm/xor.h b/arch/arm64/include/asm/xor.h
deleted file mode 100644
index 4782c760bcac..000000000000
--- a/arch/arm64/include/asm/xor.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Authors: Jackie Liu <liuyun01@kylinos.cn>
- * Copyright (C) 2018,Tianjin KYLIN Information Technology Co., Ltd.
- */
-
-#include <asm-generic/xor.h>
-#include <asm/simd.h>
-
-extern struct xor_block_template xor_block_neon;
-extern struct xor_block_template xor_block_eor3;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_32regs);
- if (cpu_has_neon()) {
- if (cpu_have_named_feature(SHA3))
- xor_register(&xor_block_eor3);
- else
- xor_register(&xor_block_neon);
- }
-}
diff --git a/arch/loongarch/include/asm/xor.h b/arch/loongarch/include/asm/xor.h
deleted file mode 100644
index 7e32f72f8b03..000000000000
--- a/arch/loongarch/include/asm/xor.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2023 WANG Xuerui <git@xen0n.name>
- */
-#ifndef _ASM_LOONGARCH_XOR_H
-#define _ASM_LOONGARCH_XOR_H
-
-#include <asm/cpu-features.h>
-
-/*
- * For grins, also test the generic routines.
- *
- * More importantly: it cannot be ruled out at this point of time, that some
- * future (maybe reduced) models could run the vector algorithms slower than
- * the scalar ones, maybe for errata or micro-op reasons. It may be
- * appropriate to revisit this after one or two more uarch generations.
- */
-#include <asm-generic/xor.h>
-
-extern struct xor_block_template xor_block_lsx;
-extern struct xor_block_template xor_block_lasx;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_8regs_p);
- xor_register(&xor_block_32regs);
- xor_register(&xor_block_32regs_p);
-#ifdef CONFIG_CPU_HAS_LSX
- if (cpu_has_lsx)
- xor_register(&xor_block_lsx);
-#endif
-#ifdef CONFIG_CPU_HAS_LASX
- if (cpu_has_lasx)
- xor_register(&xor_block_lasx);
-#endif
-}
-
-#endif /* _ASM_LOONGARCH_XOR_H */
diff --git a/arch/powerpc/include/asm/xor.h b/arch/powerpc/include/asm/xor.h
deleted file mode 100644
index 3293ac87181c..000000000000
--- a/arch/powerpc/include/asm/xor.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- *
- * Copyright (C) IBM Corporation, 2012
- *
- * Author: Anton Blanchard <anton@au.ibm.com>
- */
-#ifndef _ASM_POWERPC_XOR_H
-#define _ASM_POWERPC_XOR_H
-
-#include <asm/cpu_has_feature.h>
-#include <asm-generic/xor.h>
-
-extern struct xor_block_template xor_block_altivec;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_8regs_p);
- xor_register(&xor_block_32regs);
- xor_register(&xor_block_32regs_p);
-#ifdef CONFIG_ALTIVEC
- if (cpu_has_feature(CPU_FTR_ALTIVEC))
- xor_register(&xor_block_altivec);
-#endif
-}
-
-#endif /* _ASM_POWERPC_XOR_H */
diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h
deleted file mode 100644
index 614d9209d078..000000000000
--- a/arch/riscv/include/asm/xor.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2021 SiFive
- */
-#include <asm/vector.h>
-#include <asm-generic/xor.h>
-
-extern struct xor_block_template xor_block_rvv;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_32regs);
-#ifdef CONFIG_RISCV_ISA_V
- if (has_vector())
- xor_register(&xor_block_rvv);
-#endif
-}
diff --git a/arch/s390/include/asm/xor.h b/arch/s390/include/asm/xor.h
deleted file mode 100644
index 4e2233f64da9..000000000000
--- a/arch/s390/include/asm/xor.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Optimited xor routines
- *
- * Copyright IBM Corp. 2016
- * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
- */
-#ifndef _ASM_S390_XOR_H
-#define _ASM_S390_XOR_H
-
-extern struct xor_block_template xor_block_xc;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- xor_force(&xor_block_xc);
-}
-
-#endif /* _ASM_S390_XOR_H */
diff --git a/arch/sparc/include/asm/xor.h b/arch/sparc/include/asm/xor.h
deleted file mode 100644
index f923b009fc24..000000000000
--- a/arch/sparc/include/asm/xor.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
- * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
- */
-#ifndef ___ASM_SPARC_XOR_H
-#define ___ASM_SPARC_XOR_H
-
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm/spitfire.h>
-
-extern struct xor_block_template xor_block_VIS;
-extern struct xor_block_template xor_block_niagara;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- /* Force VIS for everything except Niagara. */
- if (tlb_type == hypervisor &&
- (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
- sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
- sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
- sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
- sun4v_chip_type == SUN4V_CHIP_NIAGARA5))
- xor_force(&xor_block_niagara);
- else
- xor_force(&xor_block_VIS);
-}
-#else /* sparc64 */
-
-/* For grins, also test the generic routines. */
-#include <asm-generic/xor.h>
-
-extern struct xor_block_template xor_block_SPARC;
-
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_32regs);
- xor_register(&xor_block_SPARC);
-}
-#endif /* !sparc64 */
-#endif /* ___ASM_SPARC_XOR_H */
diff --git a/arch/um/include/asm/xor.h b/arch/um/include/asm/xor.h
deleted file mode 100644
index 99e5c7e1f475..000000000000
--- a/arch/um/include/asm/xor.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_UM_XOR_H
-#define _ASM_UM_XOR_H
-
-#include <asm/cpufeature.h>
-#include <../../x86/include/asm/xor.h>
-
-#endif
diff --git a/arch/x86/include/asm/xor.h b/arch/x86/include/asm/xor.h
deleted file mode 100644
index d1aab8275908..000000000000
--- a/arch/x86/include/asm/xor.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef _ASM_X86_XOR_H
-#define _ASM_X86_XOR_H
-
-#include <asm/cpufeature.h>
-#include <asm-generic/xor.h>
-
-extern struct xor_block_template xor_block_pII_mmx;
-extern struct xor_block_template xor_block_p5_mmx;
-extern struct xor_block_template xor_block_sse;
-extern struct xor_block_template xor_block_sse_pf64;
-extern struct xor_block_template xor_block_avx;
-
-/*
- * When SSE is available, use it as it can write around L2. We may also be able
- * to load into the L1 only depending on how the cpu deals with a load to a line
- * that is being prefetched.
- *
- * When AVX2 is available, force using it as it is better by all measures.
- *
- * 32-bit without MMX can fall back to the generic routines.
- */
-#define arch_xor_init arch_xor_init
-static __always_inline void __init arch_xor_init(void)
-{
- if (boot_cpu_has(X86_FEATURE_AVX) &&
- boot_cpu_has(X86_FEATURE_OSXSAVE)) {
- xor_force(&xor_block_avx);
- } else if (IS_ENABLED(CONFIG_X86_64) || boot_cpu_has(X86_FEATURE_XMM)) {
- xor_register(&xor_block_sse);
- xor_register(&xor_block_sse_pf64);
- } else if (boot_cpu_has(X86_FEATURE_MMX)) {
- xor_register(&xor_block_pII_mmx);
- xor_register(&xor_block_p5_mmx);
- } else {
- xor_register(&xor_block_8regs);
- xor_register(&xor_block_8regs_p);
- xor_register(&xor_block_32regs);
- xor_register(&xor_block_32regs_p);
- }
-}
-
-#endif /* _ASM_X86_XOR_H */
generated by cgit v1.2.3 (git 2.0.4) at 2026-07-21 00:05:53 +0000