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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu.h
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h176
1 files changed, 50 insertions, 126 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9f9774f58ce1..11a36c132905 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -34,12 +34,6 @@
#define pr_fmt(fmt) "amdgpu: " fmt
-#ifdef dev_fmt
-#undef dev_fmt
-#endif
-
-#define dev_fmt(fmt) "amdgpu: " fmt
-
#include "amdgpu_ctx.h"
#include <linux/atomic.h>
@@ -116,6 +110,7 @@
#include "amdgpu_reg_state.h"
#include "amdgpu_userq.h"
#include "amdgpu_eviction_fence.h"
+#include "amdgpu_ip.h"
#if defined(CONFIG_DRM_AMD_ISP)
#include "amdgpu_isp.h"
#endif
@@ -362,59 +357,6 @@ enum amdgpu_kiq_irq {
#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
#define MAX_KIQ_REG_TRY 1000
-int amdgpu_device_ip_set_clockgating_state(void *dev,
- enum amd_ip_block_type block_type,
- enum amd_clockgating_state state);
-int amdgpu_device_ip_set_powergating_state(void *dev,
- enum amd_ip_block_type block_type,
- enum amd_powergating_state state);
-void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
- u64 *flags);
-int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type);
-bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type);
-bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,
- enum amd_ip_block_type block_type);
-int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block);
-
-int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block);
-
-#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM
-
-struct amdgpu_ip_block_status {
- bool valid;
- bool sw;
- bool hw;
- bool late_initialized;
- bool hang;
-};
-
-struct amdgpu_ip_block_version {
- const enum amd_ip_block_type type;
- const u32 major;
- const u32 minor;
- const u32 rev;
- const struct amd_ip_funcs *funcs;
-};
-
-struct amdgpu_ip_block {
- struct amdgpu_ip_block_status status;
- const struct amdgpu_ip_block_version *version;
- struct amdgpu_device *adev;
-};
-
-int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
- enum amd_ip_block_type type,
- u32 major, u32 minor);
-
-struct amdgpu_ip_block *
-amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
- enum amd_ip_block_type type);
-
-int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
- const struct amdgpu_ip_block_version *ip_block_version);
-
/*
* BIOS.
*/
@@ -757,71 +699,6 @@ struct amdgpu_mmio_remap {
struct amdgpu_bo *bo;
};
-/* Define the HW IP blocks will be used in driver , add more if necessary */
-enum amd_hw_ip_block_type {
- GC_HWIP = 1,
- HDP_HWIP,
- SDMA0_HWIP,
- SDMA1_HWIP,
- SDMA2_HWIP,
- SDMA3_HWIP,
- SDMA4_HWIP,
- SDMA5_HWIP,
- SDMA6_HWIP,
- SDMA7_HWIP,
- LSDMA_HWIP,
- MMHUB_HWIP,
- ATHUB_HWIP,
- NBIO_HWIP,
- MP0_HWIP,
- MP1_HWIP,
- UVD_HWIP,
- VCN_HWIP = UVD_HWIP,
- JPEG_HWIP = VCN_HWIP,
- VCN1_HWIP,
- VCE_HWIP,
- VPE_HWIP,
- DF_HWIP,
- DCE_HWIP,
- OSSSYS_HWIP,
- SMUIO_HWIP,
- PWR_HWIP,
- NBIF_HWIP,
- THM_HWIP,
- CLK_HWIP,
- UMC_HWIP,
- RSMU_HWIP,
- XGMI_HWIP,
- DCI_HWIP,
- PCIE_HWIP,
- ISP_HWIP,
- MAX_HWIP
-};
-
-#define HWIP_MAX_INSTANCE 44
-
-#define HW_ID_MAX 300
-#define IP_VERSION_FULL(mj, mn, rv, var, srev) \
- (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
-#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
-#define IP_VERSION_MAJ(ver) ((ver) >> 24)
-#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
-#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
-#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
-#define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
-#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
-
-struct amdgpu_ip_map_info {
- /* Map of logical to actual dev instances/mask */
- uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
- int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
- enum amd_hw_ip_block_type block,
- int8_t inst);
- uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
- enum amd_hw_ip_block_type block,
- uint32_t mask);
-};
-
enum amdgpu_uid_type {
AMDGPU_UID_TYPE_XCD,
AMDGPU_UID_TYPE_AID,
@@ -836,6 +713,38 @@ struct amdgpu_uid {
struct amdgpu_device *adev;
};
+#define MAX_UMA_OPTION_NAME 28
+#define MAX_UMA_OPTION_ENTRIES 19
+
+#define AMDGPU_UMA_FLAG_AUTO BIT(1)
+#define AMDGPU_UMA_FLAG_CUSTOM BIT(0)
+
+/**
+ * struct amdgpu_uma_carveout_option - single UMA carveout option
+ * @name: Name of the carveout option
+ * @memory_carved_mb: Amount of memory carved in MB
+ * @flags: ATCS flags supported by this option
+ */
+struct amdgpu_uma_carveout_option {
+ char name[MAX_UMA_OPTION_NAME];
+ uint32_t memory_carved_mb;
+ uint8_t flags;
+};
+
+/**
+ * struct amdgpu_uma_carveout_info - table of available UMA carveout options
+ * @num_entries: Number of available options
+ * @uma_option_index: The index of the option currently applied
+ * @update_lock: Lock to serialize changes to the option
+ * @entries: The array of carveout options
+ */
+struct amdgpu_uma_carveout_info {
+ uint8_t num_entries;
+ uint8_t uma_option_index;
+ struct mutex update_lock;
+ struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES];
+};
+
struct amd_powerplay {
void *pp_handle;
const struct amd_pm_funcs *pp_funcs;
@@ -891,6 +800,7 @@ struct amdgpu_mqd_prop {
uint64_t eop_gpu_addr;
uint32_t hqd_pipe_priority;
uint32_t hqd_queue_priority;
+ uint32_t mqd_stride_size;
bool allow_tunneling;
bool hqd_active;
uint64_t shadow_addr;
@@ -1319,6 +1229,8 @@ struct amdgpu_device {
struct work_struct userq_reset_work;
struct amdgpu_uid *uid_info;
+ struct amdgpu_uma_carveout_info uma_info;
+
/* KFD
* Must be last --ends in a flexible-array member.
*/
@@ -1545,8 +1457,13 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
-#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
-#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
+#define amdgpu_asic_supports_baco(adev) \
+ ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0)
+#define amdgpu_asic_pre_asic_init(adev) \
+ { \
+ if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \
+ (adev)->asic_funcs->pre_asic_init((adev)); \
+ }
#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
@@ -1686,12 +1603,14 @@ int amdgpu_acpi_init(struct amdgpu_device *adev);
void amdgpu_acpi_fini(struct amdgpu_device *adev);
bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
bool amdgpu_acpi_is_power_shift_control_supported(void);
+bool amdgpu_acpi_is_set_uma_allocation_size_supported(void);
int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
u8 perf_req, bool advertise);
int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
u8 dev_state, bool drv_state);
int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
enum amdgpu_ss ss_state);
+int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type);
int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
u64 *tmr_size);
@@ -1720,6 +1639,7 @@ static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { re
static inline void amdgpu_acpi_detect(void) { }
static inline void amdgpu_acpi_release(void) { }
static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
+static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; }
static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
u8 dev_state, bool drv_state) { return 0; }
static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
@@ -1727,6 +1647,10 @@ static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,
{
return 0;
}
+static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type)
+{
+ return -EINVAL;
+}
static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
#endif
generated by cgit v1.2.3 (git 2.0.4) at 2026-06-04 05:20:28 +0000