diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mes_userqueue.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 65 |
1 files changed, 43 insertions, 22 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 64cae89357b6..f2309d72bbe6 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -59,7 +59,8 @@ err_reserve_bo_failed: } static int -mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr, +mes_userq_create_wptr_mapping(struct amdgpu_device *adev, + struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue, uint64_t wptr) { @@ -93,8 +94,28 @@ mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr, return ret; } - queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj->obj); + ret = amdgpu_bo_reserve(wptr_obj->obj, true); + if (ret) { + DRM_ERROR("Failed to reserve wptr bo\n"); + return ret; + } + + /* TODO use eviction fence instead of pinning. */ + ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n"); + goto unresv_bo; + } + + queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); + amdgpu_bo_unreserve(wptr_obj->obj); + return 0; + +unresv_bo: + amdgpu_bo_unreserve(wptr_obj->obj); + return ret; + } static int convert_to_mes_priority(int priority) @@ -112,9 +133,9 @@ static int convert_to_mes_priority(int priority) } } -static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_map(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_userq_obj *ctx = &queue->fw_obj; struct amdgpu_mqd_prop *userq_props = queue->userq_prop; @@ -157,9 +178,9 @@ static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr, return 0; } -static int mes_userq_unmap(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct mes_remove_queue_input queue_input; struct amdgpu_userq_obj *ctx = &queue->fw_obj; @@ -223,7 +244,7 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, amdgpu_mes_lock(&adev->mes); r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false, - &hung_db_num, db_array); + &hung_db_num, db_array, 0); amdgpu_mes_unlock(&adev->mes); if (r) { dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); @@ -251,10 +272,10 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, return r; } -static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, - struct drm_amdgpu_userq_in *args_in, - struct amdgpu_usermode_queue *queue) +static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, + struct drm_amdgpu_userq_in *args_in) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; struct drm_amdgpu_userq_in *mqd_user = args_in; @@ -300,7 +321,7 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, goto free_mqd; } - r = amdgpu_userq_input_va_validate(queue, compute_mqd->eop_va, + r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va, 2048); if (r) goto free_mqd; @@ -341,11 +362,11 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, userq_props->tmz_queue = mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; - r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->shadow_va, + r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, shadow_info.shadow_size); if (r) goto free_mqd; - r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->csa_va, + r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, shadow_info.csa_size); if (r) goto free_mqd; @@ -366,7 +387,7 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, r = -ENOMEM; goto free_mqd; } - r = amdgpu_userq_input_va_validate(queue, mqd_sdma_v11->csa_va, + r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 32); if (r) goto free_mqd; @@ -391,7 +412,7 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, } /* FW expects WPTR BOs to be mapped into GART */ - r = mes_userq_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr); + r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); if (r) { DRM_ERROR("Failed to create WPTR mapping\n"); goto free_ctx; @@ -411,18 +432,18 @@ free_props: return r; } -static void -mes_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; + amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); kfree(queue->userq_prop); amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); } -static int mes_userq_preempt(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct mes_suspend_gang_input queue_input; struct amdgpu_userq_obj *ctx = &queue->fw_obj; @@ -466,9 +487,9 @@ out: return r; } -static int mes_userq_restore(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_restore(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct mes_resume_gang_input queue_input; struct amdgpu_userq_obj *ctx = &queue->fw_obj; |