diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_hdmi.c | 38 |
1 files changed, 14 insertions, 24 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index f1fc9669238f..a32cb4d25bc7 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1832,7 +1832,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, bool has_hdmi_sink) { struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); - enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port); + struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; if (clock < 25000) return MODE_CLOCK_LOW; @@ -1854,11 +1854,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, return MODE_CLOCK_RANGE; /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ - if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200) + if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) return MODE_CLOCK_RANGE; /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ - if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800) + if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) return MODE_CLOCK_RANGE; /* @@ -2737,12 +2737,11 @@ static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_encoder_is_combo(encoder)) return GMBUS_PIN_1_BXT + port; - else if (intel_phy_is_tc(dev_priv, phy)) - return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); + else if (intel_encoder_is_tc(encoder)) + return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); return GMBUS_PIN_2_BXT; @@ -2750,9 +2749,7 @@ static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); + enum phy phy = intel_encoder_to_phy(encoder); u8 ddc_pin; switch (phy) { @@ -2776,10 +2773,9 @@ static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); + enum phy phy = intel_encoder_to_phy(encoder); - WARN_ON(port == PORT_C); + WARN_ON(encoder->port == PORT_C); /* * Pin mapping for RKL depends on which PCH is present. With TGP, the @@ -2796,10 +2792,9 @@ static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); - enum port port = encoder->port; - enum phy phy = intel_port_to_phy(i915, port); + enum phy phy = intel_encoder_to_phy(encoder); - drm_WARN_ON(&i915->drm, port == PORT_A); + drm_WARN_ON(&i915->drm, encoder->port == PORT_A); /* * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, @@ -2815,19 +2810,14 @@ static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - - return intel_port_to_phy(dev_priv, port) + 1; + return intel_encoder_to_phy(encoder) + 1; } static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); + enum phy phy = intel_encoder_to_phy(encoder); - WARN_ON(port == PORT_B || port == PORT_C); + WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); /* * Pin mapping for ADL-S requires TC pins for all combo phy outputs |