diff options
Diffstat (limited to 'drivers/pinctrl/qcom')
72 files changed, 4539 insertions, 338 deletions
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 80af372a1147..18db350222b9 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -6,6 +6,7 @@ config PINCTRL_MSM depends on GPIOLIB # OF for pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF depends on OF + default ARCH_QCOM select QCOM_SCM select PINMUX select GENERIC_PINMUX_FUNCTIONS @@ -49,11 +50,12 @@ config PINCTRL_QCOM_SSBI_PMIC devices are pm8058 and pm8921. config PINCTRL_LPASS_LPI - tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + tristate "Qualcomm LPASS LPI pin controller driver" select PINMUX select PINCONF select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS + depends on PM_CLK depends on GPIOLIB help This is the pinctrl, pinmux, pinconf and gpiolib driver for the @@ -61,7 +63,7 @@ config PINCTRL_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. config PINCTRL_MILOS_LPASS_LPI - tristate "Qualcomm Technologies Inc Milos LPASS LPI pin controller driver" + tristate "Qualcomm Milos LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -71,7 +73,7 @@ config PINCTRL_MILOS_LPASS_LPI platform. config PINCTRL_SC7280_LPASS_LPI - tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin controller driver" + tristate "Qualcomm SC7280 and SM8350 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -81,7 +83,7 @@ config PINCTRL_SC7280_LPASS_LPI and SM8350 platforms. config PINCTRL_SDM660_LPASS_LPI - tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver" + tristate "Qualcomm SDM660 LPASS LPI pin controller driver" depends on GPIOLIB depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI @@ -91,7 +93,7 @@ config PINCTRL_SDM660_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform. config PINCTRL_SM4250_LPASS_LPI - tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver" + tristate "Qualcomm SM4250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -100,7 +102,7 @@ config PINCTRL_SM4250_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform. config PINCTRL_SDM670_LPASS_LPI - tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver" + tristate "Qualcomm SDM670 LPASS LPI pin controller driver" depends on GPIOLIB depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI @@ -110,7 +112,7 @@ config PINCTRL_SDM670_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform. config PINCTRL_SM6115_LPASS_LPI - tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" + tristate "Qualcomm SM6115 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -118,8 +120,17 @@ config PINCTRL_SM6115_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform. +config PINCTRL_SM6350_LPASS_LPI + tristate "Qualcomm SM6350 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6350 platform. + config PINCTRL_SM8250_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" + tristate "Qualcomm SM8250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -128,7 +139,7 @@ config PINCTRL_SM8250_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform. config PINCTRL_SM8450_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver" + tristate "Qualcomm SM8450 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -137,7 +148,7 @@ config PINCTRL_SM8450_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform. config PINCTRL_SC8280XP_LPASS_LPI - tristate "Qualcomm Technologies Inc SC8280XP LPASS LPI pin controller driver" + tristate "Qualcomm SC8280XP LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -146,7 +157,7 @@ config PINCTRL_SC8280XP_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform. config PINCTRL_SM8550_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver" + tristate "Qualcomm SM8550 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -156,7 +167,7 @@ config PINCTRL_SM8550_LPASS_LPI platform. config PINCTRL_SM8650_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8650 LPASS LPI pin controller driver" + tristate "Qualcomm SM8650 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 836cdeca1006..9409e678ec6d 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -4,6 +4,7 @@ if PINCTRL_MSM config PINCTRL_APQ8064 tristate "Qualcomm APQ8064 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8064 platform. @@ -11,13 +12,15 @@ config PINCTRL_APQ8064 config PINCTRL_APQ8084 tristate "Qualcomm APQ8084 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8084 platform. config PINCTRL_ELIZA - tristate "Qualcomm Technologies Inc Eliza pin controller driver" + tristate "Qualcomm Eliza pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) @@ -26,8 +29,9 @@ config PINCTRL_ELIZA If unsure, say N. config PINCTRL_GLYMUR - tristate "Qualcomm Technologies Inc Glymur pin controller driver" + tristate "Qualcomm Glymur pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) @@ -36,8 +40,9 @@ config PINCTRL_GLYMUR If unsure, say N. config PINCTRL_HAWI - tristate "Qualcomm Technologies Inc Hawi pin controller driver" + tristate "Qualcomm Hawi pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) @@ -48,13 +53,15 @@ config PINCTRL_HAWI config PINCTRL_IPQ4019 tristate "Qualcomm IPQ4019 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ4019 platform. config PINCTRL_IPQ5018 - tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver" + tristate "Qualcomm IPQ5018 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -64,29 +71,33 @@ config PINCTRL_IPQ5018 config PINCTRL_IPQ8064 tristate "Qualcomm IPQ8064 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. config PINCTRL_IPQ5210 - tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver" + tristate "Qualcomm IPQ5210 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc IPQ5210 platform. config PINCTRL_IPQ5332 - tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" + tristate "Qualcomm IPQ5332 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc IPQ5332 platform. config PINCTRL_IPQ5424 - tristate "Qualcomm Technologies, Inc. IPQ5424 pin controller driver" + tristate "Qualcomm IPQ5424 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -94,8 +105,9 @@ config PINCTRL_IPQ5424 IPQ5424. config PINCTRL_IPQ8074 - tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" + tristate "Qualcomm IPQ8074 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -103,8 +115,9 @@ config PINCTRL_IPQ8074 IPQ8074. config PINCTRL_IPQ6018 - tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver" + tristate "Qualcomm IPQ6018 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -112,17 +125,29 @@ config PINCTRL_IPQ6018 IPQ6018. config PINCTRL_IPQ9574 - tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver" + tristate "Qualcomm IPQ9574 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the Qualcomm Technologies Inc. IPQ9574 platform. Select this for IPQ9574. +config PINCTRL_IPQ9650 + tristate "Qualcomm IPQ9650 pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ9650 platform. Select this for + IPQ9650. + config PINCTRL_KAANAPALI - tristate "Qualcomm Technologies Inc Kaanapali pin controller driver" + tristate "Qualcomm Kaanapali pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -131,6 +156,7 @@ config PINCTRL_KAANAPALI config PINCTRL_MSM8226 tristate "Qualcomm 8226 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -139,6 +165,7 @@ config PINCTRL_MSM8226 config PINCTRL_MSM8660 tristate "Qualcomm 8660 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8660 platform. @@ -146,12 +173,14 @@ config PINCTRL_MSM8660 config PINCTRL_MSM8960 tristate "Qualcomm 8960 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8960 platform. config PINCTRL_MDM9607 tristate "Qualcomm 9607 pin controller driver" + default ARCH_QCOM if ARM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 9607 platform. @@ -159,6 +188,7 @@ config PINCTRL_MDM9607 config PINCTRL_MDM9615 tristate "Qualcomm 9615 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 9615 platform. @@ -166,6 +196,7 @@ config PINCTRL_MDM9615 config PINCTRL_MSM8X74 tristate "Qualcomm 8x74 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8974 platform. @@ -173,12 +204,14 @@ config PINCTRL_MSM8X74 config PINCTRL_MSM8909 tristate "Qualcomm 8909 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8909 platform. config PINCTRL_MSM8916 tristate "Qualcomm 8916 pin controller driver" + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. @@ -192,6 +225,7 @@ config PINCTRL_MSM8917 config PINCTRL_MSM8953 tristate "Qualcomm 8953 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8953 platform. @@ -201,6 +235,7 @@ config PINCTRL_MSM8953 config PINCTRL_MSM8976 tristate "Qualcomm 8976 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8976 platform. @@ -210,6 +245,7 @@ config PINCTRL_MSM8976 config PINCTRL_MSM8994 tristate "Qualcomm 8994 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8994 platform. The @@ -218,6 +254,7 @@ config PINCTRL_MSM8994 config PINCTRL_MSM8996 tristate "Qualcomm MSM8996 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8996 platform. @@ -225,13 +262,23 @@ config PINCTRL_MSM8996 config PINCTRL_MSM8998 tristate "Qualcomm MSM8998 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8998 platform. +config PINCTRL_NORD + tristate "Qualcomm Nord pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux and pinconf driver for the Qualcomm + TLMM block found on the Qualcomm NORD platforms. + config PINCTRL_QCM2290 tristate "Qualcomm QCM2290 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found in the Qualcomm QCM2290 platform. @@ -239,48 +286,54 @@ config PINCTRL_QCM2290 config PINCTRL_QCS404 tristate "Qualcomm QCS404 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found in the Qualcomm QCS404 platform. config PINCTRL_QCS615 - tristate "Qualcomm Technologies QCS615 pin controller driver" + tristate "Qualcomm QCS615 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found on the Qualcomm QCS615 platform. config PINCTRL_QCS8300 - tristate "Qualcomm Technologies QCS8300 pin controller driver" + tristate "Qualcomm QCS8300 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux and pinconf driver for the Qualcomm TLMM block found on the Qualcomm QCS8300 platform. config PINCTRL_QDF2XXX - tristate "Qualcomm Technologies QDF2xxx pin controller driver" + tristate "Qualcomm QDF2xxx pin controller driver" depends on ACPI + default ARCH_QCOM if ARM64 help This is the GPIO driver for the TLMM block found on the Qualcomm Technologies QDF2xxx SOCs. config PINCTRL_QDU1000 - tristate "Qualcomm Technologies Inc QDU1000/QRU1000 pin controller driver" + tristate "Qualcomm QDU1000/QRU1000 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf, and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc QDU1000 and QRU1000 platforms. config PINCTRL_SA8775P - tristate "Qualcomm Technologies Inc SA8775P pin controller driver" + tristate "Qualcomm SA8775P pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux and pinconf driver for the Qualcomm TLMM block found on the Qualcomm SA8775P platforms. config PINCTRL_SAR2130P - tristate "Qualcomm Technologies Inc SAR2130P pin controller driver" + tristate "Qualcomm SAR2130P pin controller driver" depends on ARM64 || COMPILE_TEST help This is the pinctrl, pinmux, pinconf and gpiolib driver for the @@ -288,202 +341,238 @@ config PINCTRL_SAR2130P Technologies Inc SAR2130P platform. config PINCTRL_SC7180 - tristate "Qualcomm Technologies Inc SC7180 pin controller driver" + tristate "Qualcomm SC7180 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC7180 platform. config PINCTRL_SC7280 - tristate "Qualcomm Technologies Inc SC7280 pin controller driver" + tristate "Qualcomm SC7280 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC7280 platform. config PINCTRL_SC8180X - tristate "Qualcomm Technologies Inc SC8180x pin controller driver" + tristate "Qualcomm SC8180x pin controller driver" depends on (OF || ACPI) depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC8180x platform. config PINCTRL_SC8280XP - tristate "Qualcomm Technologies Inc SC8280xp pin controller driver" + tristate "Qualcomm SC8280xp pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC8280xp platform. config PINCTRL_SDM660 - tristate "Qualcomm Technologies Inc SDM660 pin controller driver" + tristate "Qualcomm SDM660 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM660 platform. config PINCTRL_SDM670 - tristate "Qualcomm Technologies Inc SDM670 pin controller driver" + tristate "Qualcomm SDM670 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM670 platform. config PINCTRL_SDM845 - tristate "Qualcomm Technologies Inc SDM845 pin controller driver" + tristate "Qualcomm SDM845 pin controller driver" depends on (OF || ACPI) depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM845 platform. config PINCTRL_SDX55 - tristate "Qualcomm Technologies Inc SDX55 pin controller driver" + tristate "Qualcomm SDX55 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX55 platform. config PINCTRL_SDX65 - tristate "Qualcomm Technologies Inc SDX65 pin controller driver" + tristate "Qualcomm SDX65 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX65 platform. config PINCTRL_SDX75 - tristate "Qualcomm Technologies Inc SDX75 pin controller driver" + tristate "Qualcomm SDX75 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX75 platform. +config PINCTRL_SHIKRA + tristate "Qualcomm Shikra pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) + found on the Qualcomm Technologies Inc Shikra platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_SM4450 - tristate "Qualcomm Technologies Inc SM4450 pin controller driver" + tristate "Qualcomm SM4450 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM4450 platform. config PINCTRL_SM6115 - tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver" + tristate "Qualcomm SM6115,SM4250 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6115 and SM4250 platforms. config PINCTRL_SM6125 - tristate "Qualcomm Technologies Inc SM6125 pin controller driver" + tristate "Qualcomm SM6125 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6125 platform. config PINCTRL_SM6350 - tristate "Qualcomm Technologies Inc SM6350 pin controller driver" + tristate "Qualcomm SM6350 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6350 platform. config PINCTRL_SM6375 - tristate "Qualcomm Technologies Inc SM6375 pin controller driver" + tristate "Qualcomm SM6375 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6375 platform. config PINCTRL_SM7150 - tristate "Qualcomm Technologies Inc SM7150 pin controller driver" + tristate "Qualcomm SM7150 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM7150 platform. config PINCTRL_MILOS - tristate "Qualcomm Technologies Inc Milos pin controller driver" + tristate "Qualcomm Milos pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc Milos platform. config PINCTRL_SM8150 - tristate "Qualcomm Technologies Inc SM8150 pin controller driver" + tristate "Qualcomm SM8150 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8150 platform. config PINCTRL_SM8250 - tristate "Qualcomm Technologies Inc SM8250 pin controller driver" + tristate "Qualcomm SM8250 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8250 platform. config PINCTRL_SM8350 - tristate "Qualcomm Technologies Inc SM8350 pin controller driver" + tristate "Qualcomm SM8350 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8350 platform. config PINCTRL_SM8450 - tristate "Qualcomm Technologies Inc SM8450 pin controller driver" + tristate "Qualcomm SM8450 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8450 platform. config PINCTRL_SM8550 - tristate "Qualcomm Technologies Inc SM8550 pin controller driver" + tristate "Qualcomm SM8550 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8550 platform. config PINCTRL_SM8650 - tristate "Qualcomm Technologies Inc SM8650 pin controller driver" + tristate "Qualcomm SM8650 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8650 platform. config PINCTRL_SM8750 - tristate "Qualcomm Technologies Inc SM8750 pin controller driver" + tristate "Qualcomm SM8750 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8750 platform. config PINCTRL_X1E80100 - tristate "Qualcomm Technologies Inc X1E80100 pin controller driver" + tristate "Qualcomm X1E80100 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 84bda3ada874..93cc4e7965ca 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o +obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o @@ -37,6 +38,7 @@ obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o +obj-$(CONFIG_PINCTRL_NORD) += pinctrl-nord.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o @@ -57,12 +59,14 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o +obj-$(CONFIG_PINCTRL_SHIKRA) += pinctrl-shikra.o obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o +obj-$(CONFIG_PINCTRL_SM6350_LPASS_LPI) += pinctrl-sm6350-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index 3654913f1ae5..a47f3d4f1ea5 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -622,6 +622,7 @@ static const struct of_device_id apq8064_pinctrl_of_match[] = { { .compatible = "qcom,apq8064-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); static struct platform_driver apq8064_pinctrl_driver = { .driver = { @@ -646,4 +647,3 @@ module_exit(apq8064_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index 9fdbe6743512..e3c1f86aba7d 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -1198,6 +1198,7 @@ static const struct of_device_id apq8084_pinctrl_of_match[] = { { .compatible = "qcom,apq8084-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match); static struct platform_driver apq8084_pinctrl_driver = { .driver = { @@ -1221,4 +1222,3 @@ module_exit(apq8084_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c index dd8c04046b18..58545e14710e 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -54,30 +54,6 @@ .intr_detection_width = 2, \ } -#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .grp = PINCTRL_PINGROUP(#pg_name, \ - pg_name##_pins, \ - ARRAY_SIZE(pg_name##_pins)), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - #define UFS_RESET(pg_name, ctl, io) \ { \ .grp = PINCTRL_PINGROUP(#pg_name, \ @@ -563,15 +539,32 @@ enum eliza_functions { msm_mux_qup1_se0, msm_mux_qup1_se1, msm_mux_qup1_se2, + msm_mux_qup1_se2_l2_mira, + msm_mux_qup1_se2_l2_mirb, + msm_mux_qup1_se2_l3_mira, + msm_mux_qup1_se2_l3_mirb, msm_mux_qup1_se3, - msm_mux_qup1_se4, + msm_mux_qup1_se4_01, + msm_mux_qup1_se4_23, msm_mux_qup1_se5, msm_mux_qup1_se6, + msm_mux_qup1_se6_l1_mira, + msm_mux_qup1_se6_l1_mirb, + msm_mux_qup1_se6_l3_mira, + msm_mux_qup1_se6_l3_mirb, msm_mux_qup1_se7, + msm_mux_qup1_se7_l0_mira, + msm_mux_qup1_se7_l0_mirb, + msm_mux_qup1_se7_l1_mira, + msm_mux_qup1_se7_l1_mirb, msm_mux_qup2_se0, msm_mux_qup2_se1, msm_mux_qup2_se2, msm_mux_qup2_se3, + msm_mux_qup2_se3_l0_mira, + msm_mux_qup2_se3_l0_mirb, + msm_mux_qup2_se3_l1_mira, + msm_mux_qup2_se3_l1_mirb, msm_mux_qup2_se4, msm_mux_qup2_se5, msm_mux_qup2_se6, @@ -978,15 +971,35 @@ static const char *const qup1_se1_groups[] = { }; static const char *const qup1_se2_groups[] = { - "gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gpio42", "gpio30", + "gpio52", "gpio53", "gpio40", "gpio42", "gpio30", +}; + +static const char *const qup1_se2_l2_mira_groups[] = { + "gpio54", +}; + +static const char *const qup1_se2_l2_mirb_groups[] = { + "gpio52", +}; + +static const char *const qup1_se2_l3_mira_groups[] = { + "gpio55", +}; + +static const char *const qup1_se2_l3_mirb_groups[] = { + "gpio53", }; static const char *const qup1_se3_groups[] = { "gpio44", "gpio45", "gpio46", "gpio47", }; -static const char *const qup1_se4_groups[] = { - "gpio36", "gpio37", "gpio37", "gpio36", +static const char *const qup1_se4_01_groups[] = { + "gpio36", "gpio37", +}; + +static const char *const qup1_se4_23_groups[] = { + "gpio36", "gpio37", }; static const char *const qup1_se5_groups[] = { @@ -994,11 +1007,43 @@ static const char *const qup1_se5_groups[] = { }; static const char *const qup1_se6_groups[] = { - "gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55", + "gpio40", "gpio42", +}; + +static const char *const qup1_se6_l1_mira_groups[] = { + "gpio42", +}; + +static const char *const qup1_se6_l1_mirb_groups[] = { + "gpio54", +}; + +static const char *const qup1_se6_l3_mira_groups[] = { + "gpio40", +}; + +static const char *const qup1_se6_l3_mirb_groups[] = { + "gpio55", }; static const char *const qup1_se7_groups[] = { - "gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78", + "gpio78", "gpio114", +}; + +static const char *const qup1_se7_l0_mira_groups[] = { + "gpio81", +}; + +static const char *const qup1_se7_l0_mirb_groups[] = { + "gpio78", +}; + +static const char *const qup1_se7_l1_mira_groups[] = { + "gpio80", +}; + +static const char *const qup1_se7_l1_mirb_groups[] = { + "gpio114", }; static const char *const qup2_se0_groups[] = { @@ -1014,7 +1059,23 @@ static const char *const qup2_se2_groups[] = { }; static const char *const qup2_se3_groups[] = { - "gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116", + "gpio100", "gpio116", +}; + +static const char *const qup2_se3_l0_mira_groups[] = { + "gpio79", +}; + +static const char *const qup2_se3_l0_mirb_groups[] = { + "gpio116", +}; + +static const char *const qup2_se3_l1_mira_groups[] = { + "gpio97", +}; + +static const char *const qup2_se3_l1_mirb_groups[] = { + "gpio100", }; static const char *const qup2_se4_groups[] = { @@ -1236,15 +1297,32 @@ static const struct pinfunction eliza_functions[] = { MSM_PIN_FUNCTION(qup1_se0), MSM_PIN_FUNCTION(qup1_se1), MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se2_l2_mira), + MSM_PIN_FUNCTION(qup1_se2_l2_mirb), + MSM_PIN_FUNCTION(qup1_se2_l3_mira), + MSM_PIN_FUNCTION(qup1_se2_l3_mirb), MSM_PIN_FUNCTION(qup1_se3), - MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se4_01), + MSM_PIN_FUNCTION(qup1_se4_23), MSM_PIN_FUNCTION(qup1_se5), MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se6_l1_mira), + MSM_PIN_FUNCTION(qup1_se6_l1_mirb), + MSM_PIN_FUNCTION(qup1_se6_l3_mira), + MSM_PIN_FUNCTION(qup1_se6_l3_mirb), MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup1_se7_l0_mira), + MSM_PIN_FUNCTION(qup1_se7_l0_mirb), + MSM_PIN_FUNCTION(qup1_se7_l1_mira), + MSM_PIN_FUNCTION(qup1_se7_l1_mirb), MSM_PIN_FUNCTION(qup2_se0), MSM_PIN_FUNCTION(qup2_se1), MSM_PIN_FUNCTION(qup2_se2), MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se3_l0_mira), + MSM_PIN_FUNCTION(qup2_se3_l0_mirb), + MSM_PIN_FUNCTION(qup2_se3_l1_mira), + MSM_PIN_FUNCTION(qup2_se3_l1_mirb), MSM_PIN_FUNCTION(qup2_se4), MSM_PIN_FUNCTION(qup2_se5), MSM_PIN_FUNCTION(qup2_se6), @@ -1322,33 +1400,33 @@ static const struct msm_pingroup eliza_groups[] = { [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _), [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _), [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _), - [36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), - [37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), - [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), - [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), - [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), + [36] = PINGROUP(36, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, sdc2, _, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, sdc2, _, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _), - [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6_l1_mira, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _), [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _), [44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _), [45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _), [46] = PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _), [47] = PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _), - [48] = PINGROUP(48, _, _, _, _, _, _, _, _, _, _, _), - [49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, sdc2, _, _, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, sdc2, _, _, _, _, _, _, _, _, _, _), [50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), - [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _), - [52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), - [53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _), - [54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_traceclk, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _), - [55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _), + [51] = PINGROUP(51, sdc2, _, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), + [53] = PINGROUP(53, qup1_se2, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_traceclk, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _), [56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _), [57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _), [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _), [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _), [60] = PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _), [61] = PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _), - [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, sdc2, _, _, _, _, _, _, _, _, _, _), [63] = PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _, _, _, _, _), [64] = PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _), [65] = PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _), @@ -1364,10 +1442,10 @@ static const struct msm_pingroup eliza_groups[] = { [75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _), [76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _), [77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _), - [78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _), - [79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _), - [80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _), - [81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup1_se7, qup1_se7_l0_mirb, _, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _, _, _, _, _, _), [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _), [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _), [84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _), @@ -1383,10 +1461,10 @@ static const struct msm_pingroup eliza_groups[] = { [94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _), [95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _), [96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), - [97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, _, _, _), [98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _), [99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _), - [100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _), + [100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _), [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _), @@ -1400,9 +1478,9 @@ static const struct msm_pingroup eliza_groups[] = { [111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _), [112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _), [113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _), - [114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _), + [114] = PINGROUP(114, qup1_se7, qup1_se7_l1_mirb, _, qdss_gpio_tracedata, _, _, _, _, _, _, _), [115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _), - [116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _), + [116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3_l0_mirb, _, _, _, _, _, _, _), [117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _), [118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _), [119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _), @@ -1519,6 +1597,7 @@ static const struct of_device_id eliza_tlmm_of_match[] = { { .compatible = "qcom,eliza-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match); static struct platform_driver eliza_tlmm_driver = { .driver = { @@ -1542,4 +1621,3 @@ module_exit(eliza_tlmm_exit); MODULE_DESCRIPTION("QTI Eliza TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c index 9838c7839923..20f076e59375 100644 --- a/drivers/pinctrl/qcom/pinctrl-glymur.c +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -1777,6 +1777,7 @@ static const struct of_device_id glymur_tlmm_of_match[] = { { .compatible = "qcom,mahua-tlmm", .data = &mahua_tlmm }, { }, }; +MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match); static int glymur_tlmm_probe(struct platform_device *pdev) { @@ -1811,4 +1812,3 @@ module_exit(glymur_tlmm_exit); MODULE_DESCRIPTION("QTI Glymur TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-hawi.c b/drivers/pinctrl/qcom/pinctrl-hawi.c index 5c7894f3b9cb..cdde69e954a7 100644 --- a/drivers/pinctrl/qcom/pinctrl-hawi.c +++ b/drivers/pinctrl/qcom/pinctrl-hawi.c @@ -1584,6 +1584,7 @@ static const struct of_device_id hawi_tlmm_of_match[] = { { .compatible = "qcom,hawi-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match); static struct platform_driver hawi_tlmm_driver = { .driver = { @@ -1607,4 +1608,3 @@ module_exit(hawi_tlmm_exit); MODULE_DESCRIPTION("QTI Hawi TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 05fdd73b951e..adf7c8631f72 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -702,6 +702,7 @@ static const struct of_device_id ipq4019_pinctrl_of_match[] = { { .compatible = "qcom,ipq4019-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match); static struct platform_driver ipq4019_pinctrl_driver = { .driver = { @@ -725,4 +726,3 @@ module_exit(ipq4019_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c index cc83f9362a85..9a42e343ff17 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -1072,6 +1072,7 @@ static const struct of_device_id ipq6018_pinctrl_of_match[] = { { .compatible = "qcom,ipq6018-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match); static struct platform_driver ipq6018_pinctrl_driver = { .driver = { @@ -1095,4 +1096,3 @@ module_exit(ipq6018_pinctrl_exit); MODULE_DESCRIPTION("QTI ipq6018 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c index 0a9e357e64c6..78d320d56be6 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -624,6 +624,7 @@ static const struct of_device_id ipq8064_pinctrl_of_match[] = { { .compatible = "qcom,ipq8064-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); static struct platform_driver ipq8064_pinctrl_driver = { .driver = { @@ -648,4 +649,3 @@ module_exit(ipq8064_pinctrl_exit); MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c index 64ce8ea8f544..0b95f52adcc3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8074.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -1033,6 +1033,7 @@ static const struct of_device_id ipq8074_pinctrl_of_match[] = { { .compatible = "qcom,ipq8074-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match); static struct platform_driver ipq8074_pinctrl_driver = { .driver = { @@ -1056,4 +1057,3 @@ module_exit(ipq8074_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9650.c b/drivers/pinctrl/qcom/pinctrl-ipq9650.c new file mode 100644 index 000000000000..64e443aa31b2 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq9650.c @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + }, \ + .nfuncs = 10, \ + } + +static const struct pinctrl_pin_desc ipq9650_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); + +enum ipq9650_functions { + msm_mux_atest_char_start, + msm_mux_atest_char_status0, + msm_mux_atest_char_status1, + msm_mux_atest_char_status2, + msm_mux_atest_char_status3, + msm_mux_atest_tic_en, + msm_mux_audio_pri_mclk_in0, + msm_mux_audio_pri_mclk_out0, + msm_mux_audio_pri_mclk_in1, + msm_mux_audio_pri_mclk_out1, + msm_mux_audio_pri, + msm_mux_audio_sec, + msm_mux_audio_sec_mclk_in0, + msm_mux_audio_sec_mclk_out0, + msm_mux_audio_sec_mclk_in1, + msm_mux_audio_sec_mclk_out1, + msm_mux_core_voltage_0, + msm_mux_core_voltage_1, + msm_mux_core_voltage_2, + msm_mux_core_voltage_3, + msm_mux_core_voltage_4, + msm_mux_cri_rng0, + msm_mux_cri_rng1, + msm_mux_cri_rng2, + msm_mux_dbg_out_clk, + msm_mux_gcc_plltest_bypassnl, + msm_mux_gcc_plltest_resetn, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_mdc_mst, + msm_mux_mdc_slv0, + msm_mux_mdc_slv1, + msm_mux_mdio_mst, + msm_mux_mdio_slv, + msm_mux_mdio_slv0, + msm_mux_mdio_slv1, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk_req_n, + msm_mux_pcie2_wake, + msm_mux_pcie3_clk_req_n, + msm_mux_pcie3_wake, + msm_mux_pcie4_clk_req_n, + msm_mux_pcie4_wake, + msm_mux_pll_bist_sync, + msm_mux_pll_test, + msm_mux_pwm, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs_n, + msm_mux_qup_se0, + msm_mux_qup_se1, + msm_mux_qup_se2, + msm_mux_qup_se3, + msm_mux_qup_se4, + msm_mux_qup_se5, + msm_mux_qup_se6, + msm_mux_qup_se7, + msm_mux_resout, + msm_mux_rx_los0, + msm_mux_rx_los1, + msm_mux_rx_los2, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_tsens_max, + msm_mux_tsn, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char *const atest_char_start_groups[] = { + "gpio21", +}; + +static const char *const atest_char_status0_groups[] = { + "gpio33", +}; + +static const char *const atest_char_status1_groups[] = { + "gpio35", +}; + +static const char *const atest_char_status2_groups[] = { + "gpio22", +}; + +static const char *const atest_char_status3_groups[] = { + "gpio23", +}; + +static const char *const atest_tic_en_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_in0_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_out0_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_in1_groups[] = { + "gpio51", +}; + +static const char *const audio_pri_mclk_out1_groups[] = { + "gpio51", +}; + +static const char *const audio_pri_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const audio_sec_mclk_in0_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_out0_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_in1_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_out1_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char *const core_voltage_0_groups[] = { + "gpio16", +}; + +static const char *const core_voltage_1_groups[] = { + "gpio17", +}; + +static const char *const core_voltage_2_groups[] = { + "gpio33", +}; + +static const char *const core_voltage_3_groups[] = { + "gpio34", +}; + +static const char *const core_voltage_4_groups[] = { + "gpio35", +}; + +static const char *const cri_rng0_groups[] = { + "gpio6", +}; + +static const char *const cri_rng1_groups[] = { + "gpio7", +}; + +static const char *const cri_rng2_groups[] = { + "gpio8", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio46", +}; + +static const char *const gcc_plltest_bypassnl_groups[] = { + "gpio33", +}; + +static const char *const gcc_plltest_resetn_groups[] = { + "gpio35", +}; + +static const char *const gcc_tlmm_groups[] = { + "gpio34", +}; + +static const char *const mdc_mst_groups[] = { + "gpio22", +}; + +static const char *const mdc_slv0_groups[] = { + "gpio20", +}; + +static const char *const mdc_slv1_groups[] = { + "gpio14", +}; + +static const char *const mdio_mst_groups[] = { + "gpio23", +}; + +static const char *const mdio_slv_groups[] = { + "gpio46", + "gpio47", +}; + +static const char *const mdio_slv0_groups[] = { + "gpio21", +}; + +static const char *const mdio_slv1_groups[] = { + "gpio15", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio24", +}; + +static const char *const pcie0_wake_groups[] = { + "gpio26", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio27", +}; + +static const char *const pcie1_wake_groups[] = { + "gpio29", +}; + +static const char *const pcie2_clk_req_n_groups[] = { + "gpio51", +}; + +static const char *const pcie2_wake_groups[] = { + "gpio53", +}; + +static const char *const pcie3_clk_req_n_groups[] = { + "gpio40", +}; + +static const char *const pcie3_wake_groups[] = { + "gpio42", +}; + +static const char *const pcie4_clk_req_n_groups[] = { + "gpio30", +}; + +static const char *const pcie4_wake_groups[] = { + "gpio32", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio47", +}; + +static const char *const pll_test_groups[] = { + "gpio39", +}; + +static const char *const pwm_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio16", + "gpio17", "gpio33", "gpio34", "gpio35", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", +}; + +static const char *const qdss_cti_trig_in_a0_groups[] = { + "gpio53", +}; + +static const char *const qdss_cti_trig_in_a1_groups[] = { + "gpio29", +}; + +static const char *const qdss_cti_trig_in_b0_groups[] = { + "gpio42", +}; + +static const char *const qdss_cti_trig_in_b1_groups[] = { + "gpio43", +}; + +static const char *const qdss_cti_trig_out_a0_groups[] = { + "gpio51", +}; + +static const char *const qdss_cti_trig_out_a1_groups[] = { + "gpio27", +}; + +static const char *const qdss_cti_trig_out_b0_groups[] = { + "gpio40", +}; + +static const char *const qdss_cti_trig_out_b1_groups[] = { + "gpio44", +}; + +static const char *const qdss_traceclk_a_groups[] = { + "gpio45", +}; + +static const char *const qdss_tracectl_a_groups[] = { + "gpio46", +}; + +static const char *const qdss_tracedata_a_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qspi_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qspi_clk_groups[] = { + "gpio5", +}; + +static const char *const qspi_cs_n_groups[] = { + "gpio4", +}; + +static const char *const qup_se0_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio51", "gpio53", +}; + +static const char *const qup_se1_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio27", "gpio29", +}; + +static const char *const qup_se2_groups[] = { + "gpio27", "gpio29", "gpio33", "gpio34", +}; + +static const char *const qup_se3_groups[] = { + "gpio16", "gpio17", "gpio20", "gpio21", +}; + +static const char *const qup_se4_groups[] = { + "gpio14", "gpio15", "gpio40", "gpio42", "gpio43", "gpio44", +}; + +static const char *const qup_se5_groups[] = { + "gpio40", "gpio42", "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char *const qup_se6_groups[] = { + "gpio43", "gpio44", "gpio51", "gpio53", +}; + +static const char *const qup_se7_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const resout_groups[] = { + "gpio49", +}; + +static const char *const rx_los0_groups[] = { + "gpio39", "gpio47", "gpio50", +}; + +static const char *const rx_los1_groups[] = { + "gpio38", "gpio46", +}; + +static const char *const rx_los2_groups[] = { + "gpio37", "gpio45", +}; + +static const char *const sdc_clk_groups[] = { + "gpio5", +}; + +static const char *const sdc_cmd_groups[] = { + "gpio4", +}; + +static const char *const sdc_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const tsens_max_groups[] = { + "gpio14", +}; + +static const char *const tsn_groups[] = { + "gpio50", +}; + +static const struct pinfunction ipq9650_functions[] = { + MSM_PIN_FUNCTION(atest_char_start), + MSM_PIN_FUNCTION(atest_char_status0), + MSM_PIN_FUNCTION(atest_char_status1), + MSM_PIN_FUNCTION(atest_char_status2), + MSM_PIN_FUNCTION(atest_char_status3), + MSM_PIN_FUNCTION(atest_tic_en), + MSM_PIN_FUNCTION(audio_pri_mclk_in0), + MSM_PIN_FUNCTION(audio_pri_mclk_out0), + MSM_PIN_FUNCTION(audio_pri_mclk_in1), + MSM_PIN_FUNCTION(audio_pri_mclk_out1), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(audio_sec_mclk_in0), + MSM_PIN_FUNCTION(audio_sec_mclk_out0), + MSM_PIN_FUNCTION(audio_sec_mclk_in1), + MSM_PIN_FUNCTION(audio_sec_mclk_out1), + MSM_PIN_FUNCTION(core_voltage_0), + MSM_PIN_FUNCTION(core_voltage_1), + MSM_PIN_FUNCTION(core_voltage_2), + MSM_PIN_FUNCTION(core_voltage_3), + MSM_PIN_FUNCTION(core_voltage_4), + MSM_PIN_FUNCTION(cri_rng0), + MSM_PIN_FUNCTION(cri_rng1), + MSM_PIN_FUNCTION(cri_rng2), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(gcc_plltest_bypassnl), + MSM_PIN_FUNCTION(gcc_plltest_resetn), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv0), + MSM_PIN_FUNCTION(mdc_slv1), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv), + MSM_PIN_FUNCTION(mdio_slv0), + MSM_PIN_FUNCTION(mdio_slv1), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pcie3_clk_req_n), + MSM_PIN_FUNCTION(pcie3_wake), + MSM_PIN_FUNCTION(pcie4_clk_req_n), + MSM_PIN_FUNCTION(pcie4_wake), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(pwm), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs_n), + MSM_PIN_FUNCTION(qup_se0), + MSM_PIN_FUNCTION(qup_se1), + MSM_PIN_FUNCTION(qup_se2), + MSM_PIN_FUNCTION(qup_se3), + MSM_PIN_FUNCTION(qup_se4), + MSM_PIN_FUNCTION(qup_se5), + MSM_PIN_FUNCTION(qup_se6), + MSM_PIN_FUNCTION(qup_se7), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx_los0), + MSM_PIN_FUNCTION(rx_los1), + MSM_PIN_FUNCTION(rx_los2), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(tsn), +}; + +static const struct msm_pingroup ipq9650_groups[] = { + [0] = PINGROUP(0, sdc_data, qspi_data, _, _, _, _, _, _, _), + [1] = PINGROUP(1, sdc_data, qspi_data, _, _, _, _, _, _, _), + [2] = PINGROUP(2, sdc_data, qspi_data, _, _, _, _, _, _, _), + [3] = PINGROUP(3, sdc_data, qspi_data, _, _, _, _, _, _, _), + [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _), + [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup_se0, pwm, _, cri_rng0, qdss_tracedata_a, _, _, _, _), + [7] = PINGROUP(7, qup_se0, pwm, _, cri_rng1, qdss_tracedata_a, _, _, _, _), + [8] = PINGROUP(8, qup_se0, pwm, _, cri_rng2, qdss_tracedata_a, _, _, _, _), + [9] = PINGROUP(9, qup_se0, pwm, _, qdss_tracedata_a, _, _, _, _, _), + [10] = PINGROUP(10, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _), + [11] = PINGROUP(11, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _), + [12] = PINGROUP(12, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _), + [13] = PINGROUP(13, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _), + [14] = PINGROUP(14, qup_se4, mdc_slv1, tsens_max, _, qdss_tracedata_a, _, _, _, _), + [15] = PINGROUP(15, qup_se4, mdio_slv1, _, qdss_tracedata_a, _, _, _, _, _), + [16] = PINGROUP(16, core_voltage_0, qup_se3, pwm, _, _, _, _, _, _), + [17] = PINGROUP(17, core_voltage_1, qup_se3, pwm, _, _, _, _, _, _), + [18] = PINGROUP(18, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, mdc_slv0, qup_se3, _, qdss_tracedata_a, _, _, _, _, _), + [21] = PINGROUP(21, mdio_slv0, qup_se3, atest_char_start, _, qdss_tracedata_a, _, _, _, _), + [22] = PINGROUP(22, mdc_mst, atest_char_status2, _, _, _, _, _, _, _), + [23] = PINGROUP(23, mdio_mst, atest_char_status3, _, _, _, _, _, _, _), + [24] = PINGROUP(24, pcie0_clk_req_n, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, pcie0_wake, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, pcie1_clk_req_n, qup_se2, qup_se1, _, qdss_cti_trig_out_a1, _, _, _, _), + [28] = PINGROUP(28, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, pcie1_wake, qup_se2, qup_se1, _, qdss_cti_trig_in_a1, _, _, _, _), + [30] = PINGROUP(30, pcie4_clk_req_n, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, pcie4_wake, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, core_voltage_2, qup_se2, gcc_plltest_bypassnl, pwm, atest_char_status0, _, _, _, _), + [34] = PINGROUP(34, core_voltage_3, qup_se2, gcc_tlmm, pwm, _, _, _, _, _), + [35] = PINGROUP(35, core_voltage_4, gcc_plltest_resetn, pwm, atest_char_status1, _, _, _, _, _), + [36] = PINGROUP(36, audio_pri, qup_se7, qdss_tracedata_a, _, _, _, _, _, _), + [37] = PINGROUP(37, audio_pri, qup_se7, audio_sec_mclk_out0, audio_sec_mclk_in0, rx_los2, qdss_tracedata_a, _, _, _), + [38] = PINGROUP(38, audio_pri, qup_se7, rx_los1, qdss_tracedata_a, _, _, _, _, _), + [39] = PINGROUP(39, audio_pri, qup_se7, audio_sec_mclk_out1, audio_sec_mclk_in1, pll_test, rx_los0, _, qdss_tracedata_a, _), + [40] = PINGROUP(40, pcie3_clk_req_n, qup_se5, qup_se4, _, qdss_cti_trig_out_b0, _, _, _, _), + [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, pcie3_wake, qup_se5, qup_se4, _, qdss_cti_trig_in_b0, _, _, _, _), + [43] = PINGROUP(43, qup_se4, qup_se6, pwm, _, qdss_cti_trig_in_b1, _, _, _, _), + [44] = PINGROUP(44, qup_se4, qup_se6, pwm, _, qdss_cti_trig_out_b1, _, _, _, _), + [45] = PINGROUP(45, qup_se5, rx_los2, audio_sec, pwm, _, qdss_traceclk_a, _, _, _), + [46] = PINGROUP(46, qup_se5, rx_los1, audio_sec, mdio_slv, pwm, dbg_out_clk, qdss_tracectl_a, _, _), + [47] = PINGROUP(47, qup_se5, rx_los0, audio_sec, mdio_slv, pll_bist_sync, pwm, _, _, _), + [48] = PINGROUP(48, qup_se5, audio_sec, pwm, _, _, _, _, _, _), + [49] = PINGROUP(49, resout, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, tsn, rx_los0, _, _, _, _, _, _, _), + [51] = PINGROUP(51, pcie2_clk_req_n, qup_se6, qup_se0, audio_pri_mclk_out1, audio_pri_mclk_in1, qdss_cti_trig_out_a0, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, pcie2_wake, qup_se6, qup_se0, audio_pri_mclk_out0, audio_pri_mclk_in0, qdss_cti_trig_in_a0, _, atest_tic_en, _), +}; + +static const struct msm_pinctrl_soc_data ipq9650_tlmm = { + .pins = ipq9650_pins, + .npins = ARRAY_SIZE(ipq9650_pins), + .functions = ipq9650_functions, + .nfunctions = ARRAY_SIZE(ipq9650_functions), + .groups = ipq9650_groups, + .ngroups = ARRAY_SIZE(ipq9650_groups), + .ngpios = 54, +}; + +static const struct of_device_id ipq9650_tlmm_of_match[] = { + { .compatible = "qcom,ipq9650-tlmm", }, + {}, +}; + +static int ipq9650_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq9650_tlmm); +} + +static struct platform_driver ipq9650_tlmm_driver = { + .driver = { + .name = "ipq9650-tlmm", + .of_match_table = ipq9650_tlmm_of_match, + }, + .probe = ipq9650_tlmm_probe, +}; + +static int __init ipq9650_tlmm_init(void) +{ + return platform_driver_register(&ipq9650_tlmm_driver); +} +arch_initcall(ipq9650_tlmm_init); + +static void __exit ipq9650_tlmm_exit(void) +{ + platform_driver_unregister(&ipq9650_tlmm_driver); +} +module_exit(ipq9650_tlmm_exit); + +MODULE_DESCRIPTION("QTI IPQ9650 TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-kaanapali.c b/drivers/pinctrl/qcom/pinctrl-kaanapali.c index 5cc45b9c55ab..e95ac064b84c 100644 --- a/drivers/pinctrl/qcom/pinctrl-kaanapali.c +++ b/drivers/pinctrl/qcom/pinctrl-kaanapali.c @@ -1774,6 +1774,7 @@ static const struct of_device_id kaanapali_tlmm_of_match[] = { { .compatible = "qcom,kaanapali-tlmm",}, {}, }; +MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match); static struct platform_driver kaanapali_tlmm_driver = { .driver = { @@ -1797,4 +1798,3 @@ module_exit(kaanapali_tlmm_exit); MODULE_DESCRIPTION("QTI Kaanapali TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 76aed3296279..5fd4a4eba654 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -11,10 +11,13 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/seq_file.h> +#include <linux/cleanup.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinmux.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "../pinctrl-utils.h" @@ -22,7 +25,6 @@ #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 struct lpi_pinctrl { struct device *dev; @@ -31,15 +33,14 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); const struct lpi_pinctrl_variant_data *data; }; -static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) +static void __iomem *lpi_gpio_reg(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr) { u32 pin_offset; @@ -48,22 +49,34 @@ static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, else pin_offset = LPI_TLMM_REG_OFFSET * pin; - return ioread32(state->tlmm_base + pin_offset + addr); + return state->tlmm_base + pin_offset + addr; } -static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr, unsigned int val) +static void lpi_gpio_read_reg(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr, u32 *val) { - u32 pin_offset; + *val = ioread32(lpi_gpio_reg(state, pin, addr)); +} - if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) - pin_offset = state->data->groups[pin].pin_offset; - else - pin_offset = LPI_TLMM_REG_OFFSET * pin; +static void lpi_gpio_write_reg(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr, + unsigned int val) +{ + iowrite32(val, lpi_gpio_reg(state, pin, addr)); +} - iowrite32(val, state->tlmm_base + pin_offset + addr); +static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr, u32 *val) +{ + int ret; - return 0; + ret = pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + + lpi_gpio_read_reg(state, pin, addr, val); + + return pm_runtime_put_autosuspend(state->dev); } static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { @@ -107,8 +120,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, { struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g = &pctrl->data->groups[group]; - u32 val; - int i, pin = g->pin; + u32 io_val, val; + int i, pin = g->pin, ret; for (i = 0; i < g->nfuncs; i++) { if (g->funcs[i] == function) @@ -118,8 +131,12 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, if (WARN_ON(i == g->nfuncs)) return -EINVAL; - mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + ret = pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + + guard(mutex)(&pctrl->lock); + lpi_gpio_read_reg(pctrl, pin, LPI_GPIO_CFG_REG, &val); /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +146,25 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, */ if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + lpi_gpio_read_reg(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + lpi_gpio_write_reg(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + lpi_gpio_write_reg(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } } u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + lpi_gpio_write_reg(pctrl, pin, LPI_GPIO_CFG_REG, val); - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } static const struct pinmux_ops lpi_gpio_pinmux_ops = { @@ -162,11 +180,15 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, unsigned int param = pinconf_to_config_param(*config); struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); unsigned int arg = 0; + u32 ctl_reg; int is_out; int pull; - u32 ctl_reg; + int ret; + + ret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; - ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); is_out = ctl_reg & LPI_GPIO_OE_MASK; pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); @@ -197,6 +219,7 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, } *config = pinconf_to_config_packed(param, arg); + return 0; } @@ -206,7 +229,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, { unsigned long sval; void __iomem *reg; - int slew_offset; + int slew_offset, ret; if (slew > LPI_SLEW_RATE_MAX) { dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", @@ -220,9 +243,15 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; + else if (g->slew_base_spare_1) + reg = pctrl->slew_base + LPI_SPARE_1_REG; else reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; + ret = pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + mutex_lock(&pctrl->lock); sval = ioread32(reg); @@ -232,7 +261,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, mutex_unlock(&pctrl->lock); - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, @@ -242,8 +271,8 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; bool value, output_enabled = false; const struct lpi_pingroup *g; - int i, ret; u32 val; + int i, ret; g = &pctrl->data->groups[group]; for (i = 0; i < nconfs; i++) { @@ -287,23 +316,26 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, * As per Hardware Programming Guide, when configuring pin as output, * set the pin value before setting output-enable (OE). */ + ret = pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + + guard(mutex)(&pctrl->lock); if (output_enabled) { val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + lpi_gpio_write_reg(pctrl, group, LPI_GPIO_VALUE_REG, val); } - mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + lpi_gpio_read_reg(pctrl, group, LPI_GPIO_CFG_REG, &val); u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + lpi_gpio_write_reg(pctrl, group, LPI_GPIO_CFG_REG, val); - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } static const struct pinconf_ops lpi_gpio_pinconf_ops = { @@ -352,9 +384,14 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state = gpiochip_get_data(chip); + u32 val; + int ret; + + ret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + return val & LPI_GPIO_VALUE_IN_MASK; } static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) @@ -397,7 +434,9 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, pctldev = pctldev ? : state->ctrl; pindesc = pctldev->desc->pins[offset]; - ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg)) + return; + is_out = ctl_reg & LPI_GPIO_OE_MASK; func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); @@ -480,9 +519,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data = data; pctrl->dev = &pdev->dev; - pctrl->clks[0].id = "core"; - pctrl->clks[1].id = "audio"; - pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -495,13 +531,19 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } - ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret = devm_pm_clk_create(dev); if (ret) return ret; - ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); + ret = of_pm_clk_add_clks(dev); + if (ret < 0 && ret != -ENODEV) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + ret = devm_pm_runtime_enable(dev); if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + return ret; pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; @@ -540,7 +582,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) err_pinctrl: mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); return ret; } @@ -552,7 +593,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) int i; mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); for (i = 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index f48368492861..6ba0c4eba984 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -16,6 +16,7 @@ struct platform_device; struct pinctrl_pin_desc; #define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_SPARE_1_REG 0xc000 #define LPI_TLMM_REG_OFFSET 0x1000 #define LPI_SLEW_RATE_MAX 0x03 #define LPI_SLEW_BITS_SIZE 0x02 @@ -47,6 +48,7 @@ struct pinctrl_pin_desc; { \ .pin = id, \ .slew_offset = soff, \ + .slew_base_spare_1 = false, \ .funcs = (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -62,6 +64,7 @@ struct pinctrl_pin_desc; { \ .pin = id, \ .slew_offset = soff, \ + .slew_base_spare_1 = false, \ .funcs = (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -73,6 +76,22 @@ struct pinctrl_pin_desc; .pin_offset = poff, \ } +#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \ + { \ + .pin = id, \ + .slew_offset = soff, \ + .slew_base_spare_1 = true, \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + .pin_offset = 0, \ + } + /* * Slew rate control is done in the same register as rest of the * pin configuration. @@ -87,6 +106,7 @@ struct lpi_pingroup { unsigned int *funcs; unsigned int nfuncs; unsigned int pin_offset; + bool slew_base_spare_1; }; struct lpi_function { diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c index 5794b0a11010..ce61eb415755 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9607.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -1050,6 +1050,7 @@ static const struct of_device_id mdm9607_pinctrl_of_match[] = { { .compatible = "qcom,mdm9607-tlmm", }, { } }; +MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match); static struct platform_driver mdm9607_pinctrl_driver = { .driver = { @@ -1073,4 +1074,3 @@ module_exit(mdm9607_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm mdm9607 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c index 729fe3d7e14e..f87e4d9a8f4f 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c @@ -439,6 +439,7 @@ static const struct of_device_id mdm9615_pinctrl_of_match[] = { { .compatible = "qcom,mdm9615-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match); static struct platform_driver mdm9615_pinctrl_driver = { .driver = { @@ -463,4 +464,3 @@ module_exit(mdm9615_pinctrl_exit); MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); MODULE_DESCRIPTION("Qualcomm MDM9615 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c index 3bf6fe0cf1bb..72b8ffd97860 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -203,10 +205,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-milos-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-milos.c b/drivers/pinctrl/qcom/pinctrl-milos.c index 74b5253257af..f5079a0ce0a3 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos.c +++ b/drivers/pinctrl/qcom/pinctrl-milos.c @@ -1310,6 +1310,7 @@ static const struct of_device_id milos_tlmm_of_match[] = { { .compatible = "qcom,milos-tlmm" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, milos_tlmm_of_match); static struct platform_driver milos_tlmm_driver = { .driver = { @@ -1333,4 +1334,3 @@ module_exit(milos_tlmm_exit); MODULE_DESCRIPTION("QTI Milos TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, milos_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 45b3a2763eb8..11db6564c44d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1012,10 +1012,8 @@ static void msm_gpio_irq_ack(struct irq_data *d) static void msm_gpio_irq_eoi(struct irq_data *d) { - d = d->parent_data; - - if (d) - d->chip->irq_eoi(d); + if (d->parent_data) + irq_chip_eoi_parent(d); } static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d, @@ -1593,11 +1591,11 @@ int msm_pinctrl_probe(struct platform_device *pdev, pctrl->desc.pins = pctrl->soc->pins; pctrl->desc.npins = pctrl->soc->npins; - pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); - if (IS_ERR(pctrl->pctrl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pctrl->pctrl); - } + ret = devm_pinctrl_register_and_init(&pdev->dev, &pctrl->desc, + pctrl, &pctrl->pctrl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Couldn't register pinctrl driver\n"); for (i = 0; i < soc_data->nfunctions; i++) { func = &soc_data->functions[i]; @@ -1607,6 +1605,11 @@ int msm_pinctrl_probe(struct platform_device *pdev, return ret; } + ret = pinctrl_enable(pctrl->pctrl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Couldn't enable pinctrl driver\n"); + ret = msm_gpio_init(pctrl); if (ret) return ret; diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index d27b7599ea83..6f02e7c2499e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -645,6 +645,7 @@ static const struct of_device_id msm8226_pinctrl_of_match[] = { { .compatible = "qcom,msm8226-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match); static struct platform_driver msm8226_pinctrl_driver = { .driver = { @@ -669,4 +670,3 @@ module_exit(msm8226_pinctrl_exit); MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>"); MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c index 5ded00396cd9..5b28a1c21a88 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -974,6 +974,7 @@ static const struct of_device_id msm8660_pinctrl_of_match[] = { { .compatible = "qcom,msm8660-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match); static struct platform_driver msm8660_pinctrl_driver = { .driver = { @@ -998,4 +999,3 @@ module_exit(msm8660_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm MSM8660 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index 709c5d1d4d0a..d115035ff96a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -960,6 +960,7 @@ static const struct of_device_id msm8916_pinctrl_of_match[] = { { .compatible = "qcom,msm8916-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match); static struct platform_driver msm8916_pinctrl_driver = { .driver = { @@ -983,4 +984,3 @@ module_exit(msm8916_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm msm8916 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c index 02ea89f5feaa..d537fdaae148 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8953.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -1807,6 +1807,7 @@ static const struct of_device_id msm8953_pinctrl_of_match[] = { { .compatible = "qcom,msm8953-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match); static struct platform_driver msm8953_pinctrl_driver = { .driver = { @@ -1830,4 +1831,3 @@ module_exit(msm8953_pinctrl_exit); MODULE_DESCRIPTION("QTI msm8953 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c index 2fb15208aba0..a373150468ca 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -1239,6 +1239,7 @@ static const struct of_device_id msm8960_pinctrl_of_match[] = { { .compatible = "qcom,msm8960-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); static struct platform_driver msm8960_pinctrl_driver = { .driver = { @@ -1263,4 +1264,3 @@ module_exit(msm8960_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index 906a90778b97..bba3c87d8144 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -1087,6 +1087,7 @@ static const struct of_device_id msm8976_pinctrl_of_match[] = { { .compatible = "qcom,msm8976-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match); static struct platform_driver msm8976_pinctrl_driver = { .driver = { @@ -1110,4 +1111,3 @@ module_exit(msm8976_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm msm8976 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c index ecbe6b91d1da..fdaa67c5869f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8994.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c @@ -1334,6 +1334,7 @@ static const struct of_device_id msm8994_pinctrl_of_match[] = { { .compatible = "qcom,msm8994-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, msm8994_pinctrl_of_match); static struct platform_driver msm8994_pinctrl_driver = { .driver = { @@ -1357,4 +1358,3 @@ module_exit(msm8994_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm MSM8994 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8994_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c index 73b07a10a957..332b18a8fa9c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8996.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -1911,6 +1911,7 @@ static const struct of_device_id msm8996_pinctrl_of_match[] = { { .compatible = "qcom,msm8996-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match); static struct platform_driver msm8996_pinctrl_driver = { .driver = { @@ -1934,4 +1935,3 @@ module_exit(msm8996_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm msm8996 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index dcf11b79e562..0552c8212b29 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8998.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -1525,6 +1525,7 @@ static const struct of_device_id msm8998_pinctrl_of_match[] = { { .compatible = "qcom,msm8998-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match); static struct platform_driver msm8998_pinctrl_driver = { .driver = { @@ -1548,4 +1549,3 @@ module_exit(msm8998_pinctrl_exit); MODULE_DESCRIPTION("QTI msm8998 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index ff432ec5815a..9422629ec6ca 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -1073,6 +1073,7 @@ static const struct of_device_id msm8x74_pinctrl_of_match[] = { { .compatible = "qcom,msm8974-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); static struct platform_driver msm8x74_pinctrl_driver = { .driver = { @@ -1097,5 +1098,4 @@ module_exit(msm8x74_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c new file mode 100644 index 000000000000..7c21306e77ff --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-nord.c @@ -0,0 +1,1770 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc nord_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); + +static const unsigned int ufs_reset_pins[] = { 181 }; + +enum nord_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_aud_intfc0_clk, + msm_mux_aud_intfc0_data, + msm_mux_aud_intfc0_ws, + msm_mux_aud_intfc10_clk, + msm_mux_aud_intfc10_data, + msm_mux_aud_intfc10_ws, + msm_mux_aud_intfc1_clk, + msm_mux_aud_intfc1_data, + msm_mux_aud_intfc1_ws, + msm_mux_aud_intfc2_clk, + msm_mux_aud_intfc2_data, + msm_mux_aud_intfc2_ws, + msm_mux_aud_intfc3_clk, + msm_mux_aud_intfc3_data, + msm_mux_aud_intfc3_ws, + msm_mux_aud_intfc4_clk, + msm_mux_aud_intfc4_data, + msm_mux_aud_intfc4_ws, + msm_mux_aud_intfc5_clk, + msm_mux_aud_intfc5_data, + msm_mux_aud_intfc5_ws, + msm_mux_aud_intfc6_clk, + msm_mux_aud_intfc6_data, + msm_mux_aud_intfc6_ws, + msm_mux_aud_intfc7_clk, + msm_mux_aud_intfc7_data, + msm_mux_aud_intfc7_ws, + msm_mux_aud_intfc8_clk, + msm_mux_aud_intfc8_data, + msm_mux_aud_intfc8_ws, + msm_mux_aud_intfc9_clk, + msm_mux_aud_intfc9_data, + msm_mux_aud_intfc9_ws, + msm_mux_aud_mclk0_mira, + msm_mux_aud_mclk0_mirb, + msm_mux_aud_mclk1_mira, + msm_mux_aud_mclk1_mirb, + msm_mux_aud_mclk2_mira, + msm_mux_aud_mclk2_mirb, + msm_mux_aud_refclk0, + msm_mux_aud_refclk1, + msm_mux_bist_done, + msm_mux_ccu_async_in, + msm_mux_ccu_i2c_scl, + msm_mux_ccu_i2c_sda, + msm_mux_ccu_timer, + msm_mux_clink_debug, + msm_mux_dbg_out, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi, + msm_mux_dp_rx0, + msm_mux_dp_rx00, + msm_mux_dp_rx01, + msm_mux_dp_rx0_mute, + msm_mux_dp_rx1, + msm_mux_dp_rx10, + msm_mux_dp_rx11, + msm_mux_dp_rx1_mute, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_hot, + msm_mux_edp1_lcd, + msm_mux_edp2_hot, + msm_mux_edp2_lcd, + msm_mux_edp3_hot, + msm_mux_edp3_lcd, + msm_mux_emac0_mcg, + msm_mux_emac0_mdc, + msm_mux_emac0_mdio, + msm_mux_emac0_ptp, + msm_mux_emac1_mcg, + msm_mux_emac1_mdc, + msm_mux_emac1_mdio, + msm_mux_emac1_ptp, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_gcc_gp4_clk, + msm_mux_gcc_gp5_clk, + msm_mux_gcc_gp6_clk, + msm_mux_gcc_gp7_clk, + msm_mux_gcc_gp8_clk, + msm_mux_jitter_bist, + msm_mux_lbist_pass, + msm_mux_mbist_pass, + msm_mux_mdp0_vsync_out, + msm_mux_mdp1_vsync_out, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie2_clk_req_n, + msm_mux_pcie3_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_pwrbrk_i_n, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qspi, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup3_se0_mira, + msm_mux_qup3_se0_mirb, + msm_mux_sailss_ospi, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_smb_alert, + msm_mux_smb_alert_n, + msm_mux_smb_clk, + msm_mux_smb_dat, + msm_mux_tb_trig_sdc4, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tsc_timer, + msm_mux_tsense_pwm, + msm_mux_usb0_hs, + msm_mux_usb0_phy_ps, + msm_mux_usb1_hs, + msm_mux_usb1_phy_ps, + msm_mux_usb2_hs, + msm_mux_usxgmii0_phy, + msm_mux_usxgmii1_phy, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", +}; + +static const char *const aoss_cti_groups[] = { + "gpio83", + "gpio84", + "gpio85", + "gpio86", +}; + +static const char *const atest_char_groups[] = { + "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", +}; + +static const char *const atest_usb20_groups[] = { + "gpio126", + "gpio128", + "gpio130", +}; + +static const char *const atest_usb21_groups[] = { + "gpio127", + "gpio129", + "gpio131", +}; + +static const char *const aud_intfc0_clk_groups[] = { + "gpio57", +}; + +static const char *const aud_intfc0_data_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", "gpio66", +}; + +static const char *const aud_intfc0_ws_groups[] = { + "gpio58", +}; + +static const char *const aud_intfc10_clk_groups[] = { + "gpio61", +}; + +static const char *const aud_intfc10_data_groups[] = { + "gpio81", "gpio82", +}; + +static const char *const aud_intfc10_ws_groups[] = { + "gpio62", +}; + +static const char *const aud_intfc1_clk_groups[] = { + "gpio67", +}; + +static const char *const aud_intfc1_data_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", +}; + +static const char *const aud_intfc1_ws_groups[] = { + "gpio68", +}; + +static const char *const aud_intfc2_clk_groups[] = { + "gpio77", +}; + +static const char *const aud_intfc2_data_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", +}; + +static const char *const aud_intfc2_ws_groups[] = { + "gpio78", +}; + +static const char *const aud_intfc3_clk_groups[] = { + "gpio83", +}; + +static const char *const aud_intfc3_data_groups[] = { + "gpio85", "gpio86", +}; + +static const char *const aud_intfc3_ws_groups[] = { + "gpio84", +}; + +static const char *const aud_intfc4_clk_groups[] = { + "gpio87", +}; + +static const char *const aud_intfc4_data_groups[] = { + "gpio89", "gpio90", +}; + +static const char *const aud_intfc4_ws_groups[] = { + "gpio88", +}; + +static const char *const aud_intfc5_clk_groups[] = { + "gpio91", +}; + +static const char *const aud_intfc5_data_groups[] = { + "gpio93", "gpio94", +}; + +static const char *const aud_intfc5_ws_groups[] = { + "gpio92", +}; + +static const char *const aud_intfc6_clk_groups[] = { + "gpio95", +}; + +static const char *const aud_intfc6_data_groups[] = { + "gpio97", "gpio98", +}; + +static const char *const aud_intfc6_ws_groups[] = { + "gpio96", +}; + +static const char *const aud_intfc7_clk_groups[] = { + "gpio63", +}; + +static const char *const aud_intfc7_data_groups[] = { + "gpio65", "gpio66", +}; + +static const char *const aud_intfc7_ws_groups[] = { + "gpio64", +}; + +static const char *const aud_intfc8_clk_groups[] = { + "gpio73", +}; + +static const char *const aud_intfc8_data_groups[] = { + "gpio75", "gpio76", +}; + +static const char *const aud_intfc8_ws_groups[] = { + "gpio74", +}; + +static const char *const aud_intfc9_clk_groups[] = { + "gpio70", +}; + +static const char *const aud_intfc9_data_groups[] = { + "gpio72", +}; + +static const char *const aud_intfc9_ws_groups[] = { + "gpio71", +}; + +static const char *const aud_mclk0_mira_groups[] = { + "gpio99", +}; + +static const char *const aud_mclk0_mirb_groups[] = { + "gpio86", +}; + +static const char *const aud_mclk1_mira_groups[] = { + "gpio100", +}; + +static const char *const aud_mclk1_mirb_groups[] = { + "gpio90", +}; + +static const char *const aud_mclk2_mira_groups[] = { + "gpio101", +}; + +static const char *const aud_mclk2_mirb_groups[] = { + "gpio94", +}; + +static const char *const aud_refclk0_groups[] = { + "gpio100", +}; + +static const char *const aud_refclk1_groups[] = { + "gpio101", +}; + +static const char *const bist_done_groups[] = { + "gpio168", +}; + +static const char *const ccu_async_in_groups[] = { + "gpio45", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", +}; + +static const char *const ccu_i2c_scl_groups[] = { + "gpio16", "gpio18", "gpio20", "gpio22", "gpio24", + "gpio114", "gpio116", "gpio126", "gpio130", "gpio132", +}; + +static const char *const ccu_i2c_sda_groups[] = { + "gpio15", "gpio17", "gpio19", "gpio21", "gpio23", + "gpio113", "gpio115", "gpio125", "gpio129", "gpio131", +}; + +static const char *const ccu_timer_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio34", "gpio143", "gpio144", + "gpio150", "gpio151", "gpio152", "gpio153", +}; + +static const char *const clink_debug_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio51", + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const dbg_out_groups[] = { + "gpio113", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio165", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio37", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio39", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio36", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio38", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio99", "gpio100", "gpio109", "gpio110", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio126", "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", + "gpio136", "gpio137", "gpio138", "gpio139", "gpio162", "gpio163", + "gpio164", "gpio165", +}; + +static const char *const dp_rx0_groups[] = { + "gpio55", "gpio83", "gpio84", "gpio85", "gpio86", + "gpio88", "gpio89", "gpio137", "gpio138", +}; + +static const char *const dp_rx00_groups[] = { + "gpio99", +}; + +static const char *const dp_rx01_groups[] = { + "gpio100", +}; + +static const char *const dp_rx0_mute_groups[] = { + "gpio35", +}; + +static const char *const dp_rx1_groups[] = { + "gpio56", "gpio92", "gpio93", "gpio95", "gpio96", + "gpio97", "gpio98", "gpio158", "gpio159", +}; + +static const char *const dp_rx10_groups[] = { + "gpio121", +}; + +static const char *const dp_rx11_groups[] = { + "gpio122", +}; + +static const char *const dp_rx1_mute_groups[] = { + "gpio36", +}; + +static const char *const edp0_hot_groups[] = { + "gpio51", +}; + +static const char *const edp0_lcd_groups[] = { + "gpio47", +}; + +static const char *const edp1_hot_groups[] = { + "gpio52", +}; + +static const char *const edp1_lcd_groups[] = { + "gpio48", +}; + +static const char *const edp2_hot_groups[] = { + "gpio53", +}; + +static const char *const edp2_lcd_groups[] = { + "gpio49", +}; + +static const char *const edp3_hot_groups[] = { + "gpio54", +}; + +static const char *const edp3_lcd_groups[] = { + "gpio50", +}; + +static const char *const emac0_mcg_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const emac0_mdc_groups[] = { + "gpio47", +}; + +static const char *const emac0_mdio_groups[] = { + "gpio48", +}; + +static const char *const emac0_ptp_groups[] = { + "gpio133", "gpio134", "gpio135", "gpio136", + "gpio139", "gpio140", "gpio141", "gpio142", +}; + +static const char *const emac1_mcg_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const emac1_mdc_groups[] = { + "gpio49", +}; + +static const char *const emac1_mdio_groups[] = { + "gpio50", +}; + +static const char *const emac1_ptp_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", + "gpio41", "gpio42", "gpio43", "gpio44", +}; + +static const char *const gcc_gp1_clk_groups[] = { + "gpio51", +}; + +static const char *const gcc_gp2_clk_groups[] = { + "gpio52", +}; + +static const char *const gcc_gp3_clk_groups[] = { + "gpio42", +}; + +static const char *const gcc_gp4_clk_groups[] = { + "gpio43", +}; + +static const char *const gcc_gp5_clk_groups[] = { + "gpio105", +}; + +static const char *const gcc_gp6_clk_groups[] = { + "gpio106", +}; + +static const char *const gcc_gp7_clk_groups[] = { + "gpio13", +}; + +static const char *const gcc_gp8_clk_groups[] = { + "gpio14", +}; + +static const char *const jitter_bist_groups[] = { + "gpio123", + "gpio138", +}; + +static const char *const lbist_pass_groups[] = { + "gpio121", +}; + +static const char *const mbist_pass_groups[] = { + "gpio122", +}; + +static const char *const mdp0_vsync_out_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116", "gpio121", "gpio122", + "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", +}; + +static const char *const mdp1_vsync_out_groups[] = { + "gpio123", "gpio124", "gpio125", "gpio126", "gpio129", "gpio130", + "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio109", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio110", +}; + +static const char *const mdp_vsync_s_groups[] = { + "gpio144", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio1", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio4", +}; + +static const char *const pcie2_clk_req_n_groups[] = { + "gpio7", +}; + +static const char *const pcie3_clk_req_n_groups[] = { + "gpio10", +}; + +static const char *const phase_flag_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", + "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio98", "gpio101", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio176", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio100", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio117", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio118", +}; + +static const char *const pwrbrk_i_n_groups[] = { + "gpio167", +}; + +static const char *const qdss_cti_groups[] = { + "gpio41", "gpio42", "gpio110", "gpio138", + "gpio142", "gpio144", "gpio162", "gpio163", +}; + +static const char *const qdss_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", + "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio108", +}; + +static const char *const qspi_groups[] = { + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", +}; + +static const char *const qup0_se0_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; + +static const char *const qup0_se1_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; + +static const char *const qup0_se2_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116", +}; + +static const char *const qup0_se3_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116", +}; + +static const char *const qup0_se4_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qup0_se5_groups[] = { + "gpio109", "gpio110", "gpio121", "gpio122", +}; + +static const char *const qup1_se0_groups[] = { + "gpio123", "gpio124", "gpio125", "gpio126", +}; + +static const char *const qup1_se1_groups[] = { + "gpio123", "gpio124", "gpio125", "gpio126", +}; + +static const char *const qup1_se2_groups[] = { + "gpio127", "gpio128", "gpio129", "gpio130", +}; + +static const char *const qup1_se3_groups[] = { + "gpio129", "gpio130", +}; + +static const char *const qup1_se4_groups[] = { + "gpio131", "gpio132", "gpio137", "gpio138", +}; + +static const char *const qup1_se5_groups[] = { + "gpio133", "gpio134", "gpio135", "gpio136", +}; + +static const char *const qup1_se6_groups[] = { + "gpio131", "gpio132", "gpio137", "gpio138", +}; + +static const char *const qup2_se0_groups[] = { + "gpio139", "gpio140", "gpio141", "gpio142", +}; + +static const char *const qup2_se1_groups[] = { + "gpio143", "gpio144", "gpio154", "gpio155", +}; + +static const char *const qup2_se2_groups[] = { + "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", +}; + +static const char *const qup2_se3_groups[] = { + "gpio150", "gpio151", "gpio152", "gpio153", +}; + +static const char *const qup2_se4_groups[] = { + "gpio143", "gpio144", "gpio150", "gpio151", + "gpio152", "gpio154", "gpio155", +}; + +static const char *const qup2_se5_groups[] = { + "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char *const qup2_se6_groups[] = { + "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char *const qup3_se0_mira_groups[] = { + "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", +}; + +static const char *const qup3_se0_mirb_groups[] = { + "gpio102", "gpio103", +}; + +static const char *const sailss_ospi_groups[] = { + "gpio164", + "gpio165", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio175", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio174", +}; + +static const char *const sdc4_data_groups[] = { + "gpio170", + "gpio171", + "gpio172", + "gpio173", +}; + +static const char *const smb_alert_groups[] = { + "gpio110", +}; + +static const char *const smb_alert_n_groups[] = { + "gpio109", +}; + +static const char *const smb_clk_groups[] = { + "gpio112", +}; + +static const char *const smb_dat_groups[] = { + "gpio111", +}; + +static const char *const tb_trig_sdc4_groups[] = { + "gpio169", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio94", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio95", +}; + +static const char *const tsc_timer_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", +}; + +static const char *const usb0_hs_groups[] = { + "gpio12", +}; + +static const char *const usb0_phy_ps_groups[] = { + "gpio164", +}; + +static const char *const usb1_hs_groups[] = { + "gpio13", +}; + +static const char *const usb1_phy_ps_groups[] = { + "gpio165", +}; + +static const char *const usb2_hs_groups[] = { + "gpio14", +}; + +static const char *const usxgmii0_phy_groups[] = { + "gpio45", +}; + +static const char *const usxgmii1_phy_groups[] = { + "gpio46", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio132", +}; + +static const char *const wcn_sw_groups[] = { + "gpio161", +}; + +static const char *const wcn_sw_ctrl_groups[] = { + "gpio160", +}; + +static const struct pinfunction nord_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(aud_intfc0_clk), + MSM_PIN_FUNCTION(aud_intfc0_data), + MSM_PIN_FUNCTION(aud_intfc0_ws), + MSM_PIN_FUNCTION(aud_intfc10_clk), + MSM_PIN_FUNCTION(aud_intfc10_data), + MSM_PIN_FUNCTION(aud_intfc10_ws), + MSM_PIN_FUNCTION(aud_intfc1_clk), + MSM_PIN_FUNCTION(aud_intfc1_data), + MSM_PIN_FUNCTION(aud_intfc1_ws), + MSM_PIN_FUNCTION(aud_intfc2_clk), + MSM_PIN_FUNCTION(aud_intfc2_data), + MSM_PIN_FUNCTION(aud_intfc2_ws), + MSM_PIN_FUNCTION(aud_intfc3_clk), + MSM_PIN_FUNCTION(aud_intfc3_data), + MSM_PIN_FUNCTION(aud_intfc3_ws), + MSM_PIN_FUNCTION(aud_intfc4_clk), + MSM_PIN_FUNCTION(aud_intfc4_data), + MSM_PIN_FUNCTION(aud_intfc4_ws), + MSM_PIN_FUNCTION(aud_intfc5_clk), + MSM_PIN_FUNCTION(aud_intfc5_data), + MSM_PIN_FUNCTION(aud_intfc5_ws), + MSM_PIN_FUNCTION(aud_intfc6_clk), + MSM_PIN_FUNCTION(aud_intfc6_data), + MSM_PIN_FUNCTION(aud_intfc6_ws), + MSM_PIN_FUNCTION(aud_intfc7_clk), + MSM_PIN_FUNCTION(aud_intfc7_data), + MSM_PIN_FUNCTION(aud_intfc7_ws), + MSM_PIN_FUNCTION(aud_intfc8_clk), + MSM_PIN_FUNCTION(aud_intfc8_data), + MSM_PIN_FUNCTION(aud_intfc8_ws), + MSM_PIN_FUNCTION(aud_intfc9_clk), + MSM_PIN_FUNCTION(aud_intfc9_data), + MSM_PIN_FUNCTION(aud_intfc9_ws), + MSM_PIN_FUNCTION(aud_mclk0_mira), + MSM_PIN_FUNCTION(aud_mclk0_mirb), + MSM_PIN_FUNCTION(aud_mclk1_mira), + MSM_PIN_FUNCTION(aud_mclk1_mirb), + MSM_PIN_FUNCTION(aud_mclk2_mira), + MSM_PIN_FUNCTION(aud_mclk2_mirb), + MSM_PIN_FUNCTION(aud_refclk0), + MSM_PIN_FUNCTION(aud_refclk1), + MSM_PIN_FUNCTION(bist_done), + MSM_PIN_FUNCTION(ccu_async_in), + MSM_PIN_FUNCTION(ccu_i2c_scl), + MSM_PIN_FUNCTION(ccu_i2c_sda), + MSM_PIN_FUNCTION(ccu_timer), + MSM_PIN_FUNCTION(clink_debug), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_rx0), + MSM_PIN_FUNCTION(dp_rx00), + MSM_PIN_FUNCTION(dp_rx01), + MSM_PIN_FUNCTION(dp_rx0_mute), + MSM_PIN_FUNCTION(dp_rx1), + MSM_PIN_FUNCTION(dp_rx10), + MSM_PIN_FUNCTION(dp_rx11), + MSM_PIN_FUNCTION(dp_rx1_mute), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_hot), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(edp2_hot), + MSM_PIN_FUNCTION(edp2_lcd), + MSM_PIN_FUNCTION(edp3_hot), + MSM_PIN_FUNCTION(edp3_lcd), + MSM_PIN_FUNCTION(emac0_mcg), + MSM_PIN_FUNCTION(emac0_mdc), + MSM_PIN_FUNCTION(emac0_mdio), + MSM_PIN_FUNCTION(emac0_ptp), + MSM_PIN_FUNCTION(emac1_mcg), + MSM_PIN_FUNCTION(emac1_mdc), + MSM_PIN_FUNCTION(emac1_mdio), + MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(gcc_gp4_clk), + MSM_PIN_FUNCTION(gcc_gp5_clk), + MSM_PIN_FUNCTION(gcc_gp6_clk), + MSM_PIN_FUNCTION(gcc_gp7_clk), + MSM_PIN_FUNCTION(gcc_gp8_clk), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lbist_pass), + MSM_PIN_FUNCTION(mbist_pass), + MSM_PIN_FUNCTION(mdp0_vsync_out), + MSM_PIN_FUNCTION(mdp1_vsync_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(pcie3_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(pwrbrk_i_n), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup3_se0_mira), + MSM_PIN_FUNCTION(qup3_se0_mirb), + MSM_PIN_FUNCTION(sailss_ospi), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(smb_alert), + MSM_PIN_FUNCTION(smb_alert_n), + MSM_PIN_FUNCTION(smb_clk), + MSM_PIN_FUNCTION(smb_dat), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tsc_timer), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(usb1_hs), + MSM_PIN_FUNCTION(usb1_phy_ps), + MSM_PIN_FUNCTION(usb2_hs), + MSM_PIN_FUNCTION(usxgmii0_phy), + MSM_PIN_FUNCTION(usxgmii1_phy), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup nord_groups[] = { + [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, _, _, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, _, _, _, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, pcie2_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, _, _, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, _, _, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, pcie3_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, _, _, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, usb0_hs, clink_debug, _, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, usb1_hs, clink_debug, gcc_gp7_clk, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, usb2_hs, clink_debug, gcc_gp8_clk, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, ccu_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, ccu_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, dp_rx0_mute, _, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, dp_rx1_mute, ddr_bist_start, _, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, emac1_ptp, ddr_bist_complete, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, emac1_ptp, ddr_bist_stop, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, emac1_ptp, ddr_bist_fail, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, emac1_ptp, _, _, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, emac1_ptp, qdss_cti, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, emac1_ptp, qdss_cti, gcc_gp3_clk, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, emac1_ptp, gcc_gp4_clk, tsense_pwm, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, emac1_ptp, tsense_pwm, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, usxgmii0_phy, ccu_async_in, tsense_pwm, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, usxgmii1_phy, tsense_pwm, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, emac0_mdc, edp0_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, emac0_mdio, edp1_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, emac1_mdc, edp2_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, emac1_mdio, edp3_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, edp0_hot, clink_debug, gcc_gp1_clk, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, edp1_hot, clink_debug, gcc_gp2_clk, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, edp2_hot, clink_debug, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, edp3_hot, clink_debug, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, dp_rx0, clink_debug, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, dp_rx1, _, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, aud_intfc0_clk, _, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, aud_intfc0_ws, _, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, aud_intfc0_data, _, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, aud_intfc0_data, _, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, aud_intfc0_data, aud_intfc10_clk, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, aud_intfc0_data, aud_intfc10_ws, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, aud_intfc0_data, aud_intfc7_clk, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, aud_intfc0_data, aud_intfc7_ws, _, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, aud_intfc1_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [68] = PINGROUP(68, aud_intfc1_ws, phase_flag, _, qdss, _, _, _, _, _, _, _), + [69] = PINGROUP(69, aud_intfc1_data, phase_flag, _, qdss, _, _, _, _, _, _, _), + [70] = PINGROUP(70, aud_intfc1_data, aud_intfc9_clk, phase_flag, + _, qdss, _, _, _, _, _, _), + [71] = PINGROUP(71, aud_intfc1_data, aud_intfc9_ws, phase_flag, + _, qdss, _, _, _, _, _, _), + [72] = PINGROUP(72, aud_intfc1_data, aud_intfc9_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [73] = PINGROUP(73, aud_intfc1_data, aud_intfc8_clk, phase_flag, + _, qdss, _, _, _, _, _, _), + [74] = PINGROUP(74, aud_intfc1_data, aud_intfc8_ws, phase_flag, + _, qdss, _, _, _, _, _, _), + [75] = PINGROUP(75, aud_intfc1_data, aud_intfc8_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [76] = PINGROUP(76, aud_intfc1_data, aud_intfc8_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [77] = PINGROUP(77, aud_intfc2_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [78] = PINGROUP(78, aud_intfc2_ws, phase_flag, _, qdss, _, _, _, _, _, _, _), + [79] = PINGROUP(79, aud_intfc2_data, phase_flag, _, qdss, _, _, _, _, _, _, _), + [80] = PINGROUP(80, aud_intfc2_data, phase_flag, _, _, qdss, _, _, _, _, _, _), + [81] = PINGROUP(81, aud_intfc2_data, aud_intfc10_data, phase_flag, + _, _, qdss, _, _, _, _, _), + [82] = PINGROUP(82, aud_intfc2_data, aud_intfc10_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [83] = PINGROUP(83, aud_intfc3_clk, dp_rx0, aoss_cti, phase_flag, _, qdss, + _, _, _, _, _), + [84] = PINGROUP(84, aud_intfc3_ws, dp_rx0, aoss_cti, phase_flag, _, qdss, + _, _, _, _, _), + [85] = PINGROUP(85, aud_intfc3_data, dp_rx0, aoss_cti, phase_flag, + _, qdss, _, _, _, _, _), + [86] = PINGROUP(86, aud_intfc3_data, aud_mclk0_mirb, dp_rx0, aoss_cti, phase_flag, + _, qdss, _, _, _, _), + [87] = PINGROUP(87, aud_intfc4_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [88] = PINGROUP(88, aud_intfc4_ws, dp_rx0, phase_flag, _, qdss, _, _, _, _, _, _), + [89] = PINGROUP(89, aud_intfc4_data, dp_rx0, phase_flag, _, qdss, + _, _, _, _, _, _), + [90] = PINGROUP(90, aud_intfc4_data, aud_mclk1_mirb, phase_flag, + _, qdss, _, _, _, _, _, _), + [91] = PINGROUP(91, aud_intfc5_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [92] = PINGROUP(92, aud_intfc5_ws, dp_rx1, phase_flag, _, qdss, _, _, _, _, _, _), + [93] = PINGROUP(93, aud_intfc5_data, dp_rx1, phase_flag, _, qdss, + _, _, _, _, _, _), + [94] = PINGROUP(94, aud_intfc5_data, aud_mclk2_mirb, phase_flag, tmess_prng0, + _, qdss, _, _, _, _, _), + [95] = PINGROUP(95, aud_intfc6_clk, dp_rx1, phase_flag, tmess_prng1, + _, qdss, _, _, _, _, _), + [96] = PINGROUP(96, aud_intfc6_ws, dp_rx1, phase_flag, _, qdss, + _, _, _, _, _, _), + [97] = PINGROUP(97, aud_intfc6_data, dp_rx1, qdss, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, aud_intfc6_data, dp_rx1, phase_flag, _, qdss, + _, _, _, _, _, _), + [99] = PINGROUP(99, aud_mclk0_mira, qdss, dp_rx00, ddr_pxi, _, _, _, _, _, _, _), + [100] = PINGROUP(100, aud_mclk1_mira, aud_refclk0, pll_clk_aux, + qdss, dp_rx01, ddr_pxi, _, _, _, _, _), + [101] = PINGROUP(101, aud_mclk2_mira, aud_refclk1, phase_flag, _, qdss, + _, _, _, _, _, _), + [102] = PINGROUP(102, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, qspi, qup3_se0_mira, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, qspi, qup3_se0_mira, gcc_gp5_clk, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, qspi, qup3_se0_mira, gcc_gp6_clk, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, qspi, qup3_se0_mira, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, qspi, qup3_se0_mira, qdss, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, qup0_se0, qup0_se1, qup0_se5, mdp_vsync_e, + smb_alert_n, _, ddr_pxi, _, _, _, _), + [110] = PINGROUP(110, qup0_se0, qup0_se1, qup0_se5, qdss_cti, + mdp_vsync_p, smb_alert, _, ddr_pxi, _, _, _), + [111] = PINGROUP(111, qup0_se1, qup0_se0, smb_dat, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, qup0_se1, qup0_se0, smb_clk, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, qup0_se2, qup0_se3, ccu_i2c_sda, mdp0_vsync_out, + dbg_out, ddr_pxi, _, _, _, _, _), + [114] = PINGROUP(114, qup0_se2, qup0_se3, ccu_i2c_scl, mdp0_vsync_out, + _, ddr_pxi, _, _, _, _, _), + [115] = PINGROUP(115, qup0_se3, qup0_se2, ccu_i2c_sda, mdp0_vsync_out, + _, ddr_pxi, _, _, _, _, _), + [116] = PINGROUP(116, qup0_se3, qup0_se2, ccu_i2c_scl, mdp0_vsync_out, + _, ddr_pxi, _, _, _, _, _), + [117] = PINGROUP(117, qup0_se4, prng_rosc0, _, ddr_pxi, _, _, _, _, _, _, _), + [118] = PINGROUP(118, qup0_se4, prng_rosc1, _, ddr_pxi, _, _, _, _, _, _, _), + [119] = PINGROUP(119, qup0_se4, _, ddr_pxi, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, qup0_se4, _, ddr_pxi, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, qup0_se5, lbist_pass, mdp0_vsync_out, _, dp_rx10, ddr_pxi, + _, _, _, _, _), + [122] = PINGROUP(122, qup0_se5, mbist_pass, mdp0_vsync_out, _, dp_rx11, ddr_pxi, + _, _, _, _, _), + [123] = PINGROUP(123, qup1_se0, qup1_se1, mdp1_vsync_out, jitter_bist, + _, _, _, _, _, _, _), + [124] = PINGROUP(124, qup1_se0, qup1_se1, mdp1_vsync_out, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, qup1_se1, qup1_se0, ccu_i2c_sda, mdp1_vsync_out, + _, _, _, _, _, _, _), + [126] = PINGROUP(126, qup1_se1, qup1_se0, ccu_i2c_scl, mdp1_vsync_out, + _, atest_usb20, ddr_pxi, _, _, _, _), + [127] = PINGROUP(127, qup1_se2, qup1_se2, _, atest_usb21, ddr_pxi, + _, _, _, _, _, _), + [128] = PINGROUP(128, qup1_se2, qup1_se2, _, atest_usb20, ddr_pxi, + _, _, _, _, _, _), + [129] = PINGROUP(129, qup1_se3, qup1_se3, ccu_i2c_sda, mdp1_vsync_out, + _, atest_usb21, ddr_pxi, _, _, _, _), + [130] = PINGROUP(130, qup1_se3, qup1_se3, ccu_i2c_scl, mdp1_vsync_out, + _, atest_usb20, ddr_pxi, _, _, _, _), + [131] = PINGROUP(131, qup1_se4, qup1_se6, ccu_i2c_sda, mdp1_vsync_out, + _, atest_usb21, ddr_pxi, _, _, _, _), + [132] = PINGROUP(132, qup1_se4, qup1_se6, ccu_i2c_scl, mdp1_vsync_out, + _, vsense_trigger_mirnat, ddr_pxi, _, _, _, _), + [133] = PINGROUP(133, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, + _, _, _, _, _, _), + [134] = PINGROUP(134, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, + _, _, _, _, _, _), + [135] = PINGROUP(135, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, + _, _, _, _, _, _), + [136] = PINGROUP(136, qup1_se5, emac0_ptp, _, ddr_pxi, _, _, _, _, _, _, _), + [137] = PINGROUP(137, qup1_se6, qup1_se4, dp_rx0, _, ddr_pxi, _, _, _, _, _, _), + [138] = PINGROUP(138, qup1_se6, qup1_se4, dp_rx0, qdss_cti, jitter_bist, ddr_pxi, + _, _, _, _, _), + [139] = PINGROUP(139, qup2_se0, emac0_ptp, mdp0_vsync_out, ddr_pxi, + _, _, _, _, _, _, _), + [140] = PINGROUP(140, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, qup2_se0, emac0_ptp, qdss_cti, mdp0_vsync_out, _, _, _, _, _, _, _), + [143] = PINGROUP(143, qup2_se1, qup2_se4, ccu_timer, mdp0_vsync_out, + _, _, _, _, _, _, _), + [144] = PINGROUP(144, qup2_se1, qup2_se4, ccu_timer, qdss_cti, mdp_vsync_s, + _, _, _, _, _, _), + [145] = PINGROUP(145, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qup2_se3, ccu_timer, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qup2_se4, qup2_se1, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, qup2_se4, qup2_se1, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qup2_se5, qup2_se6, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qup2_se5, qup2_se6, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, wcn_sw, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qdss_cti, _, ddr_pxi, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, qdss_cti, _, ddr_pxi, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, usb0_phy_ps, _, sailss_ospi, ddr_pxi, _, _, _, _, _, _, _), + [165] = PINGROUP(165, usb1_phy_ps, dbg_out_clk, sailss_ospi, ddr_pxi, + _, _, _, _, _, _, _), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, pwrbrk_i_n, _, _, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, bist_done, _, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, tb_trig_sdc4, _, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, sdc4_cmd, _, _, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, sdc4_clk, _, _, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, ccu_async_in, pll_bist_sync, atest_char, + _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [181] = UFS_RESET(ufs_reset, 0xbd004, 0xbe000), +}; + +static const struct msm_gpio_wakeirq_map nord_pdc_map[] = { + { 0, 67 }, { 1, 68 }, { 2, 82 }, { 3, 69 }, { 4, 70 }, + { 5, 83 }, { 6, 71 }, { 7, 72 }, { 8, 84 }, { 9, 73 }, + { 10, 119 }, { 11, 85 }, { 45, 107 }, { 46, 98 }, { 102, 77 }, + { 108, 78 }, { 110, 120 }, { 114, 80 }, { 116, 81 }, { 120, 117 }, + { 124, 108 }, { 126, 99 }, { 128, 100 }, { 132, 101 }, { 138, 87 }, + { 142, 88 }, { 144, 89 }, { 153, 90 }, { 157, 91 }, { 159, 118 }, + { 160, 110 }, { 161, 79 }, { 166, 109 }, { 168, 111 }, +}; + +static const struct msm_pinctrl_soc_data nord_tlmm = { + .pins = nord_pins, + .npins = ARRAY_SIZE(nord_pins), + .functions = nord_functions, + .nfunctions = ARRAY_SIZE(nord_functions), + .groups = nord_groups, + .ngroups = ARRAY_SIZE(nord_groups), + .ngpios = 182, + .wakeirq_map = nord_pdc_map, + .nwakeirq_map = ARRAY_SIZE(nord_pdc_map), + .egpio_func = 11, +}; + +static const struct of_device_id nord_tlmm_of_match[] = { + { .compatible = "qcom,nord-tlmm", .data = &nord_tlmm }, + {}, +}; + +static int nord_tlmm_probe(struct platform_device *pdev) +{ + const struct msm_pinctrl_soc_data *pinctrl_data; + struct device *dev = &pdev->dev; + + pinctrl_data = device_get_match_data(dev); + if (!pinctrl_data) + return -EINVAL; + + return msm_pinctrl_probe(pdev, &nord_tlmm); +} + +static struct platform_driver nord_tlmm_driver = { + .driver = { + .name = "nord-tlmm", + .of_match_table = nord_tlmm_of_match, + }, + .probe = nord_tlmm_probe, +}; + +static int __init nord_tlmm_init(void) +{ + return platform_driver_register(&nord_tlmm_driver); +} +arch_initcall(nord_tlmm_init); + +static void __exit nord_tlmm_exit(void) +{ + platform_driver_unregister(&nord_tlmm_driver); +} +module_exit(nord_tlmm_exit); + +MODULE_DESCRIPTION("QTI Nord TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, nord_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index 3b28ac498885..ffec2fd6412c 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -75,29 +75,6 @@ .intr_detection_width = -1, \ } -#define UFS_RESET(pg_name, offset) \ - { \ - .grp = PINCTRL_PINGROUP(#pg_name, \ - pg_name##_pins, \ - ARRAY_SIZE(pg_name##_pins)), \ - .ctl_reg = offset, \ - .io_reg = offset + 0x4, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = 3, \ - .drv_bit = 0, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = 0, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } static const struct pinctrl_pin_desc qcm2290_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), @@ -1124,6 +1101,7 @@ static const struct of_device_id qcm2290_pinctrl_of_match[] = { { .compatible = "qcom,qcm2290-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match); static struct platform_driver qcm2290_pinctrl_driver = { .driver = { @@ -1147,4 +1125,3 @@ module_exit(qcm2290_pinctrl_exit); MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 1048a7093b2e..01c0f0b2839a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -1635,6 +1635,7 @@ static const struct of_device_id qcs404_pinctrl_of_match[] = { { .compatible = "qcom,qcs404-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, qcs404_pinctrl_of_match); static struct platform_driver qcs404_pinctrl_driver = { .driver = { @@ -1658,4 +1659,3 @@ module_exit(qcs404_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm QCS404 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, qcs404_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c index f066b3a576f7..0e7df184122b 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs615.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c @@ -1073,6 +1073,7 @@ static const struct of_device_id qcs615_tlmm_of_match[] = { }, {}, }; +MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match); static int qcs615_tlmm_probe(struct platform_device *pdev) { @@ -1101,4 +1102,3 @@ module_exit(qcs615_tlmm_exit); MODULE_DESCRIPTION("QTI QCS615 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c index 852cd36df6d5..9a904d809e11 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -100,12 +100,6 @@ .intr_detection_width = -1, \ } -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - #define QUP_I3C_6_MODE_OFFSET 0xaf000 #define QUP_I3C_7_MODE_OFFSET 0xb0000 #define QUP_I3C_13_MODE_OFFSET 0xb1000 diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c index 5125df7eb127..1ef77f82820c 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdu1000.c +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -75,36 +75,6 @@ .intr_detection_width = -1, \ } -#define UFS_RESET(pg_name, offset) \ - { \ - .grp = PINCTRL_PINGROUP(#pg_name, \ - pg_name##_pins, \ - ARRAY_SIZE(pg_name##_pins)), \ - .ctl_reg = offset, \ - .io_reg = offset + 0x4, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = 3, \ - .drv_bit = 0, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = 0, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - static const struct pinctrl_pin_desc qdu1000_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index e9a510d3583f..5dbaa50cbff0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -101,12 +101,6 @@ .intr_detection_width = -1, \ } -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - #define QUP_I3C_6_MODE_OFFSET 0xAF000 #define QUP_I3C_7_MODE_OFFSET 0xB0000 #define QUP_I3C_13_MODE_OFFSET 0xB1000 diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index 01cfcb416f33..a02a9a78a557 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -1148,6 +1148,7 @@ static const struct of_device_id sc7180_pinctrl_of_match[] = { { .compatible = "qcom,sc7180-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match); static struct platform_driver sc7180_pinctrl_driver = { .driver = { @@ -1172,4 +1173,3 @@ module_exit(sc7180_pinctrl_exit); MODULE_DESCRIPTION("QTI sc7180 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8..a61df10d46cb 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -129,20 +131,25 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sc7280-lpass-lpi-pinctrl", - .data = &sc7280_lpi_data, + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, }, { - .compatible = "qcom,sm8350-lpass-lpi-pinctrl", - .data = &sc7280_lpi_data, + .compatible = "qcom,sm8350-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sc7280-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sc7280-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index f22fd56efd89..bb32a56649df 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -1494,6 +1494,7 @@ static const struct of_device_id sc7280_pinctrl_of_match[] = { { .compatible = "qcom,sc7280-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match); static struct platform_driver sc7280_pinctrl_driver = { .driver = { @@ -1518,4 +1519,3 @@ module_exit(sc7280_pinctrl_exit); MODULE_DESCRIPTION("QTI sc7280 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4..27c47710365e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -166,17 +168,22 @@ static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl", - .data = &sc8280xp_lpi_data, + .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl", + .data = &sc8280xp_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sc8280xp-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c index 65411abfbfac..7b5aacaae7d7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -10,6 +10,8 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-lpass-lpi.h" @@ -145,10 +147,15 @@ static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm660_lpi_pinctrl_driver = { .driver = { .name = "qcom-sdm660-lpass-lpi-pinctrl", .of_match_table = sdm660_lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index ab0368653d30..c4a1ec90a341 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -1433,6 +1433,7 @@ static const struct of_device_id sdm660_pinctrl_of_match[] = { { .compatible = "qcom,sdm630-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); static struct platform_driver sdm660_pinctrl_driver = { .driver = { @@ -1456,4 +1457,3 @@ module_exit(sdm660_pinctrl_exit); MODULE_DESCRIPTION("QTI sdm660 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c index 858146c408d0..0a31f7ad2e0d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-lpass-lpi.h" @@ -151,10 +153,15 @@ static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm670_lpi_pinctrl_driver = { .driver = { .name = "qcom-sdm670-lpass-lpi-pinctrl", .of_match_table = sdm670_lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index b5ed2311b70e..48fbe3623e17 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1339,6 +1339,7 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = { { .compatible = "qcom,sdm845-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match); static struct platform_driver sdm845_pinctrl_driver = { .driver = { @@ -1364,4 +1365,3 @@ module_exit(sdm845_pinctrl_exit); MODULE_DESCRIPTION("QTI sdm845 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c index 3e87f5927924..656a0726db92 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx55.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -981,6 +981,7 @@ static const struct of_device_id sdx55_pinctrl_of_match[] = { { .compatible = "qcom,sdx55-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); static struct platform_driver sdx55_pinctrl_driver = { .driver = { @@ -1004,4 +1005,3 @@ module_exit(sdx55_pinctrl_exit); MODULE_DESCRIPTION("QTI sdx55 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c index 4e787341b2a2..dde8993ca9b1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx65.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -929,6 +929,7 @@ static const struct of_device_id sdx65_pinctrl_of_match[] = { { .compatible = "qcom,sdx65-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); static struct platform_driver sdx65_pinctrl_driver = { .driver = { @@ -952,4 +953,3 @@ module_exit(sdx65_pinctrl_exit); MODULE_DESCRIPTION("QTI sdx65 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c new file mode 100644 index 000000000000..0fc98369948c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c @@ -0,0 +1,1253 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_enable_bit = 7, \ + .intr_wakeup_present_bit = 6, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc shikra_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "SDC1_RCLK"), + PINCTRL_PIN(167, "SDC1_CLK"), + PINCTRL_PIN(168, "SDC1_CMD"), + PINCTRL_PIN(169, "SDC1_DATA"), + PINCTRL_PIN(170, "SDC2_CLK"), + PINCTRL_PIN(171, "SDC2_CMD"), + PINCTRL_PIN(172, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); + +static const unsigned int sdc1_rclk_pins[] = { 166 }; +static const unsigned int sdc1_clk_pins[] = { 167 }; +static const unsigned int sdc1_cmd_pins[] = { 168 }; +static const unsigned int sdc1_data_pins[] = { 169 }; +static const unsigned int sdc2_clk_pins[] = { 170 }; +static const unsigned int sdc2_cmd_pins[] = { 171 }; +static const unsigned int sdc2_data_pins[] = { 172 }; + +enum shikra_functions { + msm_mux_gpio, + msm_mux_agera_pll, + msm_mux_atest_bbrx, + msm_mux_atest_char, + msm_mux_atest_gpsadc, + msm_mux_atest_tsens, + msm_mux_atest_usb, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_cci_timer, + msm_mux_char_exec, + msm_mux_cri_trng, + msm_mux_dac_calib, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dmic, + msm_mux_emac_dll, + msm_mux_emac_mcg, + msm_mux_emac_phy, + msm_mux_emac0_ptp_aux, + msm_mux_emac0_ptp_pps, + msm_mux_emac1_ptp_aux, + msm_mux_emac1_ptp_pps, + msm_mux_ext_mclk, + msm_mux_gcc_gp, + msm_mux_gsm0_tx, + msm_mux_i2s0, + msm_mux_i2s1, + msm_mux_i2s2, + msm_mux_i2s3, + msm_mux_jitter_bist, + msm_mux_m_voc, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_out0, + msm_mux_mdp_vsync_out1, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_mpm_pwr, + msm_mux_mss_lte, + msm_mux_nav_gpio, + msm_mux_pa_indicator_or, + msm_mux_pbs_in, + msm_mux_pbs_out, + msm_mux_pcie0_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll, + msm_mux_prng_rosc, + msm_mux_pwm, + msm_mux_qdss_cti, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se1_01, + msm_mux_qup0_se1_23, + msm_mux_qup0_se2, + msm_mux_qup0_se3_01, + msm_mux_qup0_se3_23, + msm_mux_qup0_se4_01, + msm_mux_qup0_se4_23, + msm_mux_qup0_se5, + msm_mux_qup0_se6, + msm_mux_qup0_se7_01, + msm_mux_qup0_se7_23, + msm_mux_qup0_se8, + msm_mux_qup0_se9, + msm_mux_qup0_se9_01, + msm_mux_qup0_se9_23, + msm_mux_rgmii, + msm_mux_sd_write_protect, + msm_mux_sdc_cdc, + msm_mux_sdc_tb_trig, + msm_mux_ssbi_wtr, + msm_mux_swr0_rx, + msm_mux_swr0_tx, + msm_mux_tgu_ch_trigout, + msm_mux_tsc_async, + msm_mux_tsense_pwm, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_unused_adsp, + msm_mux_unused_gsm1, + msm_mux_usb0_phy_ps, + msm_mux_vfr, + msm_mux_vsense_trigger_mirnat, + msm_mux_wlan, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", +}; + +static const char *const agera_pll_groups[] = { + "gpio22", "gpio23", +}; + +static const char *const atest_bbrx_groups[] = { + "gpio58", "gpio59", +}; + +static const char *const atest_char_groups[] = { + "gpio56", "gpio57", "gpio54", "gpio55", "gpio62", +}; + +static const char *const atest_gpsadc_groups[] = { + "gpio60", "gpio96", +}; + +static const char *const atest_tsens_groups[] = { + "gpio1", "gpio2", +}; + +static const char *const atest_usb_groups[] = { + "gpio53", "gpio58", "gpio59", "gpio60", "gpio61", "gpio96", + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char *const cam_mclk_groups[] = { + "gpio34", "gpio35", "gpio96", "gpio98", +}; + +static const char *const cci_async_groups[] = { + "gpio39", +}; + +static const char *const cci_i2c0_groups[] = { + "gpio36", "gpio37", +}; + +static const char *const cci_i2c1_groups[] = { + "gpio41", "gpio42", +}; + +static const char *const cci_timer_groups[] = { + "gpio38", "gpio40", "gpio43", "gpio47", +}; + +static const char *const char_exec_groups[] = { + "gpio12", "gpio13", +}; + +static const char *const cri_trng_groups[] = { + "gpio6", "gpio7", "gpio20", +}; + +static const char *const dac_calib_groups[] = { + "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio63", "gpio64", "gpio66", "gpio68", "gpio69", + "gpio70", "gpio88", "gpio89", "gpio90", "gpio97", "gpio116", + "gpio117", "gpio118", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio61", +}; + +static const char *const ddr_bist_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char *const dmic_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char *const emac_dll_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; + +static const char *const emac_mcg_groups[] = { + "gpio28", "gpio29", "gpio40", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", +}; + +static const char *const emac_phy_groups[] = { + "gpio120", "gpio136", +}; + +static const char *const emac0_ptp_aux_groups[] = { + "gpio60", "gpio63", "gpio69", "gpio85", +}; + +static const char *const emac0_ptp_pps_groups[] = { + "gpio60", "gpio63", "gpio69", "gpio85", +}; + +static const char *const emac1_ptp_aux_groups[] = { + "gpio31", "gpio33", "gpio60", "gpio68", +}; + +static const char *const emac1_ptp_pps_groups[] = { + "gpio31", "gpio33", "gpio60", "gpio68", +}; + +static const char *const ext_mclk_groups[] = { + "gpio103", "gpio104", "gpio110", "gpio114", +}; + +static const char *const gcc_gp_groups[] = { + "gpio45", "gpio53", "gpio61", "gpio88", "gpio89", "gpio110", +}; + +static const char *const gsm0_tx_groups[] = { + "gpio75", +}; + +static const char *const i2s0_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", +}; + +static const char *const i2s1_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char *const i2s2_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", +}; + +static const char *const i2s3_groups[] = { + "gpio111", "gpio112", "gpio113", "gpio114", +}; + +static const char *const jitter_bist_groups[] = { + "gpio96", "gpio99", +}; + +static const char *const m_voc_groups[] = { + "gpio0", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio94", +}; + +static const char *const mdp_vsync_out0_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_out1_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_s_groups[] = { + "gpio95", +}; + +static const char *const mpm_pwr_groups[] = { + "gpio1", +}; + +static const char *const mss_lte_groups[] = { + "gpio115", "gpio116", +}; + +static const char *const nav_gpio_groups[] = { + "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92", + "gpio95", "gpio100", "gpio101", "gpio104", +}; + +static const char *const pa_indicator_or_groups[] = { + "gpio61", +}; + +static const char *const pbs_in_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", "gpio53", "gpio54", + "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", + "gpio61", "gpio62", "gpio63", "gpio74", +}; + +static const char *const pbs_out_groups[] = { + "gpio22", "gpio23", "gpio24", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio117", +}; + +static const char *const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio11", "gpio16", + "gpio17", "gpio28", "gpio29", "gpio30", "gpio31", "gpio48", + "gpio49", "gpio50", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio62", "gpio63", "gpio64", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio74", "gpio102", +}; + +static const char *const pll_groups[] = { + "gpio14", "gpio22", "gpio43", "gpio44", "gpio74", "gpio76", +}; + +static const char *const prng_rosc_groups[] = { + "gpio27", "gpio28", +}; + +static const char *const pwm_groups[] = { + "gpio32", "gpio40", "gpio45", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio61", "gpio62", "gpio68", + "gpio77", "gpio79", "gpio80", "gpio87", "gpio102" +}; + +static const char *const qdss_cti_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95", +}; + +static const char *const qup0_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup0_se1_groups[] = { + "gpio28", "gpio29", +}; + +static const char *const qup0_se1_01_groups[] = { + "gpio4", "gpio5", +}; + +static const char *const qup0_se1_23_groups[] = { + "gpio4", "gpio5", +}; + +static const char *const qup0_se2_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31", +}; + +static const char *const qup0_se3_01_groups[] = { + "gpio10", "gpio11", +}; + +static const char *const qup0_se3_23_groups[] = { + "gpio10", "gpio11", +}; + +static const char *const qup0_se4_01_groups[] = { + "gpio12", "gpio13", +}; + +static const char *const qup0_se4_23_groups[] = { + "gpio12", "gpio13", +}; + +static const char *const qup0_se5_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char *const qup0_se6_groups[] = { + "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup0_se7_01_groups[] = { + "gpio20", "gpio21", +}; + +static const char *const qup0_se7_23_groups[] = { + "gpio20", "gpio21", +}; + +static const char *const qup0_se8_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char *const qup0_se9_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup0_se9_01_groups[] = { + "gpio26", "gpio27", +}; + +static const char *const qup0_se9_23_groups[] = { + "gpio26", "gpio27", +}; + +static const char *const rgmii_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio134", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio109", +}; + +static const char *const sdc_cdc_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char *const sdc_tb_trig_groups[] = { + "gpio32", "gpio33", +}; + +static const char *const ssbi_wtr_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char *const swr0_rx_groups[] = { + "gpio107", "gpio108", "gpio109", +}; + +static const char *const swr0_tx_groups[] = { + "gpio105", "gpio106", +}; + +static const char *const tgu_ch_trigout_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char *const tsc_async_groups[] = { + "gpio45", "gpio46", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio21", +}; + +static const char *const uim1_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; + +static const char *const uim2_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", +}; + +static const char *const unused_adsp_groups[] = { + "gpio35", +}; + +static const char *const unused_gsm1_groups[] = { + "gpio64", +}; + +static const char *const usb0_phy_ps_groups[] = { + "gpio90", +}; + +static const char *const vfr_groups[] = { + "gpio59", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio58", +}; + +static const char *const wlan_groups[] = { + "gpio14", "gpio15", +}; + +static const struct pinfunction shikra_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_bbrx), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_gpsadc), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(char_exec), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dac_calib), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dmic), + MSM_PIN_FUNCTION(emac_dll), + MSM_PIN_FUNCTION(emac_mcg), + MSM_PIN_FUNCTION(emac_phy), + MSM_PIN_FUNCTION(emac0_ptp_aux), + MSM_PIN_FUNCTION(emac0_ptp_pps), + MSM_PIN_FUNCTION(emac1_ptp_aux), + MSM_PIN_FUNCTION(emac1_ptp_pps), + MSM_PIN_FUNCTION(ext_mclk), + MSM_PIN_FUNCTION(gcc_gp), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(i2s0), + MSM_PIN_FUNCTION(i2s1), + MSM_PIN_FUNCTION(i2s2), + MSM_PIN_FUNCTION(i2s3), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_out0), + MSM_PIN_FUNCTION(mdp_vsync_out1), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(mpm_pwr), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator_or), + MSM_PIN_FUNCTION(pbs_in), + MSM_PIN_FUNCTION(pbs_out), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwm), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se1_01), + MSM_PIN_FUNCTION(qup0_se1_23), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3_01), + MSM_PIN_FUNCTION(qup0_se3_23), + MSM_PIN_FUNCTION(qup0_se4_01), + MSM_PIN_FUNCTION(qup0_se4_23), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup0_se6), + MSM_PIN_FUNCTION(qup0_se7_01), + MSM_PIN_FUNCTION(qup0_se7_23), + MSM_PIN_FUNCTION(qup0_se8), + MSM_PIN_FUNCTION(qup0_se9), + MSM_PIN_FUNCTION(qup0_se9_01), + MSM_PIN_FUNCTION(qup0_se9_23), + MSM_PIN_FUNCTION(rgmii), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc_cdc), + MSM_PIN_FUNCTION(sdc_tb_trig), + MSM_PIN_FUNCTION(ssbi_wtr), + MSM_PIN_FUNCTION(swr0_rx), + MSM_PIN_FUNCTION(swr0_tx), + MSM_PIN_FUNCTION(tgu_ch_trigout), + MSM_PIN_FUNCTION(tsc_async), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(unused_adsp), + MSM_PIN_FUNCTION(unused_gsm1), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(vfr), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wlan), +}; + +static const struct msm_pingroup shikra_groups[] = { + [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _), + [2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _), + [4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _, + _, _), + [5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _), + [6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), + [7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), + [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _), + [15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _), + [16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), + [17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), + [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti, + _, _, _, _), + [29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _), + [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _), + [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag, + qdss_cti, _, _, _, _), + [32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _), + [46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _), + [54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb, + vsense_trigger_mirnat, emac_dll, _, _), + [59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _), + [60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _, + pbs_in, atest_gpsadc, atest_usb, emac_dll, _), + [61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb, + emac_dll, _, _, _), + [62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag, + dac_calib, _, _, _), + [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _, + _, _), + [69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib, + _, _, _, _), + [70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _), + [71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _), + [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _), + [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _, + _, _), + [97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _), + [99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _), + [103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _), + [111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _), + [166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0), + [167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6), + [168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3), + [169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0), + [170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6), + [171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3), + [172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = { + {1, 9 }, {2, 31 }, {5, 49 }, {6, 53 }, {9, 72 }, {10, 10 }, + {12, 22 }, {14, 26 }, {17, 29 }, {18, 24 }, {20, 32 }, {22, 33 }, + {25, 34 }, {27, 35 }, {28, 36 }, {29, 37 }, {30, 38 }, {31, 39 }, + {32, 40 }, {33, 41 }, {38, 42 }, {40, 43 }, {43, 44 }, {44, 45 }, + {45, 46 }, {46, 47 }, {47, 48 }, {48, 60 }, {50, 50 }, {51, 51 }, + {52, 61 }, {53, 62 }, {57, 52 }, {58, 63 }, {60, 54 }, {63, 64 }, + {73, 55 }, {74, 56 }, {75, 57 }, {77, 3 }, {80, 4 }, {84, 5 }, + {85, 67 }, {86, 69 }, {88, 70 }, {89, 71 }, {90, 73 }, {91, 74 }, + {92, 75 }, {93, 76 }, {94, 77 }, {95, 78 }, {97, 79 }, {99, 80 }, + {100, 11 }, {101, 13 }, {102, 14 }, {103, 15 }, {106, 16 }, {108, 17 }, + {112, 18 }, {116, 19 }, {117, 20 }, {119, 21 }, {120, 23 }, {136, 25 }, + {159, 27 }, {161, 28 }, +}; + +static const struct msm_pinctrl_soc_data shikra_tlmm = { + .pins = shikra_pins, + .npins = ARRAY_SIZE(shikra_pins), + .functions = shikra_functions, + .nfunctions = ARRAY_SIZE(shikra_functions), + .groups = shikra_groups, + .ngroups = ARRAY_SIZE(shikra_groups), + .ngpios = 166, + .wakeirq_map = shikra_mpm_map, + .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map), +}; + +static int shikra_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &shikra_tlmm); +} + +static const struct of_device_id shikra_tlmm_of_match[] = { + { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm }, + {}, +}; +MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match); + +static struct platform_driver shikra_tlmm_driver = { + .driver = { + .name = "shikra-tlmm", + .of_match_table = shikra_tlmm_of_match, + }, + .probe = shikra_tlmm_probe, +}; + +static int __init shikra_tlmm_init(void) +{ + return platform_driver_register(&shikra_tlmm_driver); +} +arch_initcall(shikra_tlmm_init); + +static void __exit shikra_tlmm_exit(void) +{ + platform_driver_unregister(&shikra_tlmm_driver); +} +module_exit(shikra_tlmm_exit); + +MODULE_DESCRIPTION("QTI Shikra TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc..75bafa62426a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sm4250-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm4450.c b/drivers/pinctrl/qcom/pinctrl-sm4450.c index 83650f173b01..51a66a20dc66 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4450.c @@ -99,13 +99,6 @@ .intr_detection_width = -1, \ } -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - - static const struct pinctrl_pin_desc sm4450_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2..05435ea6e17a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sm6115-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index 234451fbf47b..0099c474c442 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -47,6 +47,8 @@ enum { .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -374,6 +376,7 @@ enum sm6115_functions { msm_mux_ddr_pxi1, msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -451,6 +454,11 @@ static const char * const gpio_groups[] = { "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", }; +static const char * const egpio_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", +}; static const char * const ddr_bist_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", }; @@ -681,6 +689,7 @@ static const struct pinfunction sm6115_functions[] = { MSM_PIN_FUNCTION(ddr_pxi1), MSM_PIN_FUNCTION(ddr_pxi2), MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), @@ -839,21 +848,21 @@ static const struct msm_pingroup sm6115_groups[] = { [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), - [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _), - [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), - [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _), - [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _), - [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), - [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), - [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), - [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), - [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), - [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), - [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _), - [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), - [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), - [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _), - [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, egpio), + [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, egpio), + [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, egpio), + [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, egpio), + [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), + [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), + [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio), + [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio), + [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, egpio), + [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, egpio), + [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, egpio), + [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), + [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), + [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, egpio), + [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, egpio), [113] = UFS_RESET(ufs_reset, 0x78000), [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0), [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6), @@ -886,6 +895,7 @@ static const struct msm_pinctrl_soc_data sm6115_tlmm = { .ntiles = ARRAY_SIZE(sm6115_tiles), .wakeirq_map = sm6115_mpm_map, .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map), + .egpio_func = 9, }; static int sm6115_tlmm_probe(struct platform_device *pdev) @@ -897,6 +907,7 @@ static const struct of_device_id sm6115_tlmm_of_match[] = { { .compatible = "qcom,sm6115-tlmm", }, { } }; +MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); static struct platform_driver sm6115_tlmm_driver = { .driver = { @@ -920,4 +931,3 @@ module_exit(sm6115_tlmm_exit); MODULE_DESCRIPTION("QTI sm6115 tlmm driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index 2cf9136860fc..7447ef9a4931 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -1256,6 +1256,7 @@ static const struct of_device_id sm6125_tlmm_of_match[] = { { .compatible = "qcom,sm6125-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match); static struct platform_driver sm6125_tlmm_driver = { .driver = { @@ -1279,4 +1280,3 @@ module_exit(sm6125_tlmm_exit); MODULE_DESCRIPTION("QTI sm6125 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c new file mode 100644 index 000000000000..946b23084304 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sm6350_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; + +static const struct lpi_pingroup sm6350_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP_SLEW_SPARE_1(14, 0, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sm6350_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm6350_lpi_data = { + .pins = sm6350_lpi_pins, + .npins = ARRAY_SIZE(sm6350_lpi_pins), + .groups = sm6350_groups, + .ngroups = ARRAY_SIZE(sm6350_groups), + .functions = sm6350_functions, + .nfunctions = ARRAY_SIZE(sm6350_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm6350-lpass-lpi-pinctrl", + .data = &sm6350_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm6350-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm SM6350 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c index eb8cd4aa8a97..4089c96ff736 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -1363,6 +1363,7 @@ static const struct of_device_id sm6350_tlmm_of_match[] = { { .compatible = "qcom,sm6350-tlmm" }, { }, }; +MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match); static struct platform_driver sm6350_tlmm_driver = { .driver = { @@ -1386,4 +1387,3 @@ module_exit(sm6350_tlmm_exit); MODULE_DESCRIPTION("QTI SM6350 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c index d4547dd9f21f..8da71d940b90 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6375.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c @@ -1506,6 +1506,7 @@ static const struct of_device_id sm6375_tlmm_of_match[] = { { .compatible = "qcom,sm6375-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm6375_tlmm_of_match); static struct platform_driver sm6375_tlmm_driver = { .driver = { @@ -1529,4 +1530,3 @@ module_exit(sm6375_tlmm_exit); MODULE_DESCRIPTION("QTI SM6375 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm6375_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c index 12713671243c..526cc7bb3c6c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -1532,6 +1532,7 @@ static const struct of_device_id sm8150_pinctrl_of_match[] = { { .compatible = "qcom,sm8150-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match); static struct platform_driver sm8150_pinctrl_driver = { .driver = { @@ -1555,4 +1556,3 @@ module_exit(sm8150_pinctrl_exit); MODULE_DESCRIPTION("QTI sm8150 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c index c27452eece3e..454de788be21 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -127,17 +129,22 @@ static const struct lpi_pinctrl_variant_data sm8250_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8250-lpass-lpi-pinctrl", - .data = &sm8250_lpi_data, + .compatible = "qcom,sm8250-lpass-lpi-pinctrl", + .data = &sm8250_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8250-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index f73f3b052de4..abf5f68ef62f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -1354,6 +1354,7 @@ static const struct of_device_id sm8250_pinctrl_of_match[] = { { .compatible = "qcom,sm8250-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); static struct platform_driver sm8250_pinctrl_driver = { .driver = { @@ -1377,4 +1378,3 @@ module_exit(sm8250_pinctrl_exit); MODULE_DESCRIPTION("QTI sm8250 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c index 377ddfc77e4f..8bd278c97171 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -1632,6 +1632,7 @@ static const struct of_device_id sm8350_tlmm_of_match[] = { { .compatible = "qcom,sm8350-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match); static struct platform_driver sm8350_tlmm_driver = { .driver = { @@ -1655,4 +1656,3 @@ module_exit(sm8350_tlmm_exit); MODULE_DESCRIPTION("QTI SM8350 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e..834eee8dcce9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -195,17 +197,22 @@ static const struct lpi_pinctrl_variant_data sm8450_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8450-lpass-lpi-pinctrl", - .data = &sm8450_lpi_data, + .compatible = "qcom,sm8450-lpass-lpi-pinctrl", + .data = &sm8450_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8450-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index a1d84074ea49..8ca5b6e15e6c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -1667,6 +1667,7 @@ static const struct of_device_id sm8450_tlmm_of_match[] = { { .compatible = "qcom,sm8450-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match); static struct platform_driver sm8450_tlmm_driver = { .driver = { @@ -1690,4 +1691,3 @@ module_exit(sm8450_tlmm_exit); MODULE_DESCRIPTION("QTI SM8450 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c2..875e04e5d2b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -203,17 +205,22 @@ static const struct lpi_pinctrl_variant_data sm8550_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8550-lpass-lpi-pinctrl", - .data = &sm8550_lpi_data, + .compatible = "qcom,sm8550-lpass-lpi-pinctrl", + .data = &sm8550_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8550-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index cc8fbf4d5e84..d12256d970a0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -1752,6 +1752,7 @@ static const struct of_device_id sm8550_tlmm_of_match[] = { { .compatible = "qcom,sm8550-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); static struct platform_driver sm8550_tlmm_driver = { .driver = { @@ -1775,4 +1776,3 @@ module_exit(sm8550_tlmm_exit); MODULE_DESCRIPTION("QTI SM8550 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d..bc7889c993d0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -210,17 +212,22 @@ static const struct lpi_pinctrl_variant_data sm8650_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8650-lpass-lpi-pinctrl", - .data = &sm8650_lpi_data, + .compatible = "qcom,sm8650-lpass-lpi-pinctrl", + .data = &sm8650_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8650-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8650-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index ab41292e3b4e..cf57d226c47f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -1732,6 +1732,7 @@ static const struct of_device_id sm8650_tlmm_of_match[] = { { .compatible = "qcom,sm8650-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, sm8650_tlmm_of_match); static struct platform_driver sm8650_tlmm_driver = { .driver = { @@ -1755,4 +1756,3 @@ module_exit(sm8650_tlmm_exit); MODULE_DESCRIPTION("QTI SM8650 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm8650_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c index 4cfe73f30fac..f27e55c088d5 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8750.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c @@ -1701,6 +1701,7 @@ static const struct of_device_id sm8750_tlmm_of_match[] = { { .compatible = "qcom,sm8750-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, sm8750_tlmm_of_match); static struct platform_driver sm8750_tlmm_driver = { .driver = { @@ -1724,4 +1725,3 @@ module_exit(sm8750_tlmm_exit); MODULE_DESCRIPTION("QTI SM8750 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm8750_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index d02d42513ebb..cdd61dae74cf 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1229,6 +1229,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm7550-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8010-gpio", .data = (void *) 2 }, { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 5c966d51eda7..c42dd7c736fe 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -53,7 +53,7 @@ #define PM8XXX_GPIO_PHYSICAL_OFFSET 1 /* custom pinconf parameters */ -#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1) +#define PM8XXX_QCOM_DRIVE_STRENGTH (PIN_CONFIG_END + 1) #define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2) /** @@ -97,13 +97,13 @@ struct pm8xxx_gpio { }; static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { - {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0}, + {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGTH, 0}, {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0}, }; #ifdef CONFIG_DEBUG_FS static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = { - PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true), + PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGTH, "drive-strength", NULL, true), PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true), }; #endif @@ -291,7 +291,7 @@ static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_POWER_SOURCE: arg = pin->power_source; break; - case PM8XXX_QCOM_DRIVE_STRENGH: + case PM8XXX_QCOM_DRIVE_STRENGTH: arg = pin->output_strength; break; case PIN_CONFIG_DRIVE_PUSH_PULL: @@ -373,7 +373,7 @@ static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, pin->power_source = arg; banks |= BIT(0); break; - case PM8XXX_QCOM_DRIVE_STRENGH: + case PM8XXX_QCOM_DRIVE_STRENGTH: if (arg > PMIC_GPIO_STRENGTH_LOW) { dev_err(pctrl->dev, "invalid drive strength\n"); return -EINVAL; diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index a9fe75fc45e5..8d2b8246170b 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1851,6 +1851,7 @@ static const struct of_device_id x1e80100_pinctrl_of_match[] = { { .compatible = "qcom,x1e80100-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, x1e80100_pinctrl_of_match); static struct platform_driver x1e80100_pinctrl_driver = { .driver = { @@ -1874,4 +1875,3 @@ module_exit(x1e80100_pinctrl_exit); MODULE_DESCRIPTION("QTI X1E80100 TLMM pinctrl driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, x1e80100_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c index 7d7fff538755..007d6539cece 100644 --- a/drivers/pinctrl/qcom/tlmm-test.c +++ b/drivers/pinctrl/qcom/tlmm-test.c @@ -33,7 +33,7 @@ * dynamically, rather then relying on e.g. Devicetree and phandles. */ -#define MSM_PULL_MASK GENMASK(2, 0) +#define MSM_PULL_MASK GENMASK(1, 0) #define MSM_PULL_DOWN 1 #define MSM_PULL_UP 3 #define TLMM_REG_SIZE 0x1000 @@ -581,6 +581,9 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) int ret; int i; + if (!strcmp(tlmm_reg_name, "default_region")) + return of_address_to_resource(tlmm, 0, res); + count = of_property_count_strings(tlmm, "reg-names"); if (count <= 0) { pr_err("failed to find tlmm reg name\n"); @@ -597,18 +600,14 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) return -EINVAL; } - if (!strcmp(tlmm_reg_name, "default_region")) { - ret = of_address_to_resource(tlmm, 0, res); - } else { - for (i = 0; i < count; i++) { - if (!strcmp(reg_names[i], tlmm_reg_name)) { - ret = of_address_to_resource(tlmm, i, res); - break; - } + for (i = 0; i < count; i++) { + if (!strcmp(reg_names[i], tlmm_reg_name)) { + ret = of_address_to_resource(tlmm, i, res); + break; } - if (i == count) - ret = -EINVAL; } + if (i == count) + ret = -EINVAL; kfree(reg_names); |