diff options
Diffstat (limited to 'drivers/pinctrl')
295 files changed, 26996 insertions, 4440 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 03f2e3ee065f..e1ab3a916086 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -166,6 +166,7 @@ config PINCTRL_BM1880 depends on OF && (ARCH_BITMAIN || COMPILE_TEST) default ARCH_BITMAIN select PINMUX + select GENERIC_PINCONF help Pinctrl driver for Bitmain BM1880 SoC. @@ -272,6 +273,16 @@ config PINCTRL_GEMINI select GENERIC_PINCONF select MFD_SYSCON +config PINCTRL_GENERIC_MUX + tristate "Generic Pinctrl driver by using multiplexer" + depends on OF + select MULTIPLEXER + select PINMUX + select GENERIC_PINCTRL + help + Generic pinctrl driver by MULTIPLEXER framework to control on + board pin selection. + config PINCTRL_INGENIC bool "Pinctrl driver for the Ingenic JZ47xx SoCs" default MACH_INGENIC @@ -416,6 +427,7 @@ config PINCTRL_MICROCHIP_SGPIO select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS + select REGMAP_MMIO help Support for the serial GPIO interface used on Microsemi and Microchip SoCs. By using a serial interface, the SIO @@ -476,6 +488,7 @@ config PINCTRL_PIC32 depends on MACH_PIC32 || COMPILE_TEST select PINMUX select GENERIC_PINCONF + select GPIOLIB select GPIOLIB_IRQCHIP help This is the pin controller and gpio driver for Microchip PIC32 @@ -548,9 +561,11 @@ config PINCTRL_ST config PINCTRL_STMFX tristate "STMicroelectronics STMFX GPIO expander pinctrl driver" + depends on OF depends on I2C depends on HAS_IOMEM select GENERIC_PINCONF + select GPIOLIB select GPIOLIB_IRQCHIP select MFD_STMFX help @@ -562,7 +577,7 @@ config PINCTRL_STMFX config PINCTRL_SX150X tristate "Semtech SX150x I2C GPIO expander pinctrl driver" - depends on I2C=y + depends on I2C select PINMUX select PINCONF select GENERIC_PINCONF @@ -679,6 +694,7 @@ config PINCTRL_RP1 multi function device. source "drivers/pinctrl/actions/Kconfig" +source "drivers/pinctrl/airoha/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" @@ -708,6 +724,7 @@ source "drivers/pinctrl/sunplus/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" source "drivers/pinctrl/ti/Kconfig" +source "drivers/pinctrl/ultrarisc/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/visconti/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f7d5d5f76d0c..a35d71135abf 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-$(CONFIG_PINCTRL_EP93XX) += pinctrl-ep93xx.o obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o +obj-$(CONFIG_PINCTRL_GENERIC_MUX) += pinctrl-generic-mux.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o obj-$(CONFIG_PINCTRL_K230) += pinctrl-k230.o @@ -66,7 +67,8 @@ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o obj-y += actions/ -obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-y += airoha/ +obj-$(CONFIG_PINCTRL_ASPEED) += aspeed/ obj-y += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += cirrus/ @@ -82,7 +84,7 @@ obj-y += nuvoton/ obj-y += nxp/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-y += qcom/ -obj-$(CONFIG_ARCH_REALTEK) += realtek/ +obj-$(CONFIG_PINCTRL_RTD) += realtek/ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-y += sophgo/ @@ -93,8 +95,9 @@ obj-y += starfive/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ obj-y += sunplus/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ -obj-$(CONFIG_ARCH_TEGRA) += tegra/ +obj-y += tegra/ obj-y += ti/ +obj-$(CONFIG_PINCTRL_ULTRARISC) += ultrarisc/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ -obj-$(CONFIG_ARCH_VT8500) += vt8500/ +obj-$(CONFIG_PINCTRL_WMT) += vt8500/ diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index 1f0ef4727ba7..9f5637756bd3 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -824,7 +824,7 @@ static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(data, handle_level_irq); else irq_set_handler_locked(data, handle_edge_irq); diff --git a/drivers/pinctrl/actions/pinctrl-owl.h b/drivers/pinctrl/actions/pinctrl-owl.h index dae2e8363fd5..feee7ad7e27e 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.h +++ b/drivers/pinctrl/actions/pinctrl-owl.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * OWL SoC's Pinctrl definitions * diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig new file mode 100644 index 000000000000..22b8f850cee1 --- /dev/null +++ b/drivers/pinctrl/airoha/Kconfig @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "Airoha pinctrl drivers" + depends on ARCH_AIROHA || COMPILE_TEST + +config PINCTRL_AIROHA + tristate "Airoha pin control" + depends on OF + depends on ARCH_AIROHA || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select REGMAP_MMIO + imply PINCTRL_AIROHA_AN7563 + imply PINCTRL_AIROHA_AN7581 + imply PINCTRL_AIROHA_AN7583 + imply PINCTRL_AIROHA_EN7523 + help + Shared pin controller and gpio driver code for different + Airoha SoCs. + +config PINCTRL_AIROHA_AN7563 + tristate "AN7563 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on Airoha AN7563 and other compatible SoCs. + +config PINCTRL_AIROHA_AN7581 + tristate "AN7581 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on Airoha AN7581, AN7566, AN7551 and other compatible SoCs. + +config PINCTRL_AIROHA_AN7583 + tristate "AN7583 pinctrl" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on Airoha AN7583, AN7553, AN7567 and other compatible SoCs. + +config PINCTRL_AIROHA_EN7523 + tristate "EN7523 pinctrl" + depends on ARM || COMPILE_TEST + depends on PINCTRL_AIROHA + help + Say yes here to support pin controller and gpio driver + on Airoha EN7523, EN7529, EN7562 and other compatible SoCs. + +endmenu diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile new file mode 100644 index 000000000000..30e4bee57a4a --- /dev/null +++ b/drivers/pinctrl/airoha/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +# shared code +obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o + +# SoC drivers +obj-$(CONFIG_PINCTRL_AIROHA_AN7563) += pinctrl-an7563.o +obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o +obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o +obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h new file mode 100644 index 000000000000..c1acbfb7426e --- /dev/null +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> + * Author: Markus Gothe <markus.gothe@genexis.eu> + */ + +#ifndef __AIROHA_COMMON_HEADER__ +#define __AIROHA_COMMON_HEADER__ + +#include <dt-bindings/pinctrl/mt65xx.h> +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/cleanup.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/types.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#define AIROHA_NUM_PINS 64 +#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) +#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) + +#define PINCTRL_PIN_GROUP(id, table) \ + PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) + +#define PINCTRL_FUNC_DESC(id, table) \ + { \ + .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ + ARRAY_SIZE(table##_groups)),\ + .groups = table##_func_group, \ + .group_size = ARRAY_SIZE(table##_func_group), \ + } + +#define PINCTRL_CONF_DESC(p, offset, mask) \ + { \ + .pin = p, \ + .reg = { offset, mask }, \ + } + +struct airoha_pinctrl_reg { + u32 offset; + u32 mask; +}; + +enum airoha_pinctrl_mux_func { + AIROHA_FUNC_MUX, + AIROHA_FUNC_PWM_MUX, + AIROHA_FUNC_PWM_EXT_MUX, +}; + +struct airoha_pinctrl_func_group { + const char *name; + struct { + enum airoha_pinctrl_mux_func mux; + u32 offset; + u32 mask; + u32 val; + } regmap[2]; + int regmap_size; +}; + +struct airoha_pinctrl_func { + const struct pinfunction desc; + const struct airoha_pinctrl_func_group *groups; + u8 group_size; +}; + +struct airoha_pinctrl_conf { + u32 pin; + struct airoha_pinctrl_reg reg; +}; + +struct airoha_gpiochip_regs { + /* gpio */ + const u32 *data; + const u32 *dir; + const u32 *out; + /* irq */ + const u32 *status; + const u32 *level; + const u32 *edge; +}; + +struct airoha_pinctrl_confs_info { + const struct airoha_pinctrl_conf *confs; + unsigned int num_confs; +}; + +enum airoha_pinctrl_confs_type { + AIROHA_PINCTRL_CONFS_PULLUP, + AIROHA_PINCTRL_CONFS_PULLDOWN, + AIROHA_PINCTRL_CONFS_DRIVE_E2, + AIROHA_PINCTRL_CONFS_DRIVE_E4, + AIROHA_PINCTRL_CONFS_PCIE_RST_OD, + + AIROHA_PINCTRL_CONFS_MAX, +}; + +struct airoha_pinctrl { + struct pinctrl_dev *ctrl; + + struct pinctrl_desc desc; + const struct pingroup *grps; + const struct airoha_pinctrl_func *funcs; + const struct airoha_pinctrl_confs_info *confs_info; + + struct regmap *chip_scu; + struct regmap *regmap; + + struct gpio_chip gpiochip; + struct airoha_gpiochip_regs *gpio_regs; +}; + +struct airoha_pinctrl_match_data { + const char *chip_scu_compatible; + const char *pinctrl_name; + struct module *pinctrl_owner; + const struct pinctrl_pin_desc *pins; + const unsigned int num_pins; + const struct pingroup *grps; + const unsigned int num_grps; + const struct airoha_pinctrl_func *funcs; + const unsigned int num_funcs; + const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; +}; + +int airoha_pinctrl_probe(struct platform_device *pdev); + +#endif diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c new file mode 100644 index 000000000000..f505a3f69c5d --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -0,0 +1,865 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> + * Author: Markus Gothe <markus.gothe@genexis.eu> + */ + +#include "airoha-common.h" + +/* GPIOs */ +#define REG_GPIO_CTRL 0x0000 +#define REG_GPIO_DATA 0x0004 +#define REG_GPIO_INT 0x0008 +#define REG_GPIO_INT_EDGE 0x000c +#define REG_GPIO_INT_LEVEL 0x0010 +#define REG_GPIO_OE 0x0014 +#define REG_GPIO_CTRL1 0x0020 +#define REG_GPIO_CTRL2 0x0060 +#define REG_GPIO_CTRL3 0x0064 +#define REG_GPIO_DATA1 0x0070 +#define REG_GPIO_OE1 0x0078 +#define REG_GPIO_INT1 0x007c +#define REG_GPIO_INT_EDGE1 0x0080 +#define REG_GPIO_INT_EDGE2 0x0084 +#define REG_GPIO_INT_EDGE3 0x0088 +#define REG_GPIO_INT_LEVEL1 0x008c +#define REG_GPIO_INT_LEVEL2 0x0090 +#define REG_GPIO_INT_LEVEL3 0x0094 + +#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) +#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) + +static const u32 gpio_data_regs[] = { + REG_GPIO_DATA, + REG_GPIO_DATA1 +}; + +static const u32 gpio_out_regs[] = { + REG_GPIO_OE, + REG_GPIO_OE1 +}; + +static const u32 gpio_dir_regs[] = { + REG_GPIO_CTRL, + REG_GPIO_CTRL1, + REG_GPIO_CTRL2, + REG_GPIO_CTRL3 +}; + +static const u32 irq_status_regs[] = { + REG_GPIO_INT, + REG_GPIO_INT1 +}; + +static const u32 irq_level_regs[] = { + REG_GPIO_INT_LEVEL, + REG_GPIO_INT_LEVEL1, + REG_GPIO_INT_LEVEL2, + REG_GPIO_INT_LEVEL3 +}; + +static const u32 irq_edge_regs[] = { + REG_GPIO_INT_EDGE, + REG_GPIO_INT_EDGE1, + REG_GPIO_INT_EDGE2, + REG_GPIO_INT_EDGE3 +}; + +static struct airoha_gpiochip_regs airoha_gpiochip_regs = { + .data = gpio_data_regs, + .dir = gpio_dir_regs, + .out = gpio_out_regs, + .status = irq_status_regs, + .level = irq_level_regs, + .edge = irq_edge_regs, +}; + +static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, + struct pinctrl_gpio_range *range, + int pin) +{ + if (!range) + range = pinctrl_find_gpio_range_from_pin_nolock(pctrl_dev, + pin); + if (!range) + return -EINVAL; + + return pin - range->pin_base; +} + +/* gpio callbacks */ +static int airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio, + int value) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 offset = gpio % AIROHA_PIN_BANK_SIZE; + u8 index = gpio / AIROHA_PIN_BANK_SIZE; + + return regmap_update_bits(pinctrl->regmap, + pinctrl->gpio_regs->data[index], + BIT(offset), value ? BIT(offset) : 0); +} + +static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 val, pin = gpio % AIROHA_PIN_BANK_SIZE; + u8 index = gpio / AIROHA_PIN_BANK_SIZE; + int err; + + err = regmap_read(pinctrl->regmap, + pinctrl->gpio_regs->data[index], &val); + + return err ? err : !!(val & BIT(pin)); +} + +static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 val, mask; + u8 index; + int err; + + index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; + err = regmap_read(pinctrl->regmap, + pinctrl->gpio_regs->dir[index], &val); + if (err) + return err; + + mask = BIT(2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN)); + return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + +static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio, + bool input) +{ + struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); + u32 mask, index; + int err; + + /* set output enable */ + mask = BIT(gpio % AIROHA_PIN_BANK_SIZE); + index = gpio / AIROHA_PIN_BANK_SIZE; + err = regmap_update_bits(pinctrl->regmap, + pinctrl->gpio_regs->out[index], + mask, !input ? mask : 0); + if (err) + return err; + + /* set direction */ + mask = BIT(2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN)); + index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; + + return regmap_update_bits(pinctrl->regmap, + pinctrl->gpio_regs->dir[index], mask, + !input ? mask : 0); +} + +static int airoha_gpio_direction_input(struct gpio_chip *chip, + unsigned int gpio) +{ + return airoha_gpio_set_direction(chip, gpio, true); +} + +static int airoha_gpio_direction_output(struct gpio_chip *chip, + unsigned int gpio, int value) +{ + int err; + + err = airoha_gpio_set_direction(chip, gpio, false); + if (err) + return err; + + return airoha_gpio_set(chip, gpio, value); +} + +/* irq callbacks */ +static void airoha_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs; + u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; + u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; + u32 mask = GENMASK(2 * offset + 1, 2 * offset); + u32 val = BIT(2 * offset); + + if (WARN_ON_ONCE(data->hwirq >= AIROHA_NUM_PINS)) + return; + + gpiochip_enable_irq(gc, irqd_to_hwirq(data)); + switch (irqd_get_trigger_type(data)) { + case IRQ_TYPE_LEVEL_LOW: + val = val << 1; + fallthrough; + case IRQ_TYPE_LEVEL_HIGH: + regmap_update_bits(pinctrl->regmap, gpio_regs->level[index], + mask, val); + break; + case IRQ_TYPE_EDGE_FALLING: + val = val << 1; + fallthrough; + case IRQ_TYPE_EDGE_RISING: + regmap_update_bits(pinctrl->regmap, gpio_regs->edge[index], + mask, val); + break; + case IRQ_TYPE_EDGE_BOTH: + regmap_set_bits(pinctrl->regmap, gpio_regs->edge[index], mask); + break; + default: + break; + } +} + +static void airoha_irq_mask(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs; + u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; + u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; + u32 mask = GENMASK(2 * offset + 1, 2 * offset); + + if (data->hwirq >= AIROHA_NUM_PINS) + return; + + regmap_clear_bits(pinctrl->regmap, gpio_regs->level[index], mask); + regmap_clear_bits(pinctrl->regmap, gpio_regs->edge[index], mask); + gpiochip_disable_irq(gc, irqd_to_hwirq(data)); +} + +static void airoha_irq_ack(struct irq_data *data) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc); + struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs; + u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE; + u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE; + + if (data->hwirq >= AIROHA_NUM_PINS) + return; + + regmap_write(pinctrl->regmap, gpio_regs->status[index], BIT(offset)); +} + +static int airoha_irq_type(struct irq_data *data, unsigned int type) +{ + if (data->hwirq >= AIROHA_NUM_PINS) + return -EINVAL; + + if (type == IRQ_TYPE_NONE) { + irqd_set_trigger_type(data, type); + irq_set_handler_locked(data, handle_bad_irq); + + return 0; + } + + if (type == IRQ_TYPE_PROBE) { + if (irqd_get_trigger_type(data)) + return 0; + + type = IRQ_TYPE_EDGE_BOTH; + } + + irqd_set_trigger_type(data, type); + if (type & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(data, handle_edge_irq); + else + irq_set_handler_locked(data, handle_level_irq); + + + return 0; +} + +static irqreturn_t airoha_irq_handler(int irq, void *data) +{ + struct airoha_pinctrl *pinctrl = data; + bool handled = false; + int i; + + for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) { + struct gpio_irq_chip *girq = &pinctrl->gpiochip.irq; + u32 regmap; + unsigned long status; + int irq; + + if (regmap_read(pinctrl->regmap, pinctrl->gpio_regs->status[i], + ®map)) + continue; + + status = regmap; + for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) { + u32 offset = irq + i * AIROHA_PIN_BANK_SIZE; + + generic_handle_domain_irq(girq->domain, offset); + regmap_write(pinctrl->regmap, + pinctrl->gpio_regs->status[i], BIT(irq)); + } + handled |= !!status; + } + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static const struct irq_chip airoha_gpio_irq_chip = { + .name = "airoha-gpio-irq", + .irq_unmask = airoha_irq_unmask, + .irq_mask = airoha_irq_mask, + .irq_ack = airoha_irq_ack, + .irq_set_type = airoha_irq_type, + .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, + struct platform_device *pdev) +{ + struct gpio_chip *gc = &pinctrl->gpiochip; + struct gpio_irq_chip *girq = &gc->irq; + struct device *dev = &pdev->dev; + int irq, err; + + gc->parent = dev; + gc->label = dev_name(dev); + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->direction_input = airoha_gpio_direction_input; + gc->direction_output = airoha_gpio_direction_output; + gc->get_direction = airoha_gpio_get_direction; + gc->set = airoha_gpio_set; + gc->get = airoha_gpio_get; + gc->base = -1; + gc->ngpio = AIROHA_NUM_PINS; + + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED, + dev_name(dev), pinctrl); + if (err) + return err; + + return devm_gpiochip_add_data(dev, gc, pinctrl); +} + +/* pinmux callbacks */ +static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, + unsigned int selector, + unsigned int group) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct airoha_pinctrl_func *func; + const struct function_desc *desc; + struct group_desc *grp; + int i; + + desc = pinmux_generic_get_function(pctrl_dev, selector); + if (!desc) + return -EINVAL; + + grp = pinctrl_generic_get_group(pctrl_dev, group); + if (!grp) + return -EINVAL; + + dev_dbg(pctrl_dev->dev, "enable function %s group %s\n", + desc->func->name, grp->grp.name); + + func = desc->data; + for (i = 0; i < func->group_size; i++) { + const struct airoha_pinctrl_func_group *group; + int j; + + group = &func->groups[i]; + if (strcmp(group->name, grp->grp.name)) + continue; + + for (j = 0; j < group->regmap_size; j++) { + switch (group->regmap[j].mux) { + case AIROHA_FUNC_PWM_EXT_MUX: + case AIROHA_FUNC_PWM_MUX: + regmap_update_bits(pinctrl->regmap, + group->regmap[j].offset, + group->regmap[j].mask, + group->regmap[j].val); + break; + default: + regmap_update_bits(pinctrl->chip_scu, + group->regmap[j].offset, + group->regmap[j].mask, + group->regmap[j].val); + break; + } + } + return 0; + } + + return -EINVAL; +} + +static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev, + struct pinctrl_gpio_range *range, + unsigned int p, bool input) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + int pin; + + pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p); + if (pin < 0) + return pin; + + return airoha_gpio_set_direction(&pinctrl->gpiochip, pin, input); +} + +static const struct pinmux_ops airoha_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .gpio_set_direction = airoha_pinmux_set_direction, + .set_mux = airoha_pinmux_set_mux, + .strict = true, +}; + +/* pinconf callbacks */ +static const struct airoha_pinctrl_reg * +airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf, + int conf_size, int pin) +{ + int i; + + for (i = 0; i < conf_size; i++) { + if (conf[i].pin == pin) + return &conf[i].reg; + } + + return NULL; +} + +static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, + enum airoha_pinctrl_confs_type conf_type, + int pin, u32 *val) +{ + const struct airoha_pinctrl_confs_info *confs_info; + const struct airoha_pinctrl_reg *reg; + + confs_info = &pinctrl->confs_info[conf_type]; + + reg = airoha_pinctrl_get_conf_reg(confs_info->confs, + confs_info->num_confs, + pin); + if (!reg) + return -EINVAL; + + if (regmap_read(pinctrl->chip_scu, reg->offset, val)) + return -EINVAL; + + *val = field_get(reg->mask, *val); + + return 0; +} + +static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, + enum airoha_pinctrl_confs_type conf_type, + int pin, u32 val) +{ + const struct airoha_pinctrl_confs_info *confs_info; + const struct airoha_pinctrl_reg *reg = NULL; + + confs_info = &pinctrl->confs_info[conf_type]; + + reg = airoha_pinctrl_get_conf_reg(confs_info->confs, + confs_info->num_confs, + pin); + if (!reg) + return -EINVAL; + + + if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask, + field_prep(reg->mask, val))) + return -EINVAL; + + return 0; +} + +static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + int ret, pin; + + pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); + if (pin < 0) + return pin; + + ret = airoha_gpio_get_direction(&pinctrl->gpiochip, pin); + if (ret < 0) + return ret; + + return ret == GPIO_LINE_DIRECTION_OUT ? + PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE; +} + +static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev, + unsigned int pin, unsigned long *config) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 arg; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: { + u32 pull_up, pull_down; + + if (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) || + airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down)) + return -EINVAL; + + if (param == PIN_CONFIG_BIAS_PULL_UP && + !(pull_up && !pull_down)) + return -EINVAL; + else if (param == PIN_CONFIG_BIAS_PULL_DOWN && + !(pull_down && !pull_up)) + return -EINVAL; + else if (pull_up || pull_down) + return -EINVAL; + + arg = 1; + break; + } + case PIN_CONFIG_DRIVE_STRENGTH: { + u32 e2, e4; + + if (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) || + airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4)) + return -EINVAL; + + arg = e4 << 1 | e2; + break; + } + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg)) + return -EINVAL; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: + arg = airoha_pinconf_get_direction(pctrl_dev, pin); + if (arg != param) + return -EINVAL; + + arg = 1; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev, + unsigned int p, bool value) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + int pin; + + pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); + if (pin < 0) + return pin; + + return airoha_gpio_set(&pinctrl->gpiochip, pin, value); +} + +static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + int i, err; + + for (i = 0; i < num_configs; i++) { + u32 param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + if (err) + return err; + + break; + + case PIN_CONFIG_BIAS_PULL_UP: + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1); + if (err) + return err; + + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + if (err) + return err; + + break; + case PIN_CONFIG_DRIVE_STRENGTH: { + u32 e2 = 0, e4 = 0; + + switch (arg) { + case MTK_DRIVE_2mA: + break; + case MTK_DRIVE_4mA: + e2 = 1; + break; + case MTK_DRIVE_6mA: + e4 = 1; + break; + case MTK_DRIVE_8mA: + e2 = 1; + e4 = 1; + break; + default: + return -EINVAL; + } + + err = airoha_pinctrl_set_drive_e2_conf(pinctrl, + pin, e2); + if (err) + return err; + + err = airoha_pinctrl_set_drive_e4_conf(pinctrl, + pin, e4); + if (err) + return err; + + break; + } + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + err = airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, + pin, !!arg); + if (err) + return err; + + break; + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_LEVEL: { + bool input = param == PIN_CONFIG_INPUT_ENABLE; + + err = airoha_pinmux_set_direction(pctrl_dev, NULL, pin, + input); + if (err) + return err; + + if (param == PIN_CONFIG_LEVEL) { + err = airoha_pinconf_set_pin_value(pctrl_dev, + pin, !!arg); + if (err) + return err; + } + break; + } + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev, + unsigned int group, unsigned long *config) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + unsigned long cur_config = 0; + int i; + + for (i = 0; i < pinctrl->grps[group].npins; i++) { + if (airoha_pinconf_get(pctrl_dev, + pinctrl->grps[group].pins[i], + config)) + return -ENOTSUPP; + + if (i && cur_config != *config) + return -ENOTSUPP; + + cur_config = *config; + } + + return 0; +} + +static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev, + unsigned int group, unsigned long *configs, + unsigned int num_configs) +{ + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + int i; + + for (i = 0; i < pinctrl->grps[group].npins; i++) { + int err; + + err = airoha_pinconf_set(pctrl_dev, + pinctrl->grps[group].pins[i], + configs, num_configs); + if (err) + return err; + } + + return 0; +} + +static const struct pinconf_ops airoha_confops = { + .is_generic = true, + .pin_config_get = airoha_pinconf_get, + .pin_config_set = airoha_pinconf_set, + .pin_config_group_get = airoha_pinconf_group_get, + .pin_config_group_set = airoha_pinconf_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static const struct pinctrl_ops airoha_pctlops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +int airoha_pinctrl_probe(struct platform_device *pdev) +{ + const struct airoha_pinctrl_match_data *data; + struct device *dev = &pdev->dev; + struct airoha_pinctrl *pinctrl; + struct regmap *map; + int err, i; + + data = device_get_match_data(dev); + if (!data) + return -EINVAL; + + pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL); + if (!pinctrl) + return -ENOMEM; + + pinctrl->regmap = device_node_to_regmap(dev->parent->of_node); + if (IS_ERR(pinctrl->regmap)) + return PTR_ERR(pinctrl->regmap); + + map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "airoha,chip-scu"); + if (IS_ERR_OR_NULL(map)) { + map = syscon_regmap_lookup_by_compatible(data->chip_scu_compatible); + if (IS_ERR(map)) + return PTR_ERR(map); + } + + pinctrl->chip_scu = map; + + /* Init pinctrl desc struct */ + pinctrl->desc.name = data->pinctrl_name; + pinctrl->desc.owner = data->pinctrl_owner; + pinctrl->desc.pctlops = &airoha_pctlops; + pinctrl->desc.pmxops = &airoha_pmxops; + pinctrl->desc.confops = &airoha_confops; + pinctrl->desc.pins = data->pins; + pinctrl->desc.npins = data->num_pins; + + pinctrl->gpio_regs = &airoha_gpiochip_regs; + + err = devm_pinctrl_register_and_init(dev, &pinctrl->desc, + pinctrl, &pinctrl->ctrl); + if (err) + return err; + + /* build pin groups */ + for (i = 0; i < data->num_grps; i++) { + const struct pingroup *grp = &data->grps[i]; + + err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name, + grp->pins, grp->npins, + (void *)grp); + if (err < 0) { + dev_err(&pdev->dev, "Failed to register group %s\n", + grp->name); + return err; + } + } + + /* build functions */ + for (i = 0; i < data->num_funcs; i++) { + const struct airoha_pinctrl_func *func; + + func = &data->funcs[i]; + err = pinmux_generic_add_pinfunction(pinctrl->ctrl, + &func->desc, + (void *)func); + if (err < 0) { + dev_err(dev, "Failed to register function %s\n", + func->desc.name); + return err; + } + } + + pinctrl->grps = data->grps; + pinctrl->funcs = data->funcs; + pinctrl->confs_info = data->confs_info; + + err = pinctrl_enable(pinctrl->ctrl); + if (err) + return err; + + /* build gpio-chip */ + return airoha_pinctrl_add_gpiochip(pinctrl, pdev); +} +EXPORT_SYMBOL_GPL(airoha_pinctrl_probe); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); +MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-an7563.c b/drivers/pinctrl/airoha/pinctrl-an7563.c new file mode 100644 index 000000000000..40cbbe90cc46 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7563.c @@ -0,0 +1,1115 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AN7563 SoC pinctrl data for the Airoha pinctrl driver (pinctrl-airoha.c). + * + * Sources: AN7563 Programming Guide chapter 2 (CHIP SCU, base 0x1fa20000), + * chapter 17 (GPIO controller, base 0x1fbf0200) and AN7563PT datasheet + * chapter 4.3 (pin sharing scheme). + * + * Pin numbering follows the GPIO line numbering of the SoC: + * pins 0-27 -> GPIO0-GPIO27 (dedicated GPIO pads) + * pins 28/29 -> PCIE_RESET0/PCIE_RESET1 pads (GPIO28/GPIO29) + * pins 30/31 -> I2C_SCL/I2C_SDA pads (GPIO30/GPIO31) + * pins 32-35 -> SPI_CLK/SPI_CS/SPI_MOSI/SPI_MISO pads (GPIO32-GPIO35) + * pins 36/37 -> UART_TXD/UART_RXD pads (GPIO36/GPIO37) + * + * Definitions marked "shared" are identical to the ones already present in + * pinctrl-airoha.c (EN7581/AN7583) and must be dropped when this data is + * merged there. + */ + +#include "airoha-common.h" + +/* + * shared - named RG_SW_TOD_1PPS_MODE on AN7563. Only the LAN LED mode + * bits and GSW_TOD_1PPS exist on AN7563 (no 2nd I2C, I2S or PON 1PPS). + */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) + +/* shared */ +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +/* + * AN7563 specific: route the standalone pads to their GPIO function. + * 0: pad keeps its base function, 1: pad is GPIO<n>. + */ +#define UART_RXD_GPIO_MODE_MASK BIT(22) /* GPIO37 */ +#define UART_TXD_GPIO_MODE_MASK BIT(21) /* GPIO36 */ +#define SPI_MISO_GPIO_MODE_MASK BIT(20) /* GPIO35 */ +#define SPI_MOSI_GPIO_MODE_MASK BIT(19) /* GPIO34 */ +#define SPI_CS_GPIO_MODE_MASK BIT(18) /* GPIO33 */ +#define SPI_CLK_GPIO_MODE_MASK BIT(17) /* GPIO32 */ +#define I2C_SDA_GPIO_MODE_MASK BIT(16) /* GPIO31 */ +#define I2C_SCL_GPIO_MODE_MASK BIT(15) /* GPIO30 */ +/* shared */ +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define SIPO_RCLK_MODE_MASK BIT(11) +/* + * Note: on AN7563 GPIO_PCIE_RESET{0,1} select the GPIO function of the + * PCIE_RESET pads (0: PCIe reset, 1: GPIO28/GPIO29). + */ +#define GPIO_PCIE_RESET1_MASK BIT(10) /* GPIO29 */ +#define GPIO_PCIE_RESET0_MASK BIT(9) /* GPIO28 */ +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_PON_MODE_MASK BIT(0) + +/* shared */ +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +/* LED MAP - shared */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* + * CONF - shared. + * The AN7563 standalone IO conf registers use the same bit layout as + * EN7581 (UART1_TXD/RXD are named UART_TXD/RXD on AN7563). + */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* + * PWM MODE CONF - shared. + * The AN7563 GPIO flash mode registers use the same layout as EN7581: + * REG_GPIO_FLASH_MODE_CFG covers GPIO0-15, REG_GPIO_FLASH_MODE_CFG_EXT + * covers GPIO16-31 (bits 0-15) and GPIO36+ (bits 16+). The SPI pads + * (GPIO32-35) have no flash mode configuration bit. + */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static const struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "pcie_reset0"), /* GPIO28 */ + PINCTRL_PIN(29, "pcie_reset1"), /* GPIO29 */ + PINCTRL_PIN(30, "i2c_scl"), /* GPIO30 */ + PINCTRL_PIN(31, "i2c_sda"), /* GPIO31 */ + PINCTRL_PIN(32, "spi_clk"), /* GPIO32 */ + PINCTRL_PIN(33, "spi_cs"), /* GPIO33 */ + PINCTRL_PIN(34, "spi_mosi"), /* GPIO34 */ + PINCTRL_PIN(35, "spi_miso"), /* GPIO35 */ + PINCTRL_PIN(36, "uart_txd"), /* GPIO36 */ + PINCTRL_PIN(37, "uart_rxd"), /* GPIO37 */ +}; + +static const int pon_pins[] = { 14, 15, 16, 17, 18, 19 }; +static const int sipo_pins[] = { 20, 21 }; +static const int sipo_rclk_pins[] = { 20, 21, 26 }; +static const int mdio_pins[] = { 30, 31 }; +static const int hsuart_pins[] = { 16, 17 }; +static const int hsuart_cts_rts_pins[] = { 14, 15 }; +static const int i2c_pins[] = { 30, 31 }; +static const int jtag_udi_pins[] = { 7, 8, 9, 10, 11 }; +static const int jtag_dfd_pins[] = { 7, 8, 9, 10, 11 }; +static const int pcm1_pins[] = { 22, 23, 24, 25 }; +static const int pcm2_pins[] = { 1, 2, 3, 4 }; +static const int spi_pins[] = { 32, 33, 34, 35 }; +static const int spi_quad_pins[] = { 2, 3 }; +static const int spi_cs1_pins[] = { 4 }; +static const int pnand_pins[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 32, 33, 34, 35 +}; +static const int gpio0_pins[] = { 0 }; +static const int gpio1_pins[] = { 1 }; +static const int gpio2_pins[] = { 2 }; +static const int gpio3_pins[] = { 3 }; +static const int gpio4_pins[] = { 4 }; +static const int gpio5_pins[] = { 5 }; +static const int gpio6_pins[] = { 6 }; +static const int gpio7_pins[] = { 7 }; +static const int gpio8_pins[] = { 8 }; +static const int gpio9_pins[] = { 9 }; +static const int gpio10_pins[] = { 10 }; +static const int gpio11_pins[] = { 11 }; +static const int gpio12_pins[] = { 12 }; +static const int gpio13_pins[] = { 13 }; +static const int gpio14_pins[] = { 14 }; +static const int gpio15_pins[] = { 15 }; +static const int gpio16_pins[] = { 16 }; +static const int gpio17_pins[] = { 17 }; +static const int gpio18_pins[] = { 18 }; +static const int gpio19_pins[] = { 19 }; +static const int gpio20_pins[] = { 20 }; +static const int gpio21_pins[] = { 21 }; +static const int gpio22_pins[] = { 22 }; +static const int gpio23_pins[] = { 23 }; +static const int gpio24_pins[] = { 24 }; +static const int gpio25_pins[] = { 25 }; +static const int gpio26_pins[] = { 26 }; +static const int gpio27_pins[] = { 27 }; +static const int gpio28_pins[] = { 28 }; +static const int gpio29_pins[] = { 29 }; +static const int gpio30_pins[] = { 30 }; +static const int gpio31_pins[] = { 31 }; +static const int gpio32_pins[] = { 32 }; +static const int gpio33_pins[] = { 33 }; +static const int gpio34_pins[] = { 34 }; +static const int gpio35_pins[] = { 35 }; +static const int gpio36_pins[] = { 36 }; +static const int gpio37_pins[] = { 37 }; +static const int pcie_reset0_pins[] = { 28 }; +static const int pcie_reset1_pins[] = { 29 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("i2c", i2c), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +/* shared */ +static const char *const pon_groups[] = { "pon" }; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "hsuart", "hsuart_cts_rts" +}; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio34", "gpio35", "gpio36", "gpio37" +}; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37" +}; +static const char *const phy1_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy2_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy3_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy4_led0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy1_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char *const phy2_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char *const phy3_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char *const phy4_led1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +/* shared */ +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* + * On AN7563 the SMI master (MDC/MDIO) is shared with the I2C_SCL/I2C_SDA + * pads and selected via the SGMII MDIO mode bit. I2C is the default pad + * function (no mux bit). + */ +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +/* shared */ +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio30", GPIO30_FLASH_MODE_CFG, + I2C_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio31", GPIO31_FLASH_MODE_CFG, + I2C_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio32", SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio33", SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio34", SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio35", SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio36", GPIO36_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio37", GPIO37_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), +}; + +/* + * On AN7563 a set GPIO_PCIE_RESET{0,1} bit routes the pad to its GPIO + * function, so the PCIe reset function must clear it. + */ +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio30", GPIO30_FLASH_MODE_CFG, + I2C_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio31", GPIO31_FLASH_MODE_CFG, + I2C_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio36", GPIO36_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio37", GPIO37_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), +}; + +/* + * LED pad mapping (datasheet table 4-9): + * GPIO8: LAN0_LED0, GPIO9: LAN1_LED0, GPIO10: LAN2_LED0, GPIO11: LAN3_LED0 + * GPIO7: LAN0_LED1, GPIO6: LAN1_LED1, GPIO5: LAN2_LED1, GPIO4: LAN3_LED1 + */ +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio8", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio9", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio10", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio11", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(0, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(1, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(28, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(29, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(30, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(31, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(32, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(33, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(34, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(35, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(36, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(37, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(28, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(29, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7581-chip-scu", + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,an7563-pinctrl", .data = &pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-an7563", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7563 SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c new file mode 100644 index 000000000000..2fcf88106e11 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -0,0 +1,1487 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> + * Author: Markus Gothe <markus.gothe@genexis.eu> + */ + +#include "airoha-common.h" + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) +#define GPIO_I2C_MASTER_MODE_MODE BIT(13) +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_PCIE_RESET2_MASK BIT(12) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE2_RESET_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE2_RESET_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE2_RESET_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE2_RESET_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE2_RESET_OD_MASK BIT(2) +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(0, "uart1_txd"), + PINCTRL_PIN(1, "uart1_rxd"), + PINCTRL_PIN(2, "i2c_scl"), + PINCTRL_PIN(3, "i2c_sda"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(13, "gpio0"), + PINCTRL_PIN(14, "gpio1"), + PINCTRL_PIN(15, "gpio2"), + PINCTRL_PIN(16, "gpio3"), + PINCTRL_PIN(17, "gpio4"), + PINCTRL_PIN(18, "gpio5"), + PINCTRL_PIN(19, "gpio6"), + PINCTRL_PIN(20, "gpio7"), + PINCTRL_PIN(21, "gpio8"), + PINCTRL_PIN(22, "gpio9"), + PINCTRL_PIN(23, "gpio10"), + PINCTRL_PIN(24, "gpio11"), + PINCTRL_PIN(25, "gpio12"), + PINCTRL_PIN(26, "gpio13"), + PINCTRL_PIN(27, "gpio14"), + PINCTRL_PIN(28, "gpio15"), + PINCTRL_PIN(29, "gpio16"), + PINCTRL_PIN(30, "gpio17"), + PINCTRL_PIN(31, "gpio18"), + PINCTRL_PIN(32, "gpio19"), + PINCTRL_PIN(33, "gpio20"), + PINCTRL_PIN(34, "gpio21"), + PINCTRL_PIN(35, "gpio22"), + PINCTRL_PIN(36, "gpio23"), + PINCTRL_PIN(37, "gpio24"), + PINCTRL_PIN(38, "gpio25"), + PINCTRL_PIN(39, "gpio26"), + PINCTRL_PIN(40, "gpio27"), + PINCTRL_PIN(41, "gpio28"), + PINCTRL_PIN(42, "gpio29"), + PINCTRL_PIN(43, "gpio30"), + PINCTRL_PIN(44, "gpio31"), + PINCTRL_PIN(45, "gpio32"), + PINCTRL_PIN(46, "gpio33"), + PINCTRL_PIN(47, "gpio34"), + PINCTRL_PIN(48, "gpio35"), + PINCTRL_PIN(49, "gpio36"), + PINCTRL_PIN(50, "gpio37"), + PINCTRL_PIN(51, "gpio38"), + PINCTRL_PIN(52, "gpio39"), + PINCTRL_PIN(53, "gpio40"), + PINCTRL_PIN(54, "gpio41"), + PINCTRL_PIN(55, "gpio42"), + PINCTRL_PIN(56, "gpio43"), + PINCTRL_PIN(57, "gpio44"), + PINCTRL_PIN(58, "gpio45"), + PINCTRL_PIN(59, "gpio46"), + PINCTRL_PIN(60, "pcie_reset0"), + PINCTRL_PIN(61, "pcie_reset1"), + PINCTRL_PIN(62, "pcie_reset2"), +}; + +static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 }; +static const int pon_tod_1pps_pins[] = { 46 }; +static const int gsw_tod_1pps_pins[] = { 46 }; +static const int sipo_pins[] = { 16, 17 }; +static const int sipo_rclk_pins[] = { 16, 17, 43 }; +static const int mdio_pins[] = { 14, 15 }; +static const int uart2_pins[] = { 48, 55 }; +static const int uart2_cts_rts_pins[] = { 46, 47 }; +static const int hsuart_pins[] = { 28, 29 }; +static const int hsuart_cts_rts_pins[] = { 26, 27 }; +static const int uart4_pins[] = { 38, 39 }; +static const int uart5_pins[] = { 18, 19 }; +static const int i2c0_pins[] = { 2, 3 }; +static const int i2c1_pins[] = { 14, 15 }; +static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; +static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; +static const int i2s_pins[] = { 26, 27, 28, 29 }; +static const int pcm1_pins[] = { 22, 23, 24, 25 }; +static const int pcm2_pins[] = { 18, 19, 20, 21 }; +static const int spi_quad_pins[] = { 32, 33 }; +static const int spi_pins[] = { 4, 5, 6, 7 }; +static const int spi_cs1_pins[] = { 34 }; +static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; +static const int pcm_spi_int_pins[] = { 14 }; +static const int pcm_spi_rst_pins[] = { 15 }; +static const int pcm_spi_cs1_pins[] = { 43 }; +static const int pcm_spi_cs2_pins[] = { 40 }; +static const int pcm_spi_cs2_p128_pins[] = { 40 }; +static const int pcm_spi_cs2_p156_pins[] = { 40 }; +static const int pcm_spi_cs3_pins[] = { 41 }; +static const int pcm_spi_cs4_pins[] = { 42 }; +static const int emmc_pins[] = { + 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 +}; +static const int pnand_pins[] = { + 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 +}; +static const int gpio0_pins[] = { 13 }; +static const int gpio1_pins[] = { 14 }; +static const int gpio2_pins[] = { 15 }; +static const int gpio3_pins[] = { 16 }; +static const int gpio4_pins[] = { 17 }; +static const int gpio5_pins[] = { 18 }; +static const int gpio6_pins[] = { 19 }; +static const int gpio7_pins[] = { 20 }; +static const int gpio8_pins[] = { 21 }; +static const int gpio9_pins[] = { 22 }; +static const int gpio10_pins[] = { 23 }; +static const int gpio11_pins[] = { 24 }; +static const int gpio12_pins[] = { 25 }; +static const int gpio13_pins[] = { 26 }; +static const int gpio14_pins[] = { 27 }; +static const int gpio15_pins[] = { 28 }; +static const int gpio16_pins[] = { 29 }; +static const int gpio17_pins[] = { 30 }; +static const int gpio18_pins[] = { 31 }; +static const int gpio19_pins[] = { 32 }; +static const int gpio20_pins[] = { 33 }; +static const int gpio21_pins[] = { 34 }; +static const int gpio22_pins[] = { 35 }; +static const int gpio23_pins[] = { 36 }; +static const int gpio24_pins[] = { 37 }; +static const int gpio25_pins[] = { 38 }; +static const int gpio26_pins[] = { 39 }; +static const int gpio27_pins[] = { 40 }; +static const int gpio28_pins[] = { 41 }; +static const int gpio29_pins[] = { 42 }; +static const int gpio30_pins[] = { 43 }; +static const int gpio31_pins[] = { 44 }; +static const int gpio32_pins[] = { 45 }; +static const int gpio33_pins[] = { 46 }; +static const int gpio34_pins[] = { 47 }; +static const int gpio35_pins[] = { 48 }; +static const int gpio36_pins[] = { 49 }; +static const int gpio37_pins[] = { 50 }; +static const int gpio38_pins[] = { 51 }; +static const int gpio39_pins[] = { 52 }; +static const int gpio40_pins[] = { 53 }; +static const int gpio41_pins[] = { 54 }; +static const int gpio42_pins[] = { 55 }; +static const int gpio43_pins[] = { 56 }; +static const int gpio44_pins[] = { 57 }; +static const int gpio45_pins[] = { 58 }; +static const int gpio46_pins[] = { 59 }; +static const int gpio47_pins[] = { 60 }; +static const int gpio48_pins[] = { 61 }; +static const int gpio49_pins[] = { 62 }; +static const int pcie_reset0_pins[] = { 60 }; +static const int pcie_reset1_pins[] = { 61 }; +static const int pcie_reset2_pins[] = { 62 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("gpio47", gpio47), + PINCTRL_PIN_GROUP("gpio48", gpio48), + PINCTRL_PIN_GROUP("gpio49", gpio49), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), + PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", + "uart4", "uart5" +}; +static const char *const i2c_groups[] = { "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", + "pcm_spi_cs4" +}; +static const char *const i2s_groups[] = { "i2s" }; +static const char *const emmc_groups[] = { "emmc" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" }; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1", "pcie_reset2" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49" +}; +static const char *const phy1_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy2_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy3_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy4_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy1_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy2_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy3_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy4_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_MDC_IO_MASTER_MODE_MASK, + GPIO_MDC_IO_MASTER_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO_EN, + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE, + GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p128", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p156", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] = { + { + .name = "i2s", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] = { + { + .name = "emmc", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET2_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), + PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7581-chip-scu", + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-an7581", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c new file mode 100644 index 000000000000..2c3a75c35915 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -0,0 +1,1517 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> + * Author: Markus Gothe <markus.gothe@genexis.eu> + */ + +#include "airoha-common.h" + +/* MUX */ +#define REG_SW_TOD_1PPS_MODE 0x0214 +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define GPIO_PON_ALT_MODE_MASK BIT(27) +#define MDIO_0_GPIO_MODE_MASK BIT(26) +#define MDC_0_GPIO_MODE_MASK BIT(25) +#define UART_RXD_GPIO_MODE_MASK BIT(24) +#define UART_TXD_GPIO_MODE_MASK BIT(23) +#define SPI_MISO_GPIO_MODE_MASK BIT(22) +#define SPI_MOSI_GPIO_MODE_MASK BIT(21) +#define SPI_CS_GPIO_MODE_MASK BIT(20) +#define SPI_CLK_GPIO_MODE_MASK BIT(19) +#define I2C1_SDA_GPIO_MODE_MASK BIT(18) +#define I2C1_SCL_GPIO_MODE_MASK BIT(17) +#define I2C0_SDA_GPIO_MODE_MASK BIT(16) +#define I2C0_SCL_GPIO_MODE_MASK BIT(15) +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_OLT_MODE_MASK BIT(12) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) +#define NPU_UART_EN_MASK BIT(2) + +#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define I2C1_SCL_E2_MASK BIT(16) +#define I2C1_SDA_E2_MASK BIT(15) +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define MDIO_0_E2_MASK BIT(5) +#define MDC_0_E2_MASK BIT(4) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define I2C1_SCL_E4_MASK BIT(16) +#define I2C1_SDA_E4_MASK BIT(15) +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define MDIO_0_E4_MASK BIT(5) +#define MDC_0_E4_MASK BIT(4) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define I2C1_SCL_PU_MASK BIT(16) +#define I2C1_SDA_PU_MASK BIT(15) +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define MDIO_0_PU_MASK BIT(5) +#define MDC_0_PU_MASK BIT(4) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define I2C1_SCL_PD_MASK BIT(16) +#define I2C1_SDA_PD_MASK BIT(15) +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define MDIO_0_PD_MASK BIT(5) +#define MDC_0_PD_MASK BIT(4) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_SW_TOD_1PPS_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_SW_TOD_1PPS_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(2, "gpio0"), + PINCTRL_PIN(3, "gpio1"), + PINCTRL_PIN(4, "gpio2"), + PINCTRL_PIN(5, "gpio3"), + PINCTRL_PIN(6, "gpio4"), + PINCTRL_PIN(7, "gpio5"), + PINCTRL_PIN(8, "gpio6"), + PINCTRL_PIN(9, "gpio7"), + PINCTRL_PIN(10, "gpio8"), + PINCTRL_PIN(11, "gpio9"), + PINCTRL_PIN(12, "gpio10"), + PINCTRL_PIN(13, "gpio11"), + PINCTRL_PIN(14, "gpio12"), + PINCTRL_PIN(15, "gpio13"), + PINCTRL_PIN(16, "gpio14"), + PINCTRL_PIN(17, "gpio15"), + PINCTRL_PIN(18, "gpio16"), + PINCTRL_PIN(19, "gpio17"), + PINCTRL_PIN(20, "gpio18"), + PINCTRL_PIN(21, "gpio19"), + PINCTRL_PIN(22, "gpio20"), + PINCTRL_PIN(23, "gpio21"), + PINCTRL_PIN(24, "gpio22"), + PINCTRL_PIN(25, "gpio23"), + PINCTRL_PIN(26, "gpio24"), + PINCTRL_PIN(27, "gpio25"), + PINCTRL_PIN(28, "gpio26"), + PINCTRL_PIN(29, "gpio27"), + PINCTRL_PIN(30, "gpio28"), + PINCTRL_PIN(31, "gpio29"), + PINCTRL_PIN(32, "gpio30"), + PINCTRL_PIN(33, "gpio31"), + PINCTRL_PIN(34, "gpio32"), + PINCTRL_PIN(35, "gpio33"), + PINCTRL_PIN(36, "gpio34"), + PINCTRL_PIN(37, "gpio35"), + PINCTRL_PIN(38, "gpio36"), + PINCTRL_PIN(39, "gpio37"), + PINCTRL_PIN(40, "gpio38"), + PINCTRL_PIN(41, "i2c0_scl"), + PINCTRL_PIN(42, "i2c0_sda"), + PINCTRL_PIN(43, "i2c1_scl"), + PINCTRL_PIN(44, "i2c1_sda"), + PINCTRL_PIN(45, "spi_clk"), + PINCTRL_PIN(46, "spi_cs"), + PINCTRL_PIN(47, "spi_mosi"), + PINCTRL_PIN(48, "spi_miso"), + PINCTRL_PIN(49, "uart_txd"), + PINCTRL_PIN(50, "uart_rxd"), + PINCTRL_PIN(51, "pcie_reset0"), + PINCTRL_PIN(52, "pcie_reset1"), + PINCTRL_PIN(53, "mdc_0"), + PINCTRL_PIN(54, "mdio_0"), +}; + +static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 }; +static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 }; +static const int olt_pins[] = { 36, 37, 38, 39, 40 }; +static const int pon_tod_1pps_pins[] = { 32 }; +static const int gsw_tod_1pps_pins[] = { 32 }; +static const int sipo_pins[] = { 34, 35 }; +static const int sipo_rclk_pins[] = { 34, 35, 33 }; +static const int mdio_pins[] = { 53, 54 }; +static const int mdio1_pins[] = { 43, 44 }; +static const int uart2_pins[] = { 34, 35 }; +static const int uart2_cts_rts_pins[] = { 32, 33 }; +static const int hsuart_pins[] = { 30, 31 }; +static const int hsuart_cts_rts_pins[] = { 28, 29 }; +static const int npu_uart_pins[] = { 7, 8 }; +static const int uart4_pins[] = { 7, 8 }; +static const int uart5_pins[] = { 23, 24 }; +static const int i2c0_pins[] = { 41, 42 }; +static const int i2c1_pins[] = { 43, 44 }; +static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; +static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; +static const int pcm1_pins[] = { 10, 11, 12, 13, 14 }; +static const int pcm2_pins[] = { 28, 29, 30, 31, 24 }; +static const int spi_pins[] = { 45, 46, 47, 48 }; +static const int spi_quad_pins[] = { 25, 26 }; +static const int spi_cs1_pins[] = { 27 }; +static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; +static const int pcm_spi_rst_pins[] = { 14 }; +static const int pcm_spi_cs1_pins[] = { 24 }; +static const int emmc_pins[] = { + 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 +}; +static const int pnand_pins[] = { + 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 +}; +static const int gpio0_pins[] = { 2 }; +static const int gpio1_pins[] = { 3 }; +static const int gpio2_pins[] = { 4 }; +static const int gpio3_pins[] = { 5 }; +static const int gpio4_pins[] = { 6 }; +static const int gpio5_pins[] = { 7 }; +static const int gpio6_pins[] = { 8 }; +static const int gpio7_pins[] = { 9 }; +static const int gpio8_pins[] = { 10 }; +static const int gpio9_pins[] = { 11 }; +static const int gpio10_pins[] = { 12 }; +static const int gpio11_pins[] = { 13 }; +static const int gpio12_pins[] = { 14 }; +static const int gpio13_pins[] = { 15 }; +static const int gpio14_pins[] = { 16 }; +static const int gpio15_pins[] = { 17 }; +static const int gpio16_pins[] = { 18 }; +static const int gpio17_pins[] = { 19 }; +static const int gpio18_pins[] = { 20 }; +static const int gpio19_pins[] = { 21 }; +static const int gpio20_pins[] = { 22 }; +static const int gpio21_pins[] = { 23 }; +static const int gpio22_pins[] = { 24 }; +static const int gpio23_pins[] = { 25 }; +static const int gpio24_pins[] = { 26 }; +static const int gpio25_pins[] = { 27 }; +static const int gpio26_pins[] = { 28 }; +static const int gpio27_pins[] = { 29 }; +static const int gpio28_pins[] = { 30 }; +static const int gpio29_pins[] = { 31 }; +static const int gpio30_pins[] = { 32 }; +static const int gpio31_pins[] = { 33 }; +static const int gpio32_pins[] = { 34 }; +static const int gpio33_pins[] = { 35 }; +static const int gpio34_pins[] = { 36 }; +static const int gpio35_pins[] = { 37 }; +static const int gpio36_pins[] = { 38 }; +static const int gpio37_pins[] = { 39 }; +static const int gpio38_pins[] = { 40 }; +static const int gpio39_pins[] = { 41 }; +static const int gpio40_pins[] = { 42 }; +static const int gpio41_pins[] = { 43 }; +static const int gpio42_pins[] = { 44 }; +static const int gpio43_pins[] = { 45 }; +static const int gpio44_pins[] = { 46 }; +static const int gpio45_pins[] = { 47 }; +static const int gpio46_pins[] = { 48 }; +static const int gpio47_pins[] = { 49 }; +static const int gpio48_pins[] = { 50 }; +static const int gpio49_pins[] = { 51 }; +static const int gpio50_pins[] = { 52 }; +static const int gpio51_pins[] = { 53 }; +static const int gpio52_pins[] = { 54 }; +static const int pcie_reset0_pins[] = { 51 }; +static const int pcie_reset1_pins[] = { 52 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_alt", pon_alt), + PINCTRL_PIN_GROUP("olt", olt), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("mdio1", mdio1), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("gpio47", gpio47), + PINCTRL_PIN_GROUP("gpio48", gpio48), + PINCTRL_PIN_GROUP("gpio49", gpio49), + PINCTRL_PIN_GROUP("gpio50", gpio50), + PINCTRL_PIN_GROUP("gpio51", gpio51), + PINCTRL_PIN_GROUP("gpio52", gpio52), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +static const char *const pon_groups[] = { "pon", "pon_alt" }; +static const char *const olt_groups[] = { "olt" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", + "uart4", "uart5", "npu_uart" +}; +static const char *const i2c_groups[] = { "i2c0", "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1" +}; +static const char *const emmc_groups[] = { "emmc" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51" +}; +static const char *const phy1_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy2_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy3_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy4_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy1_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy2_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy3_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy4_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pon_alt", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, + GPIO_PON_ALT_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group olt_func_group[] = { + { + .name = "olt", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_OLT_MODE_MASK, + GPIO_OLT_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_SW_TOD_1PPS_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_SW_TOD_1PPS_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + MDC_0_GPIO_MODE_MASK | MDIO_0_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "npu_uart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + NPU_UART_EN_MASK, + NPU_UART_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + I2C0_SCL_GPIO_MODE_MASK | I2C0_SDA_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + I2C1_SCL_GPIO_MODE_MASK | I2C1_SDA_GPIO_MODE_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_MASK, + GPIO_PCM_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] = { + { + .name = "emmc", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, + I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, + I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, + I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, + I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, + SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, + SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, + SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, + SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, + MDC_0_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, + I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, + I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, + I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, + I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, + SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, + SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, + SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, + SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, + MDC_0_GPIO_MODE_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("olt", olt), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7581-chip-scu", + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-an7583", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); +MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC"); diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c new file mode 100644 index 000000000000..5aa39bacf460 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-en7523.c @@ -0,0 +1,1157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> + * Author: Markus Gothe <markus.gothe@genexis.eu> + * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com> + * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> + */ +#include "airoha-common.h" + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0210 +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0214 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x0218 +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0220 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) +#define NPU_UART_EN_MASK BIT(2) + +#define REG_FORCE_GPIO_EN 0x0224 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x0278 +#define REG_LAN_LED1_MAPPING 0x027c + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(13) +#define SPI_MOSI_E2_MASK BIT(12) +#define SPI_CLK_E2_MASK BIT(11) +#define SPI_CS0_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(13) +#define SPI_MOSI_E4_MASK BIT(12) +#define SPI_CLK_E4_MASK BIT(11) +#define SPI_CS0_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(13) +#define SPI_MOSI_PU_MASK BIT(12) +#define SPI_CLK_PU_MASK BIT(11) +#define SPI_CS0_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(13) +#define SPI_MOSI_PD_MASK BIT(12) +#define SPI_CLK_PD_MASK BIT(11) +#define SPI_CS0_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(2, "i2c_sda"), + PINCTRL_PIN(3, "i2c_scl"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(8, "uart1_txd"), + PINCTRL_PIN(9, "uart1_rxd"), + PINCTRL_PIN(12, "gpio0"), + PINCTRL_PIN(13, "gpio1"), + PINCTRL_PIN(14, "gpio2"), + PINCTRL_PIN(15, "gpio3"), + PINCTRL_PIN(16, "gpio4"), + PINCTRL_PIN(17, "gpio5"), + PINCTRL_PIN(18, "gpio6"), + PINCTRL_PIN(19, "gpio7"), + PINCTRL_PIN(20, "gpio8"), + PINCTRL_PIN(21, "gpio9"), + PINCTRL_PIN(22, "gpio10"), + PINCTRL_PIN(23, "gpio11"), + PINCTRL_PIN(24, "gpio12"), + PINCTRL_PIN(25, "gpio13"), + PINCTRL_PIN(26, "gpio14"), + PINCTRL_PIN(27, "gpio15"), + PINCTRL_PIN(28, "gpio16"), + PINCTRL_PIN(29, "gpio17"), + PINCTRL_PIN(30, "gpio18"), + PINCTRL_PIN(31, "gpio19"), + PINCTRL_PIN(32, "gpio20"), + PINCTRL_PIN(33, "gpio21"), + PINCTRL_PIN(34, "gpio22"), + PINCTRL_PIN(35, "gpio23"), + PINCTRL_PIN(36, "gpio24"), + PINCTRL_PIN(37, "gpio25"), + PINCTRL_PIN(38, "gpio26"), + PINCTRL_PIN(39, "gpio27"), + PINCTRL_PIN(40, "pcie_reset0"), + PINCTRL_PIN(41, "pcie_reset1"), +}; + +static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 }; +static const int pon_tod_1pps_pins[] = { 21 }; +static const int gsw_tod_1pps_pins[] = { 21 }; +static const int sipo_pins[] = { 13, 38 }; +static const int sipo_rclk_pins[] = { 13, 30, 38 }; +static const int mdio_pins[] = { 20, 21 }; +static const int uart2_pins[] = { 20, 21 }; +static const int npu_uart_pins[] = { 13, 38 }; +static const int i2c0_pins[] = { 2, 3 }; +static const int i2c1_pins[] = { 14, 15 }; +static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 }; +static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 }; +static const int i2s_pins[] = { 16, 17, 18, 19 }; +static const int pcm1_pins[] = { 24, 25, 26, 27 }; +static const int pcm2_pins[] = { 16, 17, 18, 19 }; +static const int spi_pins[] = { 4, 5, 6, 7 }; +static const int spi_quad_pins[] = { 14, 15 }; +static const int spi_cs1_pins[] = { 21 }; +static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 }; +static const int pcm_spi_int_pins[] = { 15 }; +static const int pcm_spi_rst_pins[] = { 14 }; +static const int pcm_spi_cs1_pins[] = { 22 }; +static const int pcm_spi_cs2_p128_pins[] = { 39 }; +static const int pcm_spi_cs2_p156_pins[] = { 39 }; +static const int pcm_spi_cs3_pins[] = { 20 }; +static const int pcm_spi_cs4_pins[] = { 23 }; +static const int gpio0_pins[] = { 12 }; +static const int gpio1_pins[] = { 13 }; +static const int gpio2_pins[] = { 14 }; +static const int gpio3_pins[] = { 15 }; +static const int gpio4_pins[] = { 16 }; +static const int gpio5_pins[] = { 17 }; +static const int gpio6_pins[] = { 18 }; +static const int gpio7_pins[] = { 19 }; +static const int gpio8_pins[] = { 20 }; +static const int gpio9_pins[] = { 21 }; +static const int gpio10_pins[] = { 22 }; +static const int gpio11_pins[] = { 23 }; +static const int gpio12_pins[] = { 24 }; +static const int gpio13_pins[] = { 25 }; +static const int gpio14_pins[] = { 26 }; +static const int gpio15_pins[] = { 27 }; +static const int gpio16_pins[] = { 28 }; +static const int gpio17_pins[] = { 29 }; +static const int gpio18_pins[] = { 30 }; +static const int gpio19_pins[] = { 31 }; +static const int gpio20_pins[] = { 32 }; +static const int gpio21_pins[] = { 33 }; +static const int gpio22_pins[] = { 34 }; +static const int gpio23_pins[] = { 35 }; +static const int gpio24_pins[] = { 36 }; +static const int gpio25_pins[] = { 37 }; +static const int gpio26_pins[] = { 38 }; +static const int gpio27_pins[] = { 39 }; +static const int gpio28_pins[] = { 40 }; +static const int gpio29_pins[] = { 41 }; +static const int pcie_reset0_pins[] = { 40 }; +static const int pcie_reset1_pins[] = { 41 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { "uart2", "npu_uart" }; +static const char *const i2c_groups[] = { "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4" +}; +static const char *const i2s_groups[] = { "i2s" }; +static const char *const gpio_groups[] = { "gpio28", "gpio29" }; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29" +}; +static const char *const phy1_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy2_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy3_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy4_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy1_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy2_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy3_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy4_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "npu_uart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + NPU_UART_EN_MASK, + NPU_UART_EN_MASK + }, + .regmap_size = 1, + } +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p128", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p156", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] = { + { + .name = "i2s", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(8, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(9, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(40, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .chip_scu_compatible = "airoha,en7523-chip-scu", + .pinctrl_name = KBUILD_MODNAME, + .pinctrl_owner = THIS_MODULE, + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + }, +}; + +static const struct of_device_id airoha_pinctrl_of_match[] = { + { .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); + +static struct platform_driver airoha_pinctrl_driver = { + .probe = airoha_pinctrl_probe, + .driver = { + .name = "pinctrl-airoha-en7523", + .of_match_table = airoha_pinctrl_of_match, + }, +}; +module_platform_driver(airoha_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); +MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); +MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); +MODULE_AUTHOR("Matheus Sampaio Queiroga <srherobrine20@gmail.com>"); +MODULE_AUTHOR("Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>"); +MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC"); diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 1a4e5b9ed471..8e1d4da0891d 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -31,3 +31,26 @@ config PINCTRL_ASPEED_G6 help Say Y here to enable pin controller support for Aspeed's 6th generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G7_SOC0 + bool "Aspeed G7 SoC pin control" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for the SoC0 instance + of Aspeed's 7th generation SoCs. GPIO is provided by a separate + GPIO driver. + +config PINCTRL_ASPEED_G7_SOC1 + bool "Aspeed G7 SoC1 pin control" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select MFD_SYSCON + select PINMUX + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to enable pin controller support for the SoC1 instance + of Aspeed's 7th generation SoCs. GPIO is provided by a separate + GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile index db2a7600ae2b..7a41ca45c6ba 100644 --- a/drivers/pinctrl/aspeed/Makefile +++ b/drivers/pinctrl/aspeed/Makefile @@ -6,3 +6,5 @@ obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o +obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC0) += pinctrl-aspeed-g7-soc0.o +obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC1) += pinctrl-aspeed-g7-soc1.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index f9d8fb1ab1ec..6c218ce3396d 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -6,7 +6,6 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 50979787db5c..b0cba0f3e17e 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -7,7 +7,6 @@ #include <linux/io.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 8cf61aab81b1..85d6640ff4c4 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -4,7 +4,6 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c new file mode 100644 index 000000000000..94f216f55bdd --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c @@ -0,0 +1,749 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <linux/bitops.h> +#include <linux/bits.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "pinctrl-aspeed.h" +#include "pinmux-aspeed.h" +#include "../pinctrl-utils.h" + +#define SCU200 0x200 /* System Reset Control #1 */ + +#define SCU010 0x010 /* Hardware Strap Register */ +#define SCU400 0x400 /* Multi-function Pin Control #1 */ +#define SCU404 0x404 /* Multi-function Pin Control #2 */ +#define SCU408 0x408 /* Multi-function Pin Control #3 */ +#define SCU40C 0x40C /* Multi-function Pin Control #3 */ +#define SCU410 0x410 /* USB Multi-function Control Register */ +#define SCU414 0x414 /* VGA Function Control Register */ + +#define SCU480 0x480 /* GPIO18A0 IO Control Register */ +#define SCU484 0x484 /* GPIO18A1 IO Control Register */ +#define SCU488 0x488 /* GPIO18A2 IO Control Register */ +#define SCU48C 0x48c /* GPIO18A3 IO Control Register */ +#define SCU490 0x490 /* GPIO18A4 IO Control Register */ +#define SCU494 0x494 /* GPIO18A5 IO Control Register */ +#define SCU498 0x498 /* GPIO18A6 IO Control Register */ +#define SCU49C 0x49c /* GPIO18A7 IO Control Register */ +#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */ +#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */ +#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */ +#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */ + +enum { + AC14, + AE15, + AD14, + AE14, + AF14, + AB13, + AB14, + AF15, + AF13, + AC13, + AD13, + AE13, + JTAG_PORT, + PCIERC0_PERST, + PCIERC1_PERST, + PORTA_MODE, + PORTA_U2, + PORTB_MODE, + PORTB_U2, + PORTA_U2_PHY, + PORTB_U2_PHY, + PORTA_U3, + PORTB_U3, + PORTA_U3_PHY, + PORTB_U3_PHY, +}; + +SIG_EXPR_LIST_DECL_SEMG(AC14, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 0)); +SIG_EXPR_LIST_DECL_SEMG(AC14, VB1CS, VB1, VB, SIG_DESC_SET(SCU404, 0)); +PIN_DECL_2(AC14, GPIO18A0, EMMCCLK, VB1CS); + +SIG_EXPR_LIST_DECL_SEMG(AE15, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 1)); +SIG_EXPR_LIST_DECL_SEMG(AE15, VB1CK, VB1, VB, SIG_DESC_SET(SCU404, 1)); +PIN_DECL_2(AE15, GPIO18A1, EMMCCMD, VB1CK); + +SIG_EXPR_LIST_DECL_SEMG(AD14, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 2)); +SIG_EXPR_LIST_DECL_SEMG(AD14, VB1MOSI, VB1, VB, SIG_DESC_SET(SCU404, 2)); +PIN_DECL_2(AD14, GPIO18A2, EMMCDAT0, VB1MOSI); + +SIG_EXPR_LIST_DECL_SEMG(AE14, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 3)); +SIG_EXPR_LIST_DECL_SEMG(AE14, VB1MISO, VB1, VB, SIG_DESC_SET(SCU404, 3)); +PIN_DECL_2(AE14, GPIO18A3, EMMCDAT1, VB1MISO); + +SIG_EXPR_LIST_DECL_SEMG(AF14, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 4)); +PIN_DECL_1(AF14, GPIO18A4, EMMCDAT2); + +SIG_EXPR_LIST_DECL_SEMG(AB13, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 5)); +PIN_DECL_1(AB13, GPIO18A5, EMMCDAT3); + +SIG_EXPR_LIST_DECL_SEMG(AB14, EMMCCDN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 6)); +SIG_EXPR_LIST_DECL_SEMG(AB14, VB0CS, VB0, VB, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_2(AB14, GPIO18A6, EMMCCDN, VB0CS); + +SIG_EXPR_LIST_DECL_SEMG(AF15, EMMCWPN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 7)); +SIG_EXPR_LIST_DECL_SEMG(AF15, VB0CK, VB0, VB, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_2(AF15, GPIO18A7, EMMCWPN, VB0CK); + +SIG_EXPR_LIST_DECL_SESG(AF13, TSPRSTN, TSPRSTN, SIG_DESC_SET(SCU010, 9)); +SIG_EXPR_LIST_DECL_SEMG(AF13, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 8)); +SIG_EXPR_LIST_DECL_SEMG(AF13, VB0MOSI, VB0, VB, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_3(AF13, GPIO18B0, TSPRSTN, EMMCDAT4, VB0MOSI); + +SIG_EXPR_LIST_DECL_SESG(AC13, UFSCLKI, UFSCLKI, SIG_DESC_SET(SCU010, 19)); +SIG_EXPR_LIST_DECL_SEMG(AC13, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 9)); +SIG_EXPR_LIST_DECL_SEMG(AC13, VB0MISO, VB0, VB, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_3(AC13, GPIO18B1, UFSCLKI, EMMCDAT5, VB0MISO); + +SIG_EXPR_LIST_DECL_SEMG(AD13, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 10)); +SIG_EXPR_LIST_DECL_SESG(AD13, DDCCLK, VGADDC, SIG_DESC_SET(SCU404, 10)); +PIN_DECL_2(AD13, GPIO18B2, EMMCDAT6, DDCCLK); + +SIG_EXPR_LIST_DECL_SEMG(AE13, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 11)); +SIG_EXPR_LIST_DECL_SESG(AE13, DDCDAT, VGADDC, SIG_DESC_SET(SCU404, 11)); +PIN_DECL_2(AE13, GPIO18B3, EMMCDAT7, DDCDAT); + +GROUP_DECL(EMMCG1, AC14, AE15, AD14); +GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13); +GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, AE13); +GROUP_DECL(EMMCWPN, AF15); +GROUP_DECL(EMMCCDN, AB14); +FUNC_DECL_(EMMC, "EMMCG1", "EMMCG4", "EMMCG8", "EMMCWPN", "EMMCCDN"); + +GROUP_DECL(VB1, AC14, AE15, AD14, AE14); +GROUP_DECL(VB0, AF15, AB14, AF13, AC13); +FUNC_DECL_2(VB, VB1, VB0); + +FUNC_GROUP_DECL(TSPRSTN, AF13); + +FUNC_GROUP_DECL(UFSCLKI, AC13); + +FUNC_GROUP_DECL(VGADDC, AD13, AE13); + +/* JTAG Port Selection */ +#define JTAG_PORT_PSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x0, 0 } +#define JTAG_PORT_SSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x41, 0 } +#define JTAG_PORT_TSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x42, 0 } +#define JTAG_PORT_DDR_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x43, 0 } +#define JTAG_PORT_USB3A_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x44, 0 } +#define JTAG_PORT_USB3B_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x45, 0 } +#define JTAG_PORT_PCIEA_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x46, 0 } +#define JTAG_PORT_PCIEB_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x47, 0 } +#define JTAG_PORT_JTAGM0_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x8, 0 } + +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPSP, JTAG0, JTAGPSP, JTAG_PORT_PSP_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGSSP, JTAG0, JTAGSSP, JTAG_PORT_SSP_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGTSP, JTAG0, JTAGTSP, JTAG_PORT_TSP_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGDDR, JTAG0, JTAGDDR, JTAG_PORT_DDR_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3A, JTAG0, JTAGUSB3A, JTAG_PORT_USB3A_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3B, JTAG0, JTAGUSB3B, JTAG_PORT_USB3B_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEA, JTAG0, JTAGPCIEA, JTAG_PORT_PCIEA_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEB, JTAG0, JTAGPCIEB, JTAG_PORT_PCIEB_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGM0, JTAG0, JTAGM0, JTAG_PORT_JTAGM0_DESC); +PIN_DECL_(JTAG_PORT, SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGSSP), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGTSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGDDR), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3A), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3B), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEA), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEB), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGM0)); + +GROUP_DECL(JTAG0, JTAG_PORT); + +FUNC_DECL_1(JTAGPSP, JTAG0); +FUNC_DECL_1(JTAGSSP, JTAG0); +FUNC_DECL_1(JTAGTSP, JTAG0); +FUNC_DECL_1(JTAGDDR, JTAG0); +FUNC_DECL_1(JTAGUSB3A, JTAG0); +FUNC_DECL_1(JTAGUSB3B, JTAG0); +FUNC_DECL_1(JTAGPCIEA, JTAG0); +FUNC_DECL_1(JTAGPCIEB, JTAG0); +FUNC_DECL_1(JTAGM0, JTAG0); + +/* PCIe Reset Control */ +SIG_EXPR_LIST_DECL_SESG(PCIERC0_PERST, PCIERC0PERST, PCIERC0PERST, SIG_DESC_SET(SCU200, 21)); +PIN_DECL_(PCIERC0_PERST, SIG_EXPR_LIST_PTR(PCIERC0_PERST, PCIERC0PERST)); +FUNC_GROUP_DECL(PCIERC0PERST, PCIERC0_PERST); + +SIG_EXPR_LIST_DECL_SESG(PCIERC1_PERST, PCIERC1PERST, PCIERC1PERST, SIG_DESC_SET(SCU200, 19)); +PIN_DECL_(PCIERC1_PERST, SIG_EXPR_LIST_PTR(PCIERC1_PERST, PCIERC1PERST)); +FUNC_GROUP_DECL(PCIERC1PERST, PCIERC1_PERST); + +#define PORTA_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 0, 0 } +#define PORTA_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 1, 0 } +#define PORTA_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 2, 0 } +#define PORTA_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHPD0, USB2AH, USB2AHPD0, PORTA_MODE_HPD0_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AH, USB2AHAP, USB2AH, PORTA_MODE_H_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHP, USB2AHAP, USB2AHP, PORTA_MODE_HP_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AD0, USB2AHAP, USB2AD0, PORTA_MODE_D0_DESC); +PIN_DECL_(PORTA_MODE, SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHPD0), + SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AH), SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHP), + SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AD0)); + +#define PORTA_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 0, 0 } +#define PORTA_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 1, 0 } +#define PORTA_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 2, 0 } +#define PORTA_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHD1, USB2A, USB2AXHD1, PORTA_U2_XHD_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHPD1, USB2A, USB2AXHPD1, PORTA_U2_XHD_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH, USB2AAP, USB2AXH, PORTA_U2_XH_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP, USB2AAP, USB2AXHP, PORTA_U2_XH_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH2B, USB2ABP, USB2AXH2B, PORTA_U2_XH2E_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP2B, USB2ABP, USB2AXHP2B, PORTA_U2_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AD1, USB2ADAP, USB2AD1, PORTA_U2_D1_DESC); +PIN_DECL_(PORTA_U2, SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHD1), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHPD1), + SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP), + SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH2B), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP2B), + SIG_EXPR_LIST_PTR(PORTA_U2, USB2AD1)); + +#define PORTB_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 0, 0 } +#define PORTB_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 1, 0 } +#define PORTB_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 2, 0 } +#define PORTB_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHPD0, USB2BH, USB2BHPD0, PORTB_MODE_HPD0_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BH, USB2BHBP, USB2BH, PORTB_MODE_H_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHP, USB2BHBP, USB2BHP, PORTB_MODE_HP_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BD0, USB2BHBP, USB2BD0, PORTB_MODE_D0_DESC); +PIN_DECL_(PORTB_MODE, SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHPD0), + SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BH), SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHP), + SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BD0)); + +#define PORTB_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 0, 0 } +#define PORTB_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 1, 0 } +#define PORTB_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 2, 0 } +#define PORTB_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHD1, USB2B, USB2BXHD1, PORTB_U2_XHD_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHPD1, USB2B, USB2BXHPD1, PORTB_U2_XHD_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH, USB2BBP, USB2BXH, PORTB_U2_XH_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP, USB2BBP, USB2BXHP, PORTB_U2_XH_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH2A, USB2BAP, USB2BXH2A, PORTB_U2_XH2E_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP2A, USB2BAP, USB2BXHP2A, PORTB_U2_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BD1, USB2BDBP, USB2BD1, PORTB_U2_D1_DESC); +PIN_DECL_(PORTB_U2, SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHD1), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHPD1), + SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP), + SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH2A), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP2A), + SIG_EXPR_LIST_PTR(PORTB_U2, USB2BD1)); +/* + * USB2 virtual PHY pins. + * + * PORTA_U2_PHY and PORTB_U2_PHY are logical endpoints, not package pins. + * They alias existing USB2 expressions so pin groups can model direct and + * cross-coupled routing for host and mode paths. + * + * - USB2AAP/USB2ADAP/USB2AHAP: use PORTA_U2_PHY + * - USB2ABP : use PORTB_U2_PHY + * - USB2BBP/USB2BDBP/USB2BHBP: use PORTB_U2_PHY + * - USB2BAP : use PORTA_U2_PHY + * + * They do not have any registers to configure this behaviour; the goal is + * simply for the driver to prevent conflicting selections. For example, + * selecting group USB2ABP and USB2BBP at the same time should not be + * allowed. + */ +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXH, USB2AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXHP, USB2AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXH2A, USB2BAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXHP2A, USB2BAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD1, USB2ADAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AH, USB2AHAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AHP, USB2AHAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD0, USB2AHAP); +PIN_DECL_(PORTA_U2_PHY, SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXH), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXHP), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXH2A), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXHP2A), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD1), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AH), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AHP), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD0)); + +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXH2B, USB2ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXHP2B, USB2ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXH, USB2BBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXHP, USB2BBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD1, USB2BDBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BH, USB2BHBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BHP, USB2BHBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD0, USB2BHBP); +PIN_DECL_(PORTB_U2_PHY, SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXH2B), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXH), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXHP), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD1), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BH), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BHP), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD0)); + +GROUP_DECL(USB2A, PORTA_U2); +GROUP_DECL(USB2AAP, PORTA_U2, PORTA_U2_PHY); +GROUP_DECL(USB2ABP, PORTA_U2, PORTB_U2_PHY); +GROUP_DECL(USB2ADAP, PORTA_U2, PORTA_U2_PHY); +GROUP_DECL(USB2AH, PORTA_MODE); +GROUP_DECL(USB2AHAP, PORTA_MODE, PORTA_U2_PHY); + +FUNC_DECL_1(USB2AXHD1, USB2A); +FUNC_DECL_1(USB2AXHPD1, USB2A); +FUNC_DECL_1(USB2AXH, USB2AAP); +FUNC_DECL_1(USB2AXHP, USB2AAP); +FUNC_DECL_1(USB2AXH2B, USB2ABP); +FUNC_DECL_1(USB2AXHP2B, USB2ABP); +FUNC_DECL_1(USB2AD1, USB2ADAP); +FUNC_DECL_1(USB2AHPD0, USB2AH); +FUNC_DECL_1(USB2AH, USB2AHAP); +FUNC_DECL_1(USB2AHP, USB2AHAP); +FUNC_DECL_1(USB2AD0, USB2AHAP); + +GROUP_DECL(USB2B, PORTB_U2); +GROUP_DECL(USB2BBP, PORTB_U2, PORTB_U2_PHY); +GROUP_DECL(USB2BAP, PORTB_U2, PORTA_U2_PHY); +GROUP_DECL(USB2BDBP, PORTB_U2, PORTB_U2_PHY); +GROUP_DECL(USB2BH, PORTB_MODE); +GROUP_DECL(USB2BHBP, PORTB_MODE, PORTB_U2_PHY); + +FUNC_DECL_1(USB2BXHD1, USB2B); +FUNC_DECL_1(USB2BXHPD1, USB2B); +FUNC_DECL_1(USB2BXH, USB2BBP); +FUNC_DECL_1(USB2BXHP, USB2BBP); +FUNC_DECL_1(USB2BXH2A, USB2BAP); +FUNC_DECL_1(USB2BXHP2A, USB2BAP); +FUNC_DECL_1(USB2BD1, USB2BDBP); +FUNC_DECL_1(USB2BHPD0, USB2BH); +FUNC_DECL_1(USB2BH, USB2BHBP); +FUNC_DECL_1(USB2BHP, USB2BHBP); +FUNC_DECL_1(USB2BD0, USB2BHBP); + +#define PORTA_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 0, 0 } +#define PORTA_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 2, 0 } +#define PORTA_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHD, USB3A, USB3AXHD, PORTA_U3_XHD_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHPD, USB3A, USB3AXHPD, PORTA_U3_XHD_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH, USB3AAP, USB3AXH, PORTA_U3_XH_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP, USB3AAP, USB3AXHP, PORTA_U3_XH_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH2B, USB3ABP, USB3AXH2B, PORTA_U3_XH2E_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP2B, USB3ABP, USB3AXHP2B, PORTA_U3_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +PIN_DECL_(PORTA_U3, SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHD), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHPD), + SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP), + SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH2B), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP2B)); + +#define PORTB_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 0, 0 } +#define PORTB_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 2, 0 } +#define PORTB_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHD, USB3B, USB3BXHD, PORTB_U3_XHD_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHPD, USB3B, USB3BXHPD, PORTB_U3_XHD_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH, USB3BBP, USB3BXH, PORTB_U3_XH_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP, USB3BBP, USB3BXHP, PORTB_U3_XH_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH2A, USB3BAP, USB3BXH2A, PORTB_U3_XH2E_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP2A, USB3BAP, USB3BXHP2A, PORTB_U3_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +PIN_DECL_(PORTB_U3, SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHD), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHPD), + SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP), + SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH2A), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP2A)); + +/* + * USB3 virtual PHY pins. + * + * PORTA_U3_PHY and PORTB_U3_PHY are logical endpoints, not package pins. + * They alias existing USB3 expressions so pin groups can model both direct and + * cross-coupled routing to PHY A/B. + * + * - USB3AAP: PORTA_U3 + PORTA_U3_PHY (A -> PHY A) + * - USB3ABP: PORTA_U3 + PORTB_U3_PHY (A -> PHY B) + * - USB3BBP: PORTB_U3 + PORTB_U3_PHY (B -> PHY B) + * - USB3BAP: PORTB_U3 + PORTA_U3_PHY (B -> PHY A) + * + * They do not have any registers to configure this behavior; the goal is + * simply for the driver to prevent conflicting selections. For example, + * selecting group USB3ABP and USB3BBP at the same time should not be + * allowed. + */ +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXH, USB3AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXHP, USB3AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXH2A, USB3BAP); +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXHP2A, USB3BAP); +PIN_DECL_(PORTA_U3_PHY, SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXH), + SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXHP), SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXH2A), + SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXHP2A)); + +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXH2B, USB3ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXHP2B, USB3ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXH, USB3BBP); +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXHP, USB3BBP); +PIN_DECL_(PORTB_U3_PHY, SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXH2B), + SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXH), + SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXHP)); + +/* USB3A xHCI to vHUB */ +GROUP_DECL(USB3A, PORTA_U3); +/* USB3A xHCI to USB3A PHY */ +GROUP_DECL(USB3AAP, PORTA_U3, PORTA_U3_PHY); +/* USB3A xHCI to USB3B PHY */ +GROUP_DECL(USB3ABP, PORTA_U3, PORTB_U3_PHY); + +FUNC_DECL_1(USB3AXHD, USB3A); +FUNC_DECL_1(USB3AXHPD, USB3A); +FUNC_DECL_1(USB3AXH, USB3AAP); +FUNC_DECL_1(USB3AXHP, USB3AAP); +FUNC_DECL_1(USB3AXH2B, USB3ABP); +FUNC_DECL_1(USB3AXHP2B, USB3ABP); + +/* USB3B xHCI to vHUB */ +GROUP_DECL(USB3B, PORTB_U3); +/* USB3B xHCI to USB3A PHY */ +GROUP_DECL(USB3BAP, PORTB_U3, PORTA_U3_PHY); +/* USB3B xHCI to USB3B PHY */ +GROUP_DECL(USB3BBP, PORTB_U3, PORTB_U3_PHY); + +FUNC_DECL_1(USB3BXHD, USB3B); +FUNC_DECL_1(USB3BXHPD, USB3B); +FUNC_DECL_1(USB3BXH, USB3BBP); +FUNC_DECL_1(USB3BXHP, USB3BBP); +FUNC_DECL_1(USB3BXH2A, USB3BAP); +FUNC_DECL_1(USB3BXHP2A, USB3BAP); + +static const struct pinctrl_pin_desc aspeed_g7_soc0_pins[] = { + ASPEED_PINCTRL_PIN(AC14), + ASPEED_PINCTRL_PIN(AE15), + ASPEED_PINCTRL_PIN(AD14), + ASPEED_PINCTRL_PIN(AE14), + ASPEED_PINCTRL_PIN(AF14), + ASPEED_PINCTRL_PIN(AB13), + ASPEED_PINCTRL_PIN(AB14), + ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF13), + ASPEED_PINCTRL_PIN(AC13), + ASPEED_PINCTRL_PIN(AD13), + ASPEED_PINCTRL_PIN(AE13), + ASPEED_PINCTRL_PIN(JTAG_PORT), + ASPEED_PINCTRL_PIN(PCIERC0_PERST), + ASPEED_PINCTRL_PIN(PCIERC1_PERST), + ASPEED_PINCTRL_PIN(PORTA_MODE), + ASPEED_PINCTRL_PIN(PORTA_U2), + ASPEED_PINCTRL_PIN(PORTA_U3), + ASPEED_PINCTRL_PIN(PORTA_U2_PHY), + ASPEED_PINCTRL_PIN(PORTA_U3_PHY), + ASPEED_PINCTRL_PIN(PORTB_MODE), + ASPEED_PINCTRL_PIN(PORTB_U2), + ASPEED_PINCTRL_PIN(PORTB_U3), + ASPEED_PINCTRL_PIN(PORTB_U2_PHY), + ASPEED_PINCTRL_PIN(PORTB_U3_PHY), +}; + +static const struct aspeed_pin_group aspeed_g7_soc0_groups[] = { + ASPEED_PINCTRL_GROUP(EMMCCDN), + ASPEED_PINCTRL_GROUP(EMMCG1), + ASPEED_PINCTRL_GROUP(EMMCG4), + ASPEED_PINCTRL_GROUP(EMMCG8), + ASPEED_PINCTRL_GROUP(EMMCWPN), + ASPEED_PINCTRL_GROUP(TSPRSTN), + ASPEED_PINCTRL_GROUP(UFSCLKI), + ASPEED_PINCTRL_GROUP(VB0), + ASPEED_PINCTRL_GROUP(VB1), + ASPEED_PINCTRL_GROUP(VGADDC), + /* JTAG groups */ + ASPEED_PINCTRL_GROUP(JTAG0), + /* PCIE RC groups */ + ASPEED_PINCTRL_GROUP(PCIERC0PERST), + ASPEED_PINCTRL_GROUP(PCIERC1PERST), + /* USB3A groups */ + ASPEED_PINCTRL_GROUP(USB3A), + ASPEED_PINCTRL_GROUP(USB3AAP), + ASPEED_PINCTRL_GROUP(USB3ABP), + /* USB3B groups */ + ASPEED_PINCTRL_GROUP(USB3B), + ASPEED_PINCTRL_GROUP(USB3BAP), + ASPEED_PINCTRL_GROUP(USB3BBP), + /* USB2A groups */ + ASPEED_PINCTRL_GROUP(USB2A), + ASPEED_PINCTRL_GROUP(USB2AAP), + ASPEED_PINCTRL_GROUP(USB2ABP), + ASPEED_PINCTRL_GROUP(USB2ADAP), + ASPEED_PINCTRL_GROUP(USB2AH), + ASPEED_PINCTRL_GROUP(USB2AHAP), + /* USB2B groups */ + ASPEED_PINCTRL_GROUP(USB2B), + ASPEED_PINCTRL_GROUP(USB2BAP), + ASPEED_PINCTRL_GROUP(USB2BBP), + ASPEED_PINCTRL_GROUP(USB2BDBP), + ASPEED_PINCTRL_GROUP(USB2BH), + ASPEED_PINCTRL_GROUP(USB2BHBP), +}; + +static const struct aspeed_pin_function aspeed_g7_soc0_functions[] = { + ASPEED_PINCTRL_FUNC(EMMC), + ASPEED_PINCTRL_FUNC(TSPRSTN), + ASPEED_PINCTRL_FUNC(UFSCLKI), + ASPEED_PINCTRL_FUNC(VB), + ASPEED_PINCTRL_FUNC(VGADDC), + /* JTAG functions */ + ASPEED_PINCTRL_FUNC(JTAGDDR), + ASPEED_PINCTRL_FUNC(JTAGM0), + ASPEED_PINCTRL_FUNC(JTAGPCIEA), + ASPEED_PINCTRL_FUNC(JTAGPCIEB), + ASPEED_PINCTRL_FUNC(JTAGPSP), + ASPEED_PINCTRL_FUNC(JTAGSSP), + ASPEED_PINCTRL_FUNC(JTAGTSP), + ASPEED_PINCTRL_FUNC(JTAGUSB3A), + ASPEED_PINCTRL_FUNC(JTAGUSB3B), + /* PCIE RC functions */ + ASPEED_PINCTRL_FUNC(PCIERC0PERST), + ASPEED_PINCTRL_FUNC(PCIERC1PERST), + /* USB3A functions */ + ASPEED_PINCTRL_FUNC(USB3AXH), + ASPEED_PINCTRL_FUNC(USB3AXH2B), + ASPEED_PINCTRL_FUNC(USB3AXHD), + ASPEED_PINCTRL_FUNC(USB3AXHP), + ASPEED_PINCTRL_FUNC(USB3AXHP2B), + ASPEED_PINCTRL_FUNC(USB3AXHPD), + /* USB3B functions */ + ASPEED_PINCTRL_FUNC(USB3BXH), + ASPEED_PINCTRL_FUNC(USB3BXH2A), + ASPEED_PINCTRL_FUNC(USB3BXHD), + ASPEED_PINCTRL_FUNC(USB3BXHP), + ASPEED_PINCTRL_FUNC(USB3BXHP2A), + ASPEED_PINCTRL_FUNC(USB3BXHPD), + /* USB2A functions */ + ASPEED_PINCTRL_FUNC(USB2AD0), + ASPEED_PINCTRL_FUNC(USB2AD1), + ASPEED_PINCTRL_FUNC(USB2AH), + ASPEED_PINCTRL_FUNC(USB2AHP), + ASPEED_PINCTRL_FUNC(USB2AHPD0), + ASPEED_PINCTRL_FUNC(USB2AXH), + ASPEED_PINCTRL_FUNC(USB2AXH2B), + ASPEED_PINCTRL_FUNC(USB2AXHD1), + ASPEED_PINCTRL_FUNC(USB2AXHP), + ASPEED_PINCTRL_FUNC(USB2AXHP2B), + ASPEED_PINCTRL_FUNC(USB2AXHPD1), + /* USB2B functions */ + ASPEED_PINCTRL_FUNC(USB2BD0), + ASPEED_PINCTRL_FUNC(USB2BD1), + ASPEED_PINCTRL_FUNC(USB2BH), + ASPEED_PINCTRL_FUNC(USB2BHP), + ASPEED_PINCTRL_FUNC(USB2BHPD0), + ASPEED_PINCTRL_FUNC(USB2BXH), + ASPEED_PINCTRL_FUNC(USB2BXH2A), + ASPEED_PINCTRL_FUNC(USB2BXHD1), + ASPEED_PINCTRL_FUNC(USB2BXHP), + ASPEED_PINCTRL_FUNC(USB2BXHP2A), + ASPEED_PINCTRL_FUNC(USB2BXHPD1), +}; + +static const struct pinmux_ops aspeed_g7_soc0_pinmux_ops = { + .get_functions_count = aspeed_pinmux_get_fn_count, + .get_function_name = aspeed_pinmux_get_fn_name, + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, + .strict = true, +}; + +static const struct pinctrl_ops aspeed_g7_soc0_pinctrl_ops = { + .get_groups_count = aspeed_pinctrl_get_groups_count, + .get_group_name = aspeed_pinctrl_get_group_name, + .get_group_pins = aspeed_pinctrl_get_group_pins, + .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +static const struct pinconf_ops aspeed_g7_soc0_pinconf_ops = { + .is_generic = true, + .pin_config_get = aspeed_pin_config_get, + .pin_config_set = aspeed_pin_config_set, + .pin_config_group_get = aspeed_pin_config_group_get, + .pin_config_group_set = aspeed_pin_config_group_set, +}; + +/* pinctrl_desc */ +static const struct pinctrl_desc aspeed_g7_soc0_pinctrl_desc = { + .name = "aspeed-g7-soc0-pinctrl", + .pins = aspeed_g7_soc0_pins, + .npins = ARRAY_SIZE(aspeed_g7_soc0_pins), + .pctlops = &aspeed_g7_soc0_pinctrl_ops, + .pmxops = &aspeed_g7_soc0_pinmux_ops, + .confops = &aspeed_g7_soc0_pinconf_ops, +}; + +static const struct aspeed_pin_config aspeed_g7_soc0_configs[] = { + /* GPIO18A */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC14, AC14 }, SCU480, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AC14, AC14 }, SCU480, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AC14, AC14 }, SCU480, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AC14, AC14 }, SCU480, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AE15, AE15 }, SCU484, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AE15, AE15 }, SCU484, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AE15, AE15 }, SCU484, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AE15, AE15 }, SCU484, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AD14, AD14 }, SCU488, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AD14, AD14 }, SCU488, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AD14, AD14 }, SCU488, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AD14, AD14 }, SCU488, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AE14, AE14 }, SCU48C, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AE14, AE14 }, SCU48C, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AE14, AE14 }, SCU48C, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AE14, AE14 }, SCU48C, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AF14, AF14 }, SCU490, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AF14, AF14 }, SCU490, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AF14, AF14 }, SCU490, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AF14, AF14 }, SCU490, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AB13, AB13 }, SCU494, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AB13, AB13 }, SCU494, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AB13, AB13 }, SCU494, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AB13, AB13 }, SCU494, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AB14, AB14 }, SCU498, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AB14, AB14 }, SCU498, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AB14, AB14 }, SCU498, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AB14, AB14 }, SCU498, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AF15, AF15 }, SCU49C, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AF15, AF15 }, SCU49C, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AF15, AF15 }, SCU49C, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AF15, AF15 }, SCU49C, BIT(5) }, + /* GPIO18B */ + { PIN_CONFIG_DRIVE_STRENGTH, { AF13, AF13 }, SCU4A0, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AF13, AF13 }, SCU4A0, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AC13, AC13 }, SCU4A4, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AC13, AC13 }, SCU4A4, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AD13, AD13 }, SCU4A8, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AD13, AD13 }, SCU4A8, BIT(5) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AE13, AE13 }, SCU4AC, GENMASK(3, 0) }, + { PIN_CONFIG_BIAS_PULL_DOWN, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_PULL_UP, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) }, + { PIN_CONFIG_BIAS_DISABLE, { AE13, AE13 }, SCU4AC, BIT(5) }, +}; + +static const struct aspeed_pin_config_map aspeed_g7_soc0_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 2, GENMASK(1, 0) }, + { PIN_CONFIG_BIAS_PULL_UP, -1, 3, GENMASK(1, 0) }, + { PIN_CONFIG_BIAS_DISABLE, -1, 0, BIT_MASK(0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 3, 0, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 6, 1, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 2, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 11, 3, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 4, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 18, 5, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 20, 6, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 23, 7, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 30, 8, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 32, 9, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 33, 10, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 35, 11, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 37, 12, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 38, 13, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 39, 14, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 41, 15, GENMASK(3, 0) }, + +}; + +static int aspeed_g7_soc0_sig_expr_set(struct aspeed_pinmux_data *ctx, + const struct aspeed_sig_expr *expr, bool enable) +{ + int ret; + int i; + + for (i = 0; i < expr->ndescs; i++) { + const struct aspeed_sig_desc *desc = &expr->descs[i]; + u32 pattern = enable ? desc->enable : desc->disable; + u32 val = (pattern << __ffs(desc->mask)); + + if (!ctx->maps[desc->ip]) + return -ENODEV; + + WARN_ON_ONCE(desc->ip != ASPEED_IP_SCU); + + ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, + desc->mask, val); + if (ret) + return ret; + } + + ret = aspeed_sig_expr_eval(ctx, expr, enable); + if (ret < 0) + return ret; + + return ret ? 0 : -EPERM; +} + +static const struct aspeed_pinmux_ops aspeed_g7_soc0_ops = { + .set = aspeed_g7_soc0_sig_expr_set, +}; + +static struct aspeed_pinctrl_data aspeed_g7_soc0_pinctrl_data = { + .pins = aspeed_g7_soc0_pins, + .npins = ARRAY_SIZE(aspeed_g7_soc0_pins), + .pinmux = { + .ops = &aspeed_g7_soc0_ops, + .groups = aspeed_g7_soc0_groups, + .ngroups = ARRAY_SIZE(aspeed_g7_soc0_groups), + .functions = aspeed_g7_soc0_functions, + .nfunctions = ARRAY_SIZE(aspeed_g7_soc0_functions), + }, + .configs = aspeed_g7_soc0_configs, + .nconfigs = ARRAY_SIZE(aspeed_g7_soc0_configs), + .confmaps = aspeed_g7_soc0_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g7_soc0_pin_config_map), +}; + +static int aspeed_g7_soc0_pinctrl_probe(struct platform_device *pdev) +{ + return aspeed_pinctrl_probe(pdev, &aspeed_g7_soc0_pinctrl_desc, + &aspeed_g7_soc0_pinctrl_data); +} + +static const struct of_device_id aspeed_g7_soc0_pinctrl_match[] = { + { .compatible = "aspeed,ast2700-soc0-pinctrl" }, + {} +}; +MODULE_DEVICE_TABLE(of, aspeed_g7_soc0_pinctrl_match); + +static struct platform_driver aspeed_g7_soc0_pinctrl_driver = { + .probe = aspeed_g7_soc0_pinctrl_probe, + .driver = { + .name = "aspeed-g7-soc0-pinctrl", + .of_match_table = aspeed_g7_soc0_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init aspeed_g7_soc0_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g7_soc0_pinctrl_driver); +} +arch_initcall(aspeed_g7_soc0_pinctrl_init); diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c new file mode 100644 index 000000000000..f8b4066699ce --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c @@ -0,0 +1,1758 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl driver for Aspeed G7 SoC1 + * + * Copyright (C) 2026 Aspeed Technology Inc. + */ + +#include <linux/errno.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" + +#define ASPEED_G7_SOC1_NR_PINS 220 +#define ASPEED_G7_SOC1_REG_WIDTH 32 +#define ASPEED_G7_SOC1_REG_STRIDE 4 + +#define ASPEED_G7_SOC1_MUX_BASE 0x400 +#define ASPEED_G7_SOC1_BIAS_BASE 0x480 +#define ASPEED_G7_SOC1_DRV_BASE 0x4C0 +#define ASPEED_G7_SOC1_PCIE_REG 0x908 +#define ASPEED_G7_SOC1_USB_MODE_REG 0x3B0 +#define ASPEED_G7_SOC1_SGMII_REG 0x47C + +/* + * Each pin occupies a 4-bit slot in the MUX registers (MUX_BITS_PER_PIN), + * but only bits [2:0] select the mux function; bit 3 is reserved read-only + * and must not be written. MUX_FUNC_MASK therefore covers 3 bits, not 4. + */ +#define ASPEED_G7_SOC1_MUX_FUNC_MASK 0x7 +#define ASPEED_G7_SOC1_MUX_BITS_PER_PIN 4 +#define ASPEED_G7_SOC1_MUX_PINS_PER_REG \ + (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_MUX_BITS_PER_PIN) + +#define ASPEED_G7_SOC1_BIAS_FUNC_MASK 0x1 +#define ASPEED_G7_SOC1_BIAS_BITS_PER_PIN 1 +#define ASPEED_G7_SOC1_BIAS_PINS_PER_REG \ + (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_BIAS_BITS_PER_PIN) + +#define ASPEED_G7_SOC1_DRV_FUNC_MASK 0x3 +#define ASPEED_G7_SOC1_DRV_BITS_PER_PIN 2 +#define ASPEED_G7_SOC1_DRV_PINS_PER_REG \ + (ASPEED_G7_SOC1_REG_WIDTH / ASPEED_G7_SOC1_DRV_BITS_PER_PIN) + +#define ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA 4 +#define ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE 1 +#define ASPEED_G7_SOC1_DRV_STRENGTH_MIN_MA \ + (ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE * ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) +#define ASPEED_G7_SOC1_DRV_STRENGTH_MAX_MA \ + ((ASPEED_G7_SOC1_DRV_FUNC_MASK + ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE) * \ + ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) + +/* + * NOTE: The numeric values of these enum entries are significant. + * They must match the SoC GPIO numbering / ball-to-GPIO ID mapping. + * Do not reorder alphabetically. + */ +enum { + C16, + C14, + C11, + D9, + F14, + D10, + C12, + C13, + AC26, + AA25, + AB23, + U22, + V21, + N26, + P25, + N25, + V23, + W22, + AB26, + AD26, + P26, + AE26, + AF26, + AF25, + AE25, + AD25, + AF23, + AF20, + AF21, + AE21, + AE23, + AD22, + AF17, + AA16, + Y16, + V17, + J13, + AB16, + AC16, + AF16, + AA15, + AB15, + AC15, + AD15, + Y15, + AA14, + W16, + V16, + AB18, + AC18, + K13, + AA17, + AB17, + AD16, + AC17, + AD17, + AE16, + AE17, + AB24, + W26, + HOLE0, + HOLE1, + HOLE2, + HOLE3, + W25, + Y23, + Y24, + W21, + AA23, + AC22, + AB22, + Y21, + AE20, + AF19, + Y22, + AA20, + AA22, + AB20, + AF18, + AE19, + AD20, + AC20, + AA21, + AB21, + AC19, + AE18, + AD19, + AD18, + U25, + U26, + Y26, + AA24, + R25, + AA26, + R26, + Y25, + B16, + D14, + B15, + B14, + C17, + B13, + E14, + C15, + D24, + B23, + B22, + C23, + B18, + B21, + M15, + B19, + B26, + A25, + A24, + B24, + E26, + A21, + A19, + A18, + D26, + C26, + A23, + A22, + B25, + F26, + A26, + A14, + E10, + E13, + D12, + F10, + E11, + F11, + F13, + N15, + C20, + C19, + A8, + R14, + A7, + P14, + D20, + A6, + B6, + N14, + B7, + B8, + B9, + M14, + J11, + E7, + D19, + B11, + D15, + B12, + B10, + P13, + C18, + C6, + C7, + D7, + N13, + C8, + C9, + C10, + M16, + A15, + G11, + H7, + H8, + H9, + H10, + H11, + J9, + J10, + E9, + F9, + F8, + M13, + F7, + D8, + E8, + L12, + F12, + E12, + J12, + G7, + G8, + G9, + G10, + K12, + W17, + V18, + W18, + Y17, + AA18, + AA13, + Y18, + AA12, + W20, + V20, + Y11, + V14, + V19, + W14, + Y20, + AB19, + U21, + T24, + V24, + V22, + T23, + AC25, + AB25, + AC24, + PCIERC2_PERST, + PORTC_MODE, + PORTD_MODE, + SGMII0, +}; + +struct aspeed_g7_soc1_pinctrl { + struct device *dev; + struct regmap *regmap; + struct pinctrl_dev *pctl; +}; + +struct aspeed_g7_field { + unsigned int reg; + unsigned int shift; + unsigned int mask; +}; + +static struct aspeed_g7_field +aspeed_g7_soc1_pinmux_field_from_pin(unsigned int pin) +{ + return (struct aspeed_g7_field){ + .reg = ASPEED_G7_SOC1_MUX_BASE + + (pin / ASPEED_G7_SOC1_MUX_PINS_PER_REG) * + ASPEED_G7_SOC1_REG_STRIDE, + .shift = (pin % ASPEED_G7_SOC1_MUX_PINS_PER_REG) * + ASPEED_G7_SOC1_MUX_BITS_PER_PIN, + .mask = ASPEED_G7_SOC1_MUX_FUNC_MASK, + }; +} + +static struct aspeed_g7_field +aspeed_g7_soc1_bias_field_from_pin(unsigned int pin) +{ + return (struct aspeed_g7_field){ + .reg = ASPEED_G7_SOC1_BIAS_BASE + + (pin / ASPEED_G7_SOC1_BIAS_PINS_PER_REG) * + ASPEED_G7_SOC1_REG_STRIDE, + .shift = pin % ASPEED_G7_SOC1_BIAS_PINS_PER_REG, + .mask = ASPEED_G7_SOC1_BIAS_FUNC_MASK, + }; +} + +static struct aspeed_g7_field +aspeed_g7_soc1_drv_field_from_idx(unsigned int idx) +{ + return (struct aspeed_g7_field){ + .reg = ASPEED_G7_SOC1_DRV_BASE + + (idx / ASPEED_G7_SOC1_DRV_PINS_PER_REG) * + ASPEED_G7_SOC1_REG_STRIDE, + .shift = (idx % ASPEED_G7_SOC1_DRV_PINS_PER_REG) * + ASPEED_G7_SOC1_DRV_BITS_PER_PIN, + .mask = ASPEED_G7_SOC1_DRV_FUNC_MASK, + }; +} + +#define PIN(n) PINCTRL_PIN(n, #n) + +static const struct pinctrl_pin_desc aspeed_g7_soc1_pins[] = { + PIN(C16), + PIN(C14), + PIN(C11), + PIN(D9), + PIN(F14), + PIN(D10), + PIN(C12), + PIN(C13), + PIN(AC26), + PIN(AA25), + PIN(AB23), + PIN(U22), + PIN(V21), + PIN(N26), + PIN(P25), + PIN(N25), + PIN(V23), + PIN(W22), + PIN(AB26), + PIN(AD26), + PIN(P26), + PIN(AE26), + PIN(AF26), + PIN(AF25), + PIN(AE25), + PIN(AD25), + PIN(AF23), + PIN(AF20), + PIN(AF21), + PIN(AE21), + PIN(AE23), + PIN(AD22), + PIN(AF17), + PIN(AA16), + PIN(Y16), + PIN(V17), + PIN(J13), + PIN(AB16), + PIN(AC16), + PIN(AF16), + PIN(AA15), + PIN(AB15), + PIN(AC15), + PIN(AD15), + PIN(Y15), + PIN(AA14), + PIN(W16), + PIN(V16), + PIN(AB18), + PIN(AC18), + PIN(K13), + PIN(AA17), + PIN(AB17), + PIN(AD16), + PIN(AC17), + PIN(AD17), + PIN(AE16), + PIN(AE17), + PIN(AB24), + PIN(W26), + PIN(HOLE0), + PIN(HOLE1), + PIN(HOLE2), + PIN(HOLE3), + PIN(W25), + PIN(Y23), + PIN(Y24), + PIN(W21), + PIN(AA23), + PIN(AC22), + PIN(AB22), + PIN(Y21), + PIN(AE20), + PIN(AF19), + PIN(Y22), + PIN(AA20), + PIN(AA22), + PIN(AB20), + PIN(AF18), + PIN(AE19), + PIN(AD20), + PIN(AC20), + PIN(AA21), + PIN(AB21), + PIN(AC19), + PIN(AE18), + PIN(AD19), + PIN(AD18), + PIN(U25), + PIN(U26), + PIN(Y26), + PIN(AA24), + PIN(R25), + PIN(AA26), + PIN(R26), + PIN(Y25), + PIN(B16), + PIN(D14), + PIN(B15), + PIN(B14), + PIN(C17), + PIN(B13), + PIN(E14), + PIN(C15), + PIN(D24), + PIN(B23), + PIN(B22), + PIN(C23), + PIN(B18), + PIN(B21), + PIN(M15), + PIN(B19), + PIN(B26), + PIN(A25), + PIN(A24), + PIN(B24), + PIN(E26), + PIN(A21), + PIN(A19), + PIN(A18), + PIN(D26), + PIN(C26), + PIN(A23), + PIN(A22), + PIN(B25), + PIN(F26), + PIN(A26), + PIN(A14), + PIN(E10), + PIN(E13), + PIN(D12), + PIN(F10), + PIN(E11), + PIN(F11), + PIN(F13), + PIN(N15), + PIN(C20), + PIN(C19), + PIN(A8), + PIN(R14), + PIN(A7), + PIN(P14), + PIN(D20), + PIN(A6), + PIN(B6), + PIN(N14), + PIN(B7), + PIN(B8), + PIN(B9), + PIN(M14), + PIN(J11), + PIN(E7), + PIN(D19), + PIN(B11), + PIN(D15), + PIN(B12), + PIN(B10), + PIN(P13), + PIN(C18), + PIN(C6), + PIN(C7), + PIN(D7), + PIN(N13), + PIN(C8), + PIN(C9), + PIN(C10), + PIN(M16), + PIN(A15), + PIN(G11), + PIN(H7), + PIN(H8), + PIN(H9), + PIN(H10), + PIN(H11), + PIN(J9), + PIN(J10), + PIN(E9), + PIN(F9), + PIN(F8), + PIN(M13), + PIN(F7), + PIN(D8), + PIN(E8), + PIN(L12), + PIN(F12), + PIN(E12), + PIN(J12), + PIN(G7), + PIN(G8), + PIN(G9), + PIN(G10), + PIN(K12), + PIN(W17), + PIN(V18), + PIN(W18), + PIN(Y17), + PIN(AA18), + PIN(AA13), + PIN(Y18), + PIN(AA12), + PIN(W20), + PIN(V20), + PIN(Y11), + PIN(V14), + PIN(V19), + PIN(W14), + PIN(Y20), + PIN(AB19), + PIN(U21), + PIN(T24), + PIN(V24), + PIN(V22), + PIN(T23), + PIN(AC25), + PIN(AB25), + PIN(AC24), + PIN(PCIERC2_PERST), + PIN(PORTC_MODE), + PIN(PORTD_MODE), + PIN(SGMII0), +}; + +static const struct pinctrl_ops aspeed_g7_soc1_pctl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +struct aspeed_g7_soc1_function { + struct pinfunction pinfunction; + const u8 *muxvals; +}; + +static int aspeed_g7_soc1_drive_strength_to_hw(u32 strength, + unsigned int *val) +{ + if (strength < ASPEED_G7_SOC1_DRV_STRENGTH_MIN_MA || + strength > ASPEED_G7_SOC1_DRV_STRENGTH_MAX_MA || + strength % ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) + return -EINVAL; + + *val = (strength / ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA) - + ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE; + + return 0; +} + +static int aspeed_g7_soc1_set_mux(struct pinctrl_dev *pctldev, + unsigned int fselector, unsigned int group) +{ + struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct aspeed_g7_soc1_function *soc1_func; + const struct function_desc *fd; + const struct pinfunction *func; + const struct pingroup *grp; + struct group_desc *gd; + const char *gname; + int i, g_idx = -1, ret; + + gd = pinctrl_generic_get_group(pctldev, group); + if (!gd) + return -EINVAL; + + grp = &gd->grp; + + fd = pinmux_generic_get_function(pctldev, fselector); + if (!fd) + return -EINVAL; + + soc1_func = fd->data; + if (!soc1_func) + return -EINVAL; + + func = &soc1_func->pinfunction; + gname = grp->name; + + for (i = 0; i < func->ngroups; i++) { + if (!strcmp(gname, func->groups[i])) { + g_idx = i; + break; + } + } + + if (g_idx < 0) + return -EINVAL; + + for (i = 0; i < grp->npins; i++) { + unsigned int val = soc1_func->muxvals[g_idx]; + unsigned int pin = grp->pins[i]; + struct aspeed_g7_field field; + + if (pin == PCIERC2_PERST) { + /* + * PCIERC2_PERST is a special case: it is managed by a + * dedicated control register (0x908) instead of the + * standard 4-bit multi-function field. + */ + field.reg = ASPEED_G7_SOC1_PCIE_REG; + field.shift = 0; + field.mask = 0x1; + val = 1; + } else if (pin == PORTC_MODE || pin == PORTD_MODE) { + /* + * PORTC_MODE and PORTD_MODE are virtual "pins" that + * control the USB 2.0 controller mode settings. + * These reside in a specific control register (0x3B0) + * with non-standard bit widths. + */ + field.reg = ASPEED_G7_SOC1_USB_MODE_REG; + field.mask = 0x3; + field.shift = pin == PORTC_MODE ? 0 : 2; + } else if (pin == SGMII0) { + /* + * SGMII0 is a virtual pin whose mux control resides at + * SCU47C bit 0, outside the contiguous pin-indexed MUX + * register range starting at MUX_BASE. The field is + * 1 bit wide; use a 1-bit mask to avoid clobbering + * adjacent bits in SCU47C. + */ + field.reg = ASPEED_G7_SOC1_SGMII_REG; + field.shift = 0; + field.mask = 0x1; + } else { + /* Standard 4-bit-per-pin multi-function configuration */ + field = aspeed_g7_soc1_pinmux_field_from_pin(pin); + } + + dev_dbg(pctl->dev, + "Setting pin %u reg 0x%x shift %u to function %s (muxval=0x%x)\n", + pin, field.reg, field.shift, func->name, val); + + ret = regmap_update_bits(pctl->regmap, field.reg, + field.mask << field.shift, + val << field.shift); + if (ret) + return ret; + } + + return 0; +} + +static int aspeed_g7_soc1_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct aspeed_g7_field field; + unsigned int val = 0; + int ret = -ENOTSUPP; + + if (pin <= AC24) { + /* + * Balls W17 through AB19 are the ADC-capable pins: mux + * function 0 selects the ADC input and function 1 selects + * GPIO, unlike all other pins where function 0 is GPIO. + */ + if (pin >= W17 && pin <= AB19) + val = 1; + field = aspeed_g7_soc1_pinmux_field_from_pin(pin); + ret = regmap_update_bits(pctl->regmap, field.reg, + field.mask << field.shift, + val << field.shift); + } + + return ret; +} + +static const struct pinmux_ops aspeed_g7_soc1_pmx_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = aspeed_g7_soc1_set_mux, + .gpio_request_enable = aspeed_g7_soc1_gpio_request_enable, + .strict = true, +}; + +/* + * aspeed_g7_soc1_drv_map - Mapping table for pin drive strength control. + * + * In AST2700 SOC1, drive strength configuration is architecturally decoupled + * from the main pin mux registers (0x400 range). It is managed by a separate + * set of registers starting at 0x4C0. + * + * This table is required because: + * 1. The mapping between physical pin IDs and drive strength control slots + * is non-linear and sparse. + * For example, W25 maps to field index 8 (stored as 9), + * meaning it occupies bits [17:16] of the first 0x4C0 register. + * 2. Only a subset of physical pins supports drive strength configuration. + * + * The table stores (drive strength field index + 1). + * The field index refers to the 2-bit drive strength field position within the + * 0x4C0 register range. A value of 0 indicates that the pin does not support + * drive strength configuration (returning -ENOTSUPP). + * This +1 offset allows us to rely on C's default zero-initialization for + * unsupported pins while avoiding compiler warnings regarding overridden + * initializers. + */ +static const int aspeed_g7_soc1_drv_map[ASPEED_G7_SOC1_NR_PINS] = { + [C16] = 1, [C14] = 2, [C11] = 3, [D9] = 4, [F14] = 5, [D10] = 6, [C12] = 7, + [C13] = 8, [W25] = 9, [Y23] = 10, [Y24] = 11, [W21] = 12, [AA23] = 13, [AC22] = 14, + [AB22] = 15, [Y21] = 16, [AE20] = 17, [AF19] = 18, [Y22] = 19, [AA20] = 20, [AA22] = 21, + [AB20] = 22, [AF18] = 23, [AE19] = 24, [AD20] = 25, [AC20] = 26, [AA21] = 27, [AB21] = 28, + [AC19] = 29, [AE18] = 30, [AD19] = 31, [AD18] = 32, [U25] = 33, [U26] = 34, [Y26] = 35, + [AA24] = 36, [R25] = 37, [AA26] = 38, [R26] = 39, [Y25] = 40, [B16] = 41, [D14] = 42, + [B15] = 43, [B14] = 44, [C17] = 45, [B13] = 46, [E14] = 47, [C15] = 48, [D24] = 49, + [B23] = 50, [B22] = 51, [C23] = 52, [B18] = 53, [B21] = 54, [M15] = 55, [B19] = 56, + [B26] = 57, [A25] = 58, [A24] = 59, [B24] = 60, [E26] = 61, [A21] = 62, [A19] = 63, + [A18] = 64, [D26] = 65, [C26] = 66, [A23] = 67, [A22] = 68, [B25] = 69, [F26] = 70, + [A26] = 71, [A14] = 72, [E10] = 73, [E13] = 74, [D12] = 75, [F10] = 76, [E11] = 77, + [F11] = 78, [F13] = 79, [N15] = 80, [C20] = 81, [C19] = 82, [A8] = 83, [R14] = 84, + [A7] = 85, [P14] = 86, [D20] = 87, [A6] = 88, [B6] = 89, [N14] = 90, [B7] = 91, + [B8] = 92, [B9] = 93, [M14] = 94, [J11] = 95, [E7] = 96, [D19] = 97, [B11] = 98, + [D15] = 99, [B12] = 100, [B10] = 101, [P13] = 102, [C18] = 103, [C6] = 104, [C7] = 105, + [D7] = 106, [N13] = 107, [C8] = 108, [C9] = 109, [C10] = 110, [M16] = 111, [A15] = 112, + [E9] = 113, [F9] = 114, [F8] = 115, [M13] = 116, [F7] = 117, [D8] = 118, [E8] = 119, + [L12] = 120, +}; + +static int aspeed_g7_soc1_pin_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + struct aspeed_g7_field field; + unsigned int val, val_raw; + int ret, ds_idx; + + if (pin > AC24) + return -EINVAL; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + field = aspeed_g7_soc1_bias_field_from_pin(pin); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + /* + * The hardware has a single 1-bit enable/disable field per + * pin; pull direction is fixed in silicon and cannot be read + * back from the register. Reject readback requests for a + * specific pull direction. + */ + return -ENOTSUPP; + case PIN_CONFIG_DRIVE_STRENGTH: + ds_idx = aspeed_g7_soc1_drv_map[pin]; + if (!ds_idx) + return -ENOTSUPP; + ds_idx--; /* Adjust back to 0-based hardware index */ + field = aspeed_g7_soc1_drv_field_from_idx(ds_idx); + break; + default: + return -ENOTSUPP; + } + + ret = regmap_read(pctl->regmap, field.reg, &val_raw); + if (ret) + return ret; + + val = (val_raw & (field.mask << field.shift)) >> field.shift; + if (param == PIN_CONFIG_DRIVE_STRENGTH) + val = (val + ASPEED_G7_SOC1_DRV_STRENGTH_HW_BASE) * + ASPEED_G7_SOC1_DRV_STRENGTH_STEP_MA; + + if (!val) + return -EINVAL; + + *config = pinconf_to_config_packed(param, val); + + return 0; +} + +static int aspeed_g7_soc1_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct aspeed_g7_field field; + enum pin_config_param param; + int i, ret, ds_idx; + unsigned int val; + u32 arg; + + if (pin > AC24) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + /* + * The hardware has one enable/disable bit per pin; + * pull direction is fixed in silicon. Both PULL_UP + * and PULL_DOWN map to "enable bias"; the caller must + * request the direction that the hardware provides. + */ + case PIN_CONFIG_BIAS_DISABLE: + field = aspeed_g7_soc1_bias_field_from_pin(pin); + val = (param == PIN_CONFIG_BIAS_DISABLE) ? 1 : 0; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ds_idx = aspeed_g7_soc1_drv_map[pin]; + if (!ds_idx) + return -ENOTSUPP; + ds_idx--; /* Adjust back to 0-based hardware index */ + field = aspeed_g7_soc1_drv_field_from_idx(ds_idx); + ret = aspeed_g7_soc1_drive_strength_to_hw(arg, &val); + if (ret) + return ret; + break; + default: + return -ENOTSUPP; + } + + dev_dbg(pctl->dev, + "Configuring pin %u reg 0x%x shift %u param %d arg %u val 0x%x\n", + pin, field.reg, field.shift, param, arg, val); + + ret = regmap_update_bits(pctl->regmap, field.reg, + field.mask << field.shift, + val << field.shift); + + if (ret) + return ret; + } + + return 0; +} + +static int aspeed_g7_soc1_pin_config_group_get(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *config) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret) + return ret; + if (!npins) + return -ENODEV; + + return aspeed_g7_soc1_pin_config_get(pctldev, pins[0], config); +} + +static int aspeed_g7_soc1_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + int i; + + ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = aspeed_g7_soc1_pin_config_set(pctldev, pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops aspeed_g7_soc1_conf_ops = { + .is_generic = true, + .pin_config_get = aspeed_g7_soc1_pin_config_get, + .pin_config_set = aspeed_g7_soc1_pin_config_set, + .pin_config_group_get = aspeed_g7_soc1_pin_config_group_get, + .pin_config_group_set = aspeed_g7_soc1_pin_config_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static const struct pinctrl_desc aspeed_g7_soc1_desc = { + .name = "aspeed-g7-soc1-pinctrl", + .pins = aspeed_g7_soc1_pins, + .npins = ARRAY_SIZE(aspeed_g7_soc1_pins), + .pctlops = &aspeed_g7_soc1_pctl_ops, + .pmxops = &aspeed_g7_soc1_pmx_ops, + .confops = &aspeed_g7_soc1_conf_ops, + .owner = THIS_MODULE, +}; + + #define PIN_GROUP(name, ...) static const unsigned int name ## _pins[] = { __VA_ARGS__ } + +/* Pin Groups and Functions */ +PIN_GROUP(ADC0, W17); +PIN_GROUP(ADC1, V18); +PIN_GROUP(ADC10, Y11); +PIN_GROUP(ADC11, V14); +PIN_GROUP(ADC12, V19); +PIN_GROUP(ADC13, W14); +PIN_GROUP(ADC14, Y20); +PIN_GROUP(ADC15, AB19); +PIN_GROUP(ADC2, W18); +PIN_GROUP(ADC3, Y17); +PIN_GROUP(ADC4, AA18); +PIN_GROUP(ADC5, AA13); +PIN_GROUP(ADC6, Y18); +PIN_GROUP(ADC7, AA12); +PIN_GROUP(ADC8, W20); +PIN_GROUP(ADC9, V20); +PIN_GROUP(AUXPWRGOOD0, W14); +PIN_GROUP(AUXPWRGOOD1, Y20); +PIN_GROUP(CANBUS, G7, G8, G9); +PIN_GROUP(DI2C0, C16, D9); +PIN_GROUP(DI2C1, C14, F14); +PIN_GROUP(DI2C10, R25, AA26); +PIN_GROUP(DI2C11, R26, Y25); +PIN_GROUP(DI2C12, W25, Y23); +PIN_GROUP(DI2C13, Y24, W21); +PIN_GROUP(DI2C14, AA23, AC22); +PIN_GROUP(DI2C15, AB22, Y21); +PIN_GROUP(DI2C2, D10, C12); +PIN_GROUP(DI2C3, C11, C13); +PIN_GROUP(DI2C8, U25, U26); +PIN_GROUP(DI2C9, Y26, AA24); +PIN_GROUP(DSGPM0, D19, B10, C7, D7); +PIN_GROUP(ESPI0, B16, D14, B15, B14, C17, B13, E14, C15); +PIN_GROUP(ESPI1, C16, C14, C11, D9, F14, D10, C12, C13); +PIN_GROUP(FSI0, AD20, AC20); +PIN_GROUP(FSI1, AA21, AB21); +PIN_GROUP(FSI2, AC19, AE18); +PIN_GROUP(FSI3, AD19, AD18); +PIN_GROUP(FWQSPI, M16, A15); +PIN_GROUP(FWSPIABR, A14); +PIN_GROUP(FWWPN, N15); +PIN_GROUP(HBLED, V24); +PIN_GROUP(HVI3C0, U25, U26); +PIN_GROUP(HVI3C1, Y26, AA24); +PIN_GROUP(HVI3C12, W25, Y23); +PIN_GROUP(HVI3C13, Y24, W21); +PIN_GROUP(HVI3C14, AA23, AC22); +PIN_GROUP(HVI3C15, AB22, Y21); +PIN_GROUP(HVI3C2, R25, AA26); +PIN_GROUP(HVI3C3, R26, Y25); +PIN_GROUP(I2C0, G11, H7); +PIN_GROUP(I2C1, H8, H9); +PIN_GROUP(I2C10, G8, G9); +PIN_GROUP(I2C11, G10, K12); +PIN_GROUP(I2C12, AC18, AA17); +PIN_GROUP(I2C13, AB17, AD16); +PIN_GROUP(I2C14, AC17, AD17); +PIN_GROUP(I2C15, AE16, AE17); +PIN_GROUP(I2C2, H10, H11); +PIN_GROUP(I2C3, J9, J10); +PIN_GROUP(I2C4, E9, F9); +PIN_GROUP(I2C5, F8, M13); +PIN_GROUP(I2C6, F7, D8); +PIN_GROUP(I2C7, E8, L12); +PIN_GROUP(I2C8, F12, E12); +PIN_GROUP(I2C9, J12, G7); +PIN_GROUP(I2CF0, F12, E12, J12, G7); +PIN_GROUP(I2CF1, E9, F9, F8, M13); +PIN_GROUP(I2CF2, F7, D8, E8, L12); +PIN_GROUP(I3C10, AC19, AE18); +PIN_GROUP(I3C11, AD19, AD18); +PIN_GROUP(I3C4, AE20, AF19); +PIN_GROUP(I3C5, Y22, AA20); +PIN_GROUP(I3C6, AA22, AB20); +PIN_GROUP(I3C7, AF18, AE19); +PIN_GROUP(I3C8, AD20, AC20); +PIN_GROUP(I3C9, AA21, AB21); +PIN_GROUP(JTAGM1, F10, E11, F11, F13); +PIN_GROUP(JTAGM1TRST, D12); +PIN_GROUP(LPC0, AF26, AF25, B16, D14, B15, B14, C17, B13, E14, C15); +PIN_GROUP(LPC1, C16, C14, C11, D9, F14, D10, C12, C13, AE16, AE17); +PIN_GROUP(LTPI, U25, U26, Y26, AA24); +PIN_GROUP(LTPI_PS_I2C0, G11, H7); +PIN_GROUP(LTPI_PS_I2C1, H8, H9); +PIN_GROUP(LTPI_PS_I2C2, H10, H11); +PIN_GROUP(LTPI_PS_I2C3, J9, J10); +PIN_GROUP(MACLINK0, U21); +PIN_GROUP(MACLINK1, AC24); +PIN_GROUP(MACLINK2, T24); +PIN_GROUP(MDIO0, B9, M14); +PIN_GROUP(MDIO1, C9, C10); +PIN_GROUP(MDIO2, E10, E13); +PIN_GROUP(NCTS0, AF17); +PIN_GROUP(NCTS1, AA15); +PIN_GROUP(NCTS5, V21); +PIN_GROUP(NCTS6, AB26); +PIN_GROUP(NDCD0, AA16); +PIN_GROUP(NDCD1, AB15); +PIN_GROUP(NDCD5, N26); +PIN_GROUP(NDCD6, AD26); +PIN_GROUP(NDSR0, Y16); +PIN_GROUP(NDSR1, AC15); +PIN_GROUP(NDSR5, P25); +PIN_GROUP(NDSR6, P26); +PIN_GROUP(NDTR0, J13); +PIN_GROUP(NDTR1, Y15); +PIN_GROUP(NDTR5, V23); +PIN_GROUP(NDTR6, AF26); +PIN_GROUP(NRI0, V17); +PIN_GROUP(NRI1, AD15); +PIN_GROUP(NRI5, N25); +PIN_GROUP(NRI6, AE26); +PIN_GROUP(NRTS0, AB16); +PIN_GROUP(NRTS1, AA14); +PIN_GROUP(NRTS5, W22); +PIN_GROUP(NRTS6, AF25); +PIN_GROUP(OSCCLK, C17); +PIN_GROUP(PE2SGRSTN, E10, PCIERC2_PERST); +PIN_GROUP(PWM0, AE25); +PIN_GROUP(PWM1, AD25); +PIN_GROUP(PWM10, AB17); +PIN_GROUP(PWM11, AD16); +PIN_GROUP(PWM12, AC17); +PIN_GROUP(PWM13, AD17); +PIN_GROUP(PWM14, AE16); +PIN_GROUP(PWM15, AE17); +PIN_GROUP(PWM2, AF23); +PIN_GROUP(PWM3, AF20); +PIN_GROUP(PWM4, AF21); +PIN_GROUP(PWM5, AE21); +PIN_GROUP(PWM6, AE23); +PIN_GROUP(PWM7, AD22); +PIN_GROUP(PWM8, K13); +PIN_GROUP(PWM9, AA17); +PIN_GROUP(QSPI0, C23, B18); +PIN_GROUP(QSPI1, B24, E26); +PIN_GROUP(QSPI2, B25, F26); +PIN_GROUP(RGMII0, C20, C19, A8, R14, A7, P14, D20, A6, B6, N14, B7, B8); +PIN_GROUP(RGMII1, D19, B11, D15, B12, B10, P13, C18, C6, C7, D7, N13, C8); +PIN_GROUP(RMII0, C20, A8, R14, A7, P14, A6, B6, N14); +PIN_GROUP(RMII0RCLKO, D20); +PIN_GROUP(RMII1, D19, D15, B12, B10, P13, C6, C7, D7); +PIN_GROUP(RMII1RCLKO, C18); +PIN_GROUP(SALT0, AC17); +PIN_GROUP(SALT1, AD17); +PIN_GROUP(SALT10, Y18); +PIN_GROUP(SALT11, AA12); +PIN_GROUP(SALT12, AB26); +PIN_GROUP(SALT13, AD26); +PIN_GROUP(SALT14, P26); +PIN_GROUP(SALT15, AE26); +PIN_GROUP(SALT2, AC15); +PIN_GROUP(SALT3, AD15); +PIN_GROUP(SALT4, W17); +PIN_GROUP(SALT5, V18); +PIN_GROUP(SALT6, W18); +PIN_GROUP(SALT7, Y17); +PIN_GROUP(SALT8, AA18); +PIN_GROUP(SALT9, AA13); +PIN_GROUP(SD, C16, C14, C11, D9, F14, D10, C12, C13); +PIN_GROUP(SGMII, SGMII0); +PIN_GROUP(SGPM0, U21, T24, V22, T23); +PIN_GROUP(SGPM1, AC25, AB25, AB24, W26); +PIN_GROUP(SGPS, B11, C18, N13, C8); +PIN_GROUP(SIOONCTRLN0, AE23); +PIN_GROUP(SIOONCTRLN1, AA15); +PIN_GROUP(SIOPBIN0, AD25); +PIN_GROUP(SIOPBIN1, AA16); +PIN_GROUP(SIOPBON0, AE25); +PIN_GROUP(SIOPBON1, AF17); +PIN_GROUP(SIOPWREQN0, AE21); +PIN_GROUP(SIOPWREQN1, AB16); +PIN_GROUP(SIOPWRGD1, AB15); +PIN_GROUP(SIOS3N0, AF20); +PIN_GROUP(SIOS3N1, V17); +PIN_GROUP(SIOS5N0, AF21); +PIN_GROUP(SIOS5N1, J13); +PIN_GROUP(SIOSCIN0, AF23); +PIN_GROUP(SIOSCIN1, Y16); +PIN_GROUP(SMON0, U21, T24, V22, T23); +PIN_GROUP(SMON1, W26, AC25, AB25); +PIN_GROUP(SPI0, D24, B23, B22); +PIN_GROUP(SPI0ABR, M15); +PIN_GROUP(SPI0CS1, B21); +PIN_GROUP(SPI0WPN, B19); +PIN_GROUP(SPI1, B26, A25, A24); +PIN_GROUP(SPI1ABR, A19); +PIN_GROUP(SPI1CS1, A21); +PIN_GROUP(SPI1WPN, A18); +PIN_GROUP(SPI2, D26, C26, A23, A22); +PIN_GROUP(SPI2CS1, A26); +PIN_GROUP(TACH0, AC26); +PIN_GROUP(TACH1, AA25); +PIN_GROUP(TACH10, AB26); +PIN_GROUP(TACH11, AD26); +PIN_GROUP(TACH12, P26); +PIN_GROUP(TACH13, AE26); +PIN_GROUP(TACH14, AF26); +PIN_GROUP(TACH15, AF25); +PIN_GROUP(TACH2, AB23); +PIN_GROUP(TACH3, U22); +PIN_GROUP(TACH4, V21); +PIN_GROUP(TACH5, N26); +PIN_GROUP(TACH6, P25); +PIN_GROUP(TACH7, N25); +PIN_GROUP(TACH8, V23); +PIN_GROUP(TACH9, W22); +PIN_GROUP(THRU0, AC26, AA25); +PIN_GROUP(THRU1, AB23, U22); +PIN_GROUP(THRU2, A19, A18); +PIN_GROUP(THRU3, B25, F26); +PIN_GROUP(UART0, AC16, AF16); +PIN_GROUP(UART1, W16, V16); +PIN_GROUP(UART2, AB18, AC18); +PIN_GROUP(UART3, K13, AA17); +PIN_GROUP(UART5, AB17, AD16); +PIN_GROUP(UART6, AC17, AD17); +PIN_GROUP(UART7, AE16, AE17); +PIN_GROUP(UART8, M15, B19); +PIN_GROUP(UART9, B26, A25); +PIN_GROUP(UART10, A24, B24); +PIN_GROUP(UART11, E26, A21); +PIN_GROUP(USB2CD, PORTC_MODE); +PIN_GROUP(USB2CH, PORTC_MODE); +PIN_GROUP(USB2CU, PORTC_MODE); +PIN_GROUP(USB2CUD, PORTC_MODE); +PIN_GROUP(USB2DD, PORTD_MODE); +PIN_GROUP(USB2DH, PORTD_MODE); +PIN_GROUP(USBUART, G10, K12); +PIN_GROUP(VGA, J11, E7); +PIN_GROUP(VPI, C16, C14, C11, D9, F14, D10, AC26, AA25, AB23, U22, V21, N26, + P25, N25, V23, W22, AB26, AD26, P26, AE26, AF26, AF25, AE25, AD25, + AF23, AF20, AF21, AE21); +PIN_GROUP(WDTRST0N, K13); +PIN_GROUP(WDTRST1N, AA17); +PIN_GROUP(WDTRST2N, AB17); +PIN_GROUP(WDTRST3N, AD16); +PIN_GROUP(WDTRST4N, AC25); +PIN_GROUP(WDTRST5N, AB25); +PIN_GROUP(WDTRST6N, AC24); +PIN_GROUP(WDTRST7N, AB24); + +#define GROUP(n) PINCTRL_PINGROUP(#n, n##_pins, ARRAY_SIZE(n##_pins)) + +static const struct pingroup aspeed_g7_soc1_groups[] = { + GROUP(ADC0), + GROUP(ADC1), + GROUP(ADC10), + GROUP(ADC11), + GROUP(ADC12), + GROUP(ADC13), + GROUP(ADC14), + GROUP(ADC15), + GROUP(ADC2), + GROUP(ADC3), + GROUP(ADC4), + GROUP(ADC5), + GROUP(ADC6), + GROUP(ADC7), + GROUP(ADC8), + GROUP(ADC9), + GROUP(AUXPWRGOOD0), + GROUP(AUXPWRGOOD1), + GROUP(CANBUS), + GROUP(DI2C0), + GROUP(DI2C1), + GROUP(DI2C10), + GROUP(DI2C11), + GROUP(DI2C12), + GROUP(DI2C13), + GROUP(DI2C14), + GROUP(DI2C15), + GROUP(DI2C2), + GROUP(DI2C3), + GROUP(DI2C8), + GROUP(DI2C9), + GROUP(DSGPM0), + GROUP(ESPI0), + GROUP(ESPI1), + GROUP(FSI0), + GROUP(FSI1), + GROUP(FSI2), + GROUP(FSI3), + GROUP(FWQSPI), + GROUP(FWSPIABR), + GROUP(FWWPN), + GROUP(HBLED), + GROUP(HVI3C0), + GROUP(HVI3C1), + GROUP(HVI3C12), + GROUP(HVI3C13), + GROUP(HVI3C14), + GROUP(HVI3C15), + GROUP(HVI3C2), + GROUP(HVI3C3), + GROUP(I2C0), + GROUP(I2C1), + GROUP(I2C10), + GROUP(I2C11), + GROUP(I2C12), + GROUP(I2C13), + GROUP(I2C14), + GROUP(I2C15), + GROUP(I2C2), + GROUP(I2C3), + GROUP(I2C4), + GROUP(I2C5), + GROUP(I2C6), + GROUP(I2C7), + GROUP(I2C8), + GROUP(I2C9), + GROUP(I2CF0), + GROUP(I2CF1), + GROUP(I2CF2), + GROUP(I3C10), + GROUP(I3C11), + GROUP(I3C4), + GROUP(I3C5), + GROUP(I3C6), + GROUP(I3C7), + GROUP(I3C8), + GROUP(I3C9), + GROUP(JTAGM1), + GROUP(JTAGM1TRST), + GROUP(LPC0), + GROUP(LPC1), + GROUP(LTPI), + GROUP(LTPI_PS_I2C0), + GROUP(LTPI_PS_I2C1), + GROUP(LTPI_PS_I2C2), + GROUP(LTPI_PS_I2C3), + GROUP(MACLINK0), + GROUP(MACLINK1), + GROUP(MACLINK2), + GROUP(MDIO0), + GROUP(MDIO1), + GROUP(MDIO2), + GROUP(NCTS0), + GROUP(NCTS1), + GROUP(NCTS5), + GROUP(NCTS6), + GROUP(NDCD0), + GROUP(NDCD1), + GROUP(NDCD5), + GROUP(NDCD6), + GROUP(NDSR0), + GROUP(NDSR1), + GROUP(NDSR5), + GROUP(NDSR6), + GROUP(NDTR0), + GROUP(NDTR1), + GROUP(NDTR5), + GROUP(NDTR6), + GROUP(NRI0), + GROUP(NRI1), + GROUP(NRI5), + GROUP(NRI6), + GROUP(NRTS0), + GROUP(NRTS1), + GROUP(NRTS5), + GROUP(NRTS6), + GROUP(OSCCLK), + GROUP(PE2SGRSTN), + GROUP(PWM0), + GROUP(PWM1), + GROUP(PWM10), + GROUP(PWM11), + GROUP(PWM12), + GROUP(PWM13), + GROUP(PWM14), + GROUP(PWM15), + GROUP(PWM2), + GROUP(PWM3), + GROUP(PWM4), + GROUP(PWM5), + GROUP(PWM6), + GROUP(PWM7), + GROUP(PWM8), + GROUP(PWM9), + GROUP(QSPI0), + GROUP(QSPI1), + GROUP(QSPI2), + GROUP(RGMII0), + GROUP(RGMII1), + GROUP(RMII0), + GROUP(RMII0RCLKO), + GROUP(RMII1), + GROUP(RMII1RCLKO), + GROUP(SALT0), + GROUP(SALT1), + GROUP(SALT10), + GROUP(SALT11), + GROUP(SALT12), + GROUP(SALT13), + GROUP(SALT14), + GROUP(SALT15), + GROUP(SALT2), + GROUP(SALT3), + GROUP(SALT4), + GROUP(SALT5), + GROUP(SALT6), + GROUP(SALT7), + GROUP(SALT8), + GROUP(SALT9), + GROUP(SD), + GROUP(SGMII), + GROUP(SGPM0), + GROUP(SGPM1), + GROUP(SGPS), + GROUP(SIOONCTRLN0), + GROUP(SIOONCTRLN1), + GROUP(SIOPBIN0), + GROUP(SIOPBIN1), + GROUP(SIOPBON0), + GROUP(SIOPBON1), + GROUP(SIOPWREQN0), + GROUP(SIOPWREQN1), + GROUP(SIOPWRGD1), + GROUP(SIOS3N0), + GROUP(SIOS3N1), + GROUP(SIOS5N0), + GROUP(SIOS5N1), + GROUP(SIOSCIN0), + GROUP(SIOSCIN1), + GROUP(SMON0), + GROUP(SMON1), + GROUP(SPI0), + GROUP(SPI0ABR), + GROUP(SPI0CS1), + GROUP(SPI0WPN), + GROUP(SPI1), + GROUP(SPI1ABR), + GROUP(SPI1CS1), + GROUP(SPI1WPN), + GROUP(SPI2), + GROUP(SPI2CS1), + GROUP(TACH0), + GROUP(TACH1), + GROUP(TACH10), + GROUP(TACH11), + GROUP(TACH12), + GROUP(TACH13), + GROUP(TACH14), + GROUP(TACH15), + GROUP(TACH2), + GROUP(TACH3), + GROUP(TACH4), + GROUP(TACH5), + GROUP(TACH6), + GROUP(TACH7), + GROUP(TACH8), + GROUP(TACH9), + GROUP(THRU0), + GROUP(THRU1), + GROUP(THRU2), + GROUP(THRU3), + GROUP(UART0), + GROUP(UART1), + GROUP(UART10), + GROUP(UART11), + GROUP(UART2), + GROUP(UART3), + GROUP(UART5), + GROUP(UART6), + GROUP(UART7), + GROUP(UART8), + GROUP(UART9), + GROUP(USB2CD), + GROUP(USB2CH), + GROUP(USB2CU), + GROUP(USB2CUD), + GROUP(USB2DD), + GROUP(USB2DH), + GROUP(USBUART), + GROUP(VGA), + GROUP(VPI), + GROUP(WDTRST0N), + GROUP(WDTRST1N), + GROUP(WDTRST2N), + GROUP(WDTRST3N), + GROUP(WDTRST4N), + GROUP(WDTRST5N), + GROUP(WDTRST6N), + GROUP(WDTRST7N), +}; + +/** + * VM() - Helper macro to unwrap a parenthesized list of arguments. + * @...: The parenthesized list to be unwrapped. + * + * Since the C preprocessor treats commas inside braces {} as argument + * separators for macros, we wrap lists (like mux values) in parentheses () + * to protect them during macro expansion. This macro strips those + * parentheses when the values are needed for array initialization. + */ +#define VM(...) __VA_ARGS__ + +/** + * FUNC() - Macro to initialize an aspeed_g7_soc1_function entry. + * @n: Name of the pin function. + * @m: Parenthesized list of mux values, mapped 1:1 to the groups list. + * @...: Variable list of pin group names associated with this function. + * + * This macro solves complex static initialization by: + * 1. Creating anonymous arrays for both group names and mux values + * using C99 Compound Literals. + * 2. Using VM(m) to unwrap mux values into the array initializer. + * 3. Calculating the number of groups via sizeof() division, which + * bypasses the __must_be_array() check performed by ARRAY_SIZE() + * that often fails on compound literals in the kernel environment. + * + * Example: FUNC(i2c0, (1, 4), "i2c0", "di2c0") + * Maps "i2c0" group to mux value 1 and "di2c0" group to mux value 4. + */ +#define FUNC(n, m, ...) \ + { \ + .pinfunction = { \ + .name = #n, \ + .groups = (const char *const[]){ __VA_ARGS__ }, \ + .ngroups = sizeof((const char *const[]){ __VA_ARGS__ }) / sizeof(char *), \ + }, \ + .muxvals = (const u8[]){ VM m } \ + } + +static const struct aspeed_g7_soc1_function aspeed_g7_soc1_functions[] = { + FUNC(ADC0, (0), "ADC0"), + FUNC(ADC1, (0), "ADC1"), + FUNC(ADC10, (0), "ADC10"), + FUNC(ADC11, (0), "ADC11"), + FUNC(ADC12, (0), "ADC12"), + FUNC(ADC13, (0), "ADC13"), + FUNC(ADC14, (0), "ADC14"), + FUNC(ADC15, (0), "ADC15"), + FUNC(ADC2, (0), "ADC2"), + FUNC(ADC3, (0), "ADC3"), + FUNC(ADC4, (0), "ADC4"), + FUNC(ADC5, (0), "ADC5"), + FUNC(ADC6, (0), "ADC6"), + FUNC(ADC7, (0), "ADC7"), + FUNC(ADC8, (0), "ADC8"), + FUNC(ADC9, (0), "ADC9"), + FUNC(AUXPWRGOOD0, (2), "AUXPWRGOOD0"), + FUNC(AUXPWRGOOD1, (2), "AUXPWRGOOD1"), + FUNC(CANBUS, (2), "CANBUS"), + FUNC(ESPI0, (1), "ESPI0"), + FUNC(ESPI1, (1), "ESPI1"), + FUNC(FSI0, (2), "FSI0"), + FUNC(FSI1, (2), "FSI1"), + FUNC(FSI2, (2), "FSI2"), + FUNC(FSI3, (2), "FSI3"), + FUNC(FWQSPI, (1), "FWQSPI"), + FUNC(FWSPIABR, (1), "FWSPIABR"), + FUNC(FWWPN, (1), "FWWPN"), + FUNC(HBLED, (2), "HBLED"), + FUNC(I2C0, (1, 2, 4), "I2C0", "LTPI_PS_I2C0", "DI2C0"), + FUNC(I2C1, (1, 2, 4), "I2C1", "LTPI_PS_I2C1", "DI2C1"), + FUNC(I2C10, (1, 2), "I2C10", "DI2C10"), + FUNC(I2C11, (1, 2), "I2C11", "DI2C11"), + FUNC(I2C12, (4, 2), "I2C12", "DI2C12"), + FUNC(I2C13, (4, 2), "I2C13", "DI2C13"), + FUNC(I2C14, (4, 2), "I2C14", "DI2C14"), + FUNC(I2C15, (2, 2), "I2C15", "DI2C15"), + FUNC(I2C2, (1, 2, 4), "I2C2", "LTPI_PS_I2C2", "DI2C2"), + FUNC(I2C3, (1, 2, 4), "I2C3", "LTPI_PS_I2C3", "DI2C3"), + FUNC(I2C4, (1), "I2C4"), + FUNC(I2C5, (1), "I2C5"), + FUNC(I2C6, (1), "I2C6"), + FUNC(I2C7, (1), "I2C7"), + FUNC(I2C8, (1, 2), "I2C8", "DI2C8"), + FUNC(I2C9, (1, 2), "I2C9", "DI2C9"), + FUNC(I2CF0, (5), "I2CF0"), + FUNC(I2CF1, (5), "I2CF1"), + FUNC(I2CF2, (5), "I2CF2"), + FUNC(I3C0, (1), "HVI3C0"), + FUNC(I3C1, (1), "HVI3C1"), + FUNC(I3C10, (1), "I3C10"), + FUNC(I3C11, (1), "I3C11"), + FUNC(I3C12, (1), "HVI3C12"), + FUNC(I3C13, (1), "HVI3C13"), + FUNC(I3C14, (1), "HVI3C14"), + FUNC(I3C15, (1), "HVI3C15"), + FUNC(I3C2, (1), "HVI3C2"), + FUNC(I3C3, (1), "HVI3C3"), + FUNC(I3C4, (1), "I3C4"), + FUNC(I3C5, (1), "I3C5"), + FUNC(I3C6, (1), "I3C6"), + FUNC(I3C7, (1), "I3C7"), + FUNC(I3C8, (1), "I3C8"), + FUNC(I3C9, (1), "I3C9"), + FUNC(JTAGM1, (1, 1), "JTAGM1", "JTAGM1TRST"), + FUNC(LPC0, (2), "LPC0"), + FUNC(LPC1, (2), "LPC1"), + FUNC(LTPI, (2), "LTPI"), + FUNC(MACLINK0, (4), "MACLINK0"), + FUNC(MACLINK1, (3), "MACLINK1"), + FUNC(MACLINK2, (4), "MACLINK2"), + FUNC(MDIO0, (1), "MDIO0"), + FUNC(MDIO1, (1), "MDIO1"), + FUNC(MDIO2, (1), "MDIO2"), + FUNC(NCTS0, (1), "NCTS0"), + FUNC(NCTS1, (1), "NCTS1"), + FUNC(NCTS5, (4), "NCTS5"), + FUNC(NCTS6, (4), "NCTS6"), + FUNC(NDCD0, (1), "NDCD0"), + FUNC(NDCD1, (1), "NDCD1"), + FUNC(NDCD5, (4), "NDCD5"), + FUNC(NDCD6, (4), "NDCD6"), + FUNC(NDSR0, (1), "NDSR0"), + FUNC(NDSR1, (1), "NDSR1"), + FUNC(NDSR5, (4), "NDSR5"), + FUNC(NDSR6, (4), "NDSR6"), + FUNC(NDTR0, (1), "NDTR0"), + FUNC(NDTR1, (1), "NDTR1"), + FUNC(NDTR5, (4), "NDTR5"), + FUNC(NDTR6, (4), "NDTR6"), + FUNC(NRI0, (1), "NRI0"), + FUNC(NRI1, (1), "NRI1"), + FUNC(NRI5, (4), "NRI5"), + FUNC(NRI6, (4), "NRI6"), + FUNC(NRTS0, (1), "NRTS0"), + FUNC(NRTS1, (1), "NRTS1"), + FUNC(NRTS5, (4), "NRTS5"), + FUNC(NRTS6, (4), "NRTS6"), + FUNC(OSCCLK, (3), "OSCCLK"), + FUNC(PCIERC, (2), "PE2SGRSTN"), + FUNC(PWM0, (1), "PWM0"), + FUNC(PWM1, (1), "PWM1"), + FUNC(PWM10, (3), "PWM10"), + FUNC(PWM11, (3), "PWM11"), + FUNC(PWM12, (3), "PWM12"), + FUNC(PWM13, (3), "PWM13"), + FUNC(PWM14, (3), "PWM14"), + FUNC(PWM15, (3), "PWM15"), + FUNC(PWM2, (1), "PWM2"), + FUNC(PWM3, (1), "PWM3"), + FUNC(PWM4, (1), "PWM4"), + FUNC(PWM5, (1), "PWM5"), + FUNC(PWM6, (1), "PWM6"), + FUNC(PWM7, (1), "PWM7"), + FUNC(PWM8, (3), "PWM8"), + FUNC(PWM9, (3), "PWM9"), + FUNC(QSPI0, (1), "QSPI0"), + FUNC(QSPI1, (1), "QSPI1"), + FUNC(QSPI2, (1), "QSPI2"), + FUNC(RGMII0, (1), "RGMII0"), + FUNC(RGMII1, (1), "RGMII1"), + FUNC(RMII0, (2), "RMII0"), + FUNC(RMII0RCLKO, (2), "RMII0RCLKO"), + FUNC(RMII1, (2), "RMII1"), + FUNC(RMII1RCLKO, (2), "RMII1RCLKO"), + FUNC(SALT0, (2), "SALT0"), + FUNC(SALT1, (2), "SALT1"), + FUNC(SALT10, (2), "SALT10"), + FUNC(SALT11, (2), "SALT11"), + FUNC(SALT12, (2), "SALT12"), + FUNC(SALT13, (2), "SALT13"), + FUNC(SALT14, (2), "SALT14"), + FUNC(SALT15, (2), "SALT15"), + FUNC(SALT2, (2), "SALT2"), + FUNC(SALT3, (2), "SALT3"), + FUNC(SALT4, (2), "SALT4"), + FUNC(SALT5, (2), "SALT5"), + FUNC(SALT6, (2), "SALT6"), + FUNC(SALT7, (2), "SALT7"), + FUNC(SALT8, (2), "SALT8"), + FUNC(SALT9, (2), "SALT9"), + FUNC(SD, (3), "SD"), + FUNC(SGMII, (1), "SGMII"), + FUNC(SGPM0, (1, 4), "SGPM0", "DSGPM0"), + FUNC(SGPM1, (1), "SGPM1"), + FUNC(SGPS, (5), "SGPS"), + FUNC(SIOONCTRLN0, (2), "SIOONCTRLN0"), + FUNC(SIOONCTRLN1, (2), "SIOONCTRLN1"), + FUNC(SIOPBIN0, (2), "SIOPBIN0"), + FUNC(SIOPBIN1, (2), "SIOPBIN1"), + FUNC(SIOPBON0, (2), "SIOPBON0"), + FUNC(SIOPBON1, (2), "SIOPBON1"), + FUNC(SIOPWREQN0, (2), "SIOPWREQN0"), + FUNC(SIOPWREQN1, (2), "SIOPWREQN1"), + FUNC(SIOPWRGD1, (2), "SIOPWRGD1"), + FUNC(SIOS3N0, (2), "SIOS3N0"), + FUNC(SIOS3N1, (2), "SIOS3N1"), + FUNC(SIOS5N0, (2), "SIOS5N0"), + FUNC(SIOS5N1, (2), "SIOS5N1"), + FUNC(SIOSCIN0, (2), "SIOSCIN0"), + FUNC(SIOSCIN1, (2), "SIOSCIN1"), + FUNC(SMON0, (2), "SMON0"), + FUNC(SMON1, (4), "SMON1"), + FUNC(SPI0, (1), "SPI0"), + FUNC(SPI0ABR, (1), "SPI0ABR"), + FUNC(SPI0CS1, (1), "SPI0CS1"), + FUNC(SPI0WPN, (1), "SPI0WPN"), + FUNC(SPI1, (1), "SPI1"), + FUNC(SPI1ABR, (1), "SPI1ABR"), + FUNC(SPI1CS1, (1), "SPI1CS1"), + FUNC(SPI1WPN, (1), "SPI1WPN"), + FUNC(SPI2, (1), "SPI2"), + FUNC(SPI2CS1, (1), "SPI2CS1"), + FUNC(TACH0, (1), "TACH0"), + FUNC(TACH1, (1), "TACH1"), + FUNC(TACH10, (1), "TACH10"), + FUNC(TACH11, (1), "TACH11"), + FUNC(TACH12, (1), "TACH12"), + FUNC(TACH13, (1), "TACH13"), + FUNC(TACH14, (1), "TACH14"), + FUNC(TACH15, (1), "TACH15"), + FUNC(TACH2, (1), "TACH2"), + FUNC(TACH3, (1), "TACH3"), + FUNC(TACH4, (1), "TACH4"), + FUNC(TACH5, (1), "TACH5"), + FUNC(TACH6, (1), "TACH6"), + FUNC(TACH7, (1), "TACH7"), + FUNC(TACH8, (1), "TACH8"), + FUNC(TACH9, (1), "TACH9"), + FUNC(THRU0, (2), "THRU0"), + FUNC(THRU1, (2), "THRU1"), + FUNC(THRU2, (4), "THRU2"), + FUNC(THRU3, (4), "THRU3"), + FUNC(UART0, (1), "UART0"), + FUNC(UART1, (1), "UART1"), + FUNC(UART10, (3), "UART10"), + FUNC(UART11, (3), "UART11"), + FUNC(UART2, (1), "UART2"), + FUNC(UART3, (1), "UART3"), + FUNC(UART5, (4), "UART5"), + FUNC(UART6, (4), "UART6"), + FUNC(UART7, (1), "UART7"), + FUNC(UART8, (3), "UART8"), + FUNC(UART9, (3), "UART9"), + FUNC(USB2C, (0, 1, 2, 3), "USB2CUD", "USB2CD", "USB2CH", "USB2CU"), + FUNC(USB2D, (1, 2), "USB2DD", "USB2DH"), + FUNC(USBUART, (2), "USBUART"), + FUNC(VGA, (1), "VGA"), + FUNC(VPI, (5), "VPI"), + FUNC(WDTRST0N, (2), "WDTRST0N"), + FUNC(WDTRST1N, (2), "WDTRST1N"), + FUNC(WDTRST2N, (2), "WDTRST2N"), + FUNC(WDTRST3N, (2), "WDTRST3N"), + FUNC(WDTRST4N, (2), "WDTRST4N"), + FUNC(WDTRST5N, (2), "WDTRST5N"), + FUNC(WDTRST6N, (2), "WDTRST6N"), + FUNC(WDTRST7N, (2), "WDTRST7N"), +}; + +static int aspeed_g7_soc1_pinctrl_probe(struct platform_device *pdev) +{ + struct aspeed_g7_soc1_pinctrl *pctl; + struct device *dev = &pdev->dev; + int i, ret; + + pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + pctl->dev = dev; + pctl->regmap = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(pctl->regmap)) { + dev_err(dev, "Failed to get regmap from parent\n"); + return PTR_ERR(pctl->regmap); + } + + ret = devm_pinctrl_register_and_init(dev, &aspeed_g7_soc1_desc, pctl, + &pctl->pctl); + if (ret) { + dev_err(dev, "Failed to register pinctrl\n"); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(aspeed_g7_soc1_groups); i++) { + const struct pingroup *grp = &aspeed_g7_soc1_groups[i]; + + ret = pinctrl_generic_add_group(pctl->pctl, grp->name, + (const unsigned int *)grp->pins, + grp->npins, pctl); + if (ret < 0) { + dev_err(dev, "Failed to add group %s\n", grp->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(aspeed_g7_soc1_functions); i++) { + const struct aspeed_g7_soc1_function *func = &aspeed_g7_soc1_functions[i]; + + ret = pinmux_generic_add_function(pctl->pctl, func->pinfunction.name, + func->pinfunction.groups, + func->pinfunction.ngroups, (void *)func); + if (ret < 0) { + dev_err(dev, "Failed to add function %s\n", func->pinfunction.name); + return ret; + } + } + + return pinctrl_enable(pctl->pctl); +} + +static const struct of_device_id aspeed_g7_soc1_pinctrl_match[] = { + { .compatible = "aspeed,ast2700-soc1-pinctrl" }, + {} +}; +MODULE_DEVICE_TABLE(of, aspeed_g7_soc1_pinctrl_match); + +static struct platform_driver aspeed_g7_soc1_pinctrl_driver = { + .probe = aspeed_g7_soc1_pinctrl_probe, + .driver = { + .name = "aspeed-g7-soc1-pinctrl", + .of_match_table = aspeed_g7_soc1_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init aspeed_g7_soc1_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g7_soc1_pinctrl_driver); +} +arch_initcall(aspeed_g7_soc1_pinctrl_init); diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 206f3f1249cf..19d22e7fd11e 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -121,6 +121,7 @@ source "drivers/pinctrl/bcm/Kconfig.stb" config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" depends on ARCH_BCM_IPROC || COMPILE_TEST + select GPIOLIB select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF @@ -186,6 +187,7 @@ config PINCTRL_NS config PINCTRL_NSP_GPIO bool "Broadcom NSP GPIO (with PINCONF) driver" depends on ARCH_BCM_NSP || COMPILE_TEST + select GPIOLIB select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index e7b35019a5a7..725e880ae086 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1350,7 +1350,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) pc->pctl_desc = *pdata->pctl_desc; pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); if (IS_ERR(pc->pctl_dev)) { - gpiochip_remove(&pc->gpio_chip); return PTR_ERR(pc->pctl_dev); } diff --git a/drivers/pinctrl/bcm/pinctrl-bcm4908.c b/drivers/pinctrl/bcm/pinctrl-bcm4908.c index 12f7a253ea4d..709ef4add927 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm4908.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c @@ -3,7 +3,6 @@ #include <linux/err.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> @@ -466,6 +465,7 @@ static const struct of_device_id bcm4908_pinctrl_of_match_table[] = { { .compatible = "brcm,bcm4908-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table); static int bcm4908_pinctrl_probe(struct platform_device *pdev) { @@ -561,4 +561,3 @@ module_platform_driver(bcm4908_pinctrl_driver); MODULE_AUTHOR("Rafał Miłecki"); MODULE_DESCRIPTION("Broadcom BCM4908 pinmux driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.c b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c index 59d2ce8462d8..b41a3d16aabe 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm63xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c @@ -8,7 +8,6 @@ #include <linux/gpio/regmap.h> #include <linux/mfd/syscon.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -20,6 +19,7 @@ #define BCM63XX_DATA_REG 0x0c static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.h b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h index 95243027ecd9..3dcfabb94ece 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm63xx.h +++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 8c353676f2af..e20f7dc79d43 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -868,7 +868,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) gc->set = iproc_gpio_set; gc->get = iproc_gpio_get; - chip->pinmux_is_supported = of_property_read_bool(dev->of_node, + chip->pinmux_is_supported = of_property_present(dev->of_node, "gpio-ranges"); /* optional GPIO interrupt support */ diff --git a/drivers/pinctrl/bcm/pinctrl-ns.c b/drivers/pinctrl/bcm/pinctrl-ns.c index 03bd01b4a945..e134c9c73450 100644 --- a/drivers/pinctrl/bcm/pinctrl-ns.c +++ b/drivers/pinctrl/bcm/pinctrl-ns.c @@ -204,6 +204,7 @@ static const struct of_device_id ns_pinctrl_of_match_table[] = { { .compatible = "brcm,bcm53012-pinmux", .data = (void *)FLAG_BCM53012, }, { } }; +MODULE_DEVICE_TABLE(of, ns_pinctrl_of_match_table); static int ns_pinctrl_probe(struct platform_device *pdev) { @@ -295,4 +296,3 @@ static struct platform_driver ns_pinctrl_driver = { module_platform_driver(ns_pinctrl_driver); MODULE_AUTHOR("Rafał Miłecki"); -MODULE_DEVICE_TABLE(of, ns_pinctrl_of_match_table); diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index b425ecacd1b0..83fcc80d5967 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -159,7 +159,7 @@ static void nsp_gpio_irq_ack(struct irq_data *d) u32 trigger_type; trigger_type = irq_get_trigger_type(d->irq); - if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + if (trigger_type & IRQ_TYPE_EDGE_BOTH) writel(val, chip->base + NSP_GPIO_EVENT); } @@ -177,7 +177,7 @@ static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) u32 trigger_type; trigger_type = irq_get_trigger_type(d->irq); - if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + if (trigger_type & IRQ_TYPE_EDGE_BOTH) nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); else nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); @@ -671,11 +671,8 @@ static int nsp_gpio_probe(struct platform_device *pdev) /* Install ISR for this GPIO controller. */ ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler, IRQF_SHARED, "gpio-a", &chip->gc); - if (ret) { - dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n", - irq, ret); + if (ret) return ret; - } girq = &chip->gc.irq; gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip); diff --git a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c index 227c37c360e1..8990fab0446c 100644 --- a/drivers/pinctrl/cirrus/pinctrl-cs42l43.c +++ b/drivers/pinctrl/cirrus/pinctrl-cs42l43.c @@ -343,7 +343,7 @@ static int cs42l43_pin_set_db(struct cs42l43_pin *priv, unsigned int pin, return regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL2, CS42L43_GPIO1_DEGLITCH_BYP_MASK << pin, - !!us << pin); + !us << pin); } static int cs42l43_pin_config_get(struct pinctrl_dev *pctldev, @@ -499,12 +499,10 @@ static int cs42l43_gpio_set(struct gpio_chip *chip, unsigned int offset, ret = regmap_update_bits(priv->regmap, CS42L43_GPIO_CTRL1, BIT(shift), value << shift); - if (ret) - return ret; pm_runtime_put(priv->dev); - return 0; + return ret; } static int cs42l43_gpio_direction_out(struct gpio_chip *chip, @@ -604,8 +602,8 @@ static int cs42l43_pin_probe(struct platform_device *pdev) } static const struct platform_device_id cs42l43_pin_id_table[] = { - { "cs42l43-pinctrl", }, - {} + { .name = "cs42l43-pinctrl" }, + { } }; MODULE_DEVICE_TABLE(platform, cs42l43_pin_id_table); diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 6cbcaa6709da..1675dd36bd5c 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -622,8 +622,13 @@ static int pinctrl_generic_group_name_to_selector(struct pinctrl_dev *pctldev, const char *function) { const struct pinctrl_ops *ops = pctldev->desc->pctlops; - int ngroups = ops->get_groups_count(pctldev); int selector = 0; + int ngroups; + + if (!ops->get_groups_count || !ops->get_group_name) + return -EINVAL; + + ngroups = ops->get_groups_count(pctldev); /* See if this pctldev has this group */ while (selector < ngroups) { @@ -738,8 +743,15 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, const char *pin_group) { const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - unsigned int ngroups = pctlops->get_groups_count(pctldev); unsigned int group_selector = 0; + unsigned int ngroups; + + if (!pctlops->get_groups_count || !pctlops->get_group_name) { + dev_err(pctldev->dev, "does not support pin groups\n"); + return -EINVAL; + } + + ngroups = pctlops->get_groups_count(pctldev); while (group_selector < ngroups) { const char *gname = pctlops->get_group_name(pctldev, @@ -760,6 +772,7 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, return -EINVAL; } +EXPORT_SYMBOL_GPL(pinctrl_get_group_selector); bool pinctrl_gpio_can_use_line(struct gpio_chip *gc, unsigned int offset) { @@ -1801,6 +1814,11 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) mutex_lock(&pctldev->mutex); + if (!ops->get_groups_count || !ops->get_group_name) { + mutex_unlock(&pctldev->mutex); + return 0; + } + ngroups = ops->get_groups_count(pctldev); seq_puts(s, "registered pin groups:\n"); @@ -2081,12 +2099,25 @@ static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev) static int pinctrl_check_ops(struct pinctrl_dev *pctldev) { const struct pinctrl_ops *ops = pctldev->desc->pctlops; + const struct pinconf_ops *confops = pctldev->desc->confops; + bool needs_groups = false; - if (!ops || - !ops->get_groups_count || - !ops->get_group_name) + if (!ops) return -EINVAL; + if (pctldev->desc->pmxops) + needs_groups = true; + + if (confops && (confops->pin_config_group_get || + confops->pin_config_group_set)) + needs_groups = true; + + if (needs_groups && (!ops->get_groups_count || !ops->get_group_name)) { + dev_err(pctldev->dev, + "driver needs group callbacks for mux or group config\n"); + return -EINVAL; + } + return 0; } diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 02a271dd292f..465b43092eb7 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -69,6 +69,10 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, int i; struct pinctrl_dt_map *dt_map; + /* Initialize dev_name before any allocation can fail */ + for (i = 0; i < num_maps; i++) + map[i].dev_name = NULL; + /* Initialize common mapping table entry fields */ for (i = 0; i < num_maps; i++) { const char *devname; diff --git a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c index e14bdbc7bea7..613552e35070 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c +++ b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c @@ -9,7 +9,6 @@ #include <linux/err.h> #include <linux/errno.h> #include <linux/module.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/scmi_protocol.h> #include <linux/seq_file.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index b36c8a1461b7..4a6bdaefa42f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -540,10 +540,31 @@ static int imx1_pinctrl_parse_functions(struct device_node *np, return 0; } +/* + * Check if the DT contains pins in the direct child nodes. This indicates the + * newer DT format to store pins. This function returns true if the first found + * fsl,pins property is in a child of np. Otherwise false is returned. + */ +static bool imx1_pinctrl_dt_is_flat_functions(struct device_node *np) +{ + for_each_child_of_node_scoped(np, function_np) { + if (of_property_present(function_np, "fsl,pins")) + return true; + + for_each_child_of_node_scoped(function_np, pinctrl_np) { + if (of_property_present(pinctrl_np, "fsl,pins")) + return false; + } + } + + return true; +} + static int imx1_pinctrl_parse_dt(struct platform_device *pdev, struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info) { struct device_node *np = pdev->dev.of_node; + bool flat_funcs; int ret; u32 nfuncs = 0; u32 ngroups = 0; @@ -552,9 +573,15 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev, if (!np) return -ENODEV; - for_each_child_of_node_scoped(np, child) { - ++nfuncs; - ngroups += of_get_child_count(child); + flat_funcs = imx1_pinctrl_dt_is_flat_functions(np); + if (flat_funcs) { + nfuncs = 1; + ngroups = of_get_child_count(np); + } else { + for_each_child_of_node_scoped(np, child) { + ++nfuncs; + ngroups += of_get_child_count(child); + } } if (!nfuncs) { @@ -574,10 +601,14 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev, if (!info->functions || !info->groups) return -ENOMEM; - for_each_child_of_node_scoped(np, child) { - ret = imx1_pinctrl_parse_functions(child, info, ifunc++); - if (ret == -ENOMEM) - return -ENOMEM; + if (flat_funcs) { + imx1_pinctrl_parse_functions(np, info, 0); + } else { + for_each_child_of_node_scoped(np, child) { + ret = imx1_pinctrl_parse_functions(child, info, ifunc++); + if (ret == -ENOMEM) + return -ENOMEM; + } } return 0; diff --git a/drivers/pinctrl/freescale/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c index 0404efbf2a86..7655c1a0cd66 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx23.c +++ b/drivers/pinctrl/freescale/pinctrl-imx23.c @@ -6,7 +6,6 @@ // Copyright 2012 Freescale Semiconductor, Inc. #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-mxs.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c index d2b0b6aad306..e1604c3bdcec 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx25.c +++ b/drivers/pinctrl/freescale/pinctrl-imx25.c @@ -14,7 +14,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c index afeb39957203..37fdac794455 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx27.c +++ b/drivers/pinctrl/freescale/pinctrl-imx27.c @@ -9,7 +9,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c index eb847151713a..aa013ba280b3 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx28.c +++ b/drivers/pinctrl/freescale/pinctrl-imx28.c @@ -6,7 +6,6 @@ // Copyright 2012 Freescale Semiconductor, Inc. #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-mxs.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c index 1546517d8110..88aa0583b0d2 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx35.c +++ b/drivers/pinctrl/freescale/pinctrl-imx35.c @@ -12,7 +12,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c index 9b044aee4f7c..b54f98cfa63c 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx50.c +++ b/drivers/pinctrl/freescale/pinctrl-imx50.c @@ -9,7 +9,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c index e580c022bebe..fb0a81a6d29c 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx51.c +++ b/drivers/pinctrl/freescale/pinctrl-imx51.c @@ -10,7 +10,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c index 1034192ab410..3c94ec4dffbe 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx53.c +++ b/drivers/pinctrl/freescale/pinctrl-imx53.c @@ -10,7 +10,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c index 09542fdcd405..6a1cafa69230 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c @@ -8,7 +8,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c index ae5cec74a3e8..3ba2ff757322 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6q.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c @@ -10,7 +10,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c index 3111f50263f6..15483f10f743 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c @@ -8,7 +8,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c b/drivers/pinctrl/freescale/pinctrl-imx6sll.c index 72a7214811ab..27d24f5d58e4 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sll.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c @@ -7,7 +7,6 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c index aa76bc6d7402..4e4b78b5b42d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c @@ -8,7 +8,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c index ba0ef1ea5722..063805daee03 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c @@ -8,7 +8,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c index 7dec709ebd9a..fe957d09eb40 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -8,7 +8,6 @@ #include <linux/firmware/imx/sci.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c b/drivers/pinctrl/freescale/pinctrl-imx8mq.c index e59e4fc80193..845aed2f0e34 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mq.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c @@ -8,7 +8,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c index 37ef3229231b..884c8311be70 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -10,7 +10,6 @@ #include <linux/firmware/imx/sci.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c index 5632c7285147..88af25b0d48e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c @@ -6,7 +6,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx91.c b/drivers/pinctrl/freescale/pinctrl-imx91.c index 5421141c586a..312a81d79fb3 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx91.c +++ b/drivers/pinctrl/freescale/pinctrl-imx91.c @@ -4,7 +4,6 @@ */ #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c b/drivers/pinctrl/freescale/pinctrl-imx93.c index 5977dda3b759..8458a41c583e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx93.c +++ b/drivers/pinctrl/freescale/pinctrl-imx93.c @@ -6,7 +6,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 76adcc5abdec..76a4bc0181a0 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -7,7 +7,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index dcb541976f2f..415bc0a16957 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index 3d3c1706928a..269b8e25db84 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -6,7 +6,6 @@ * Author: Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> @@ -995,8 +994,8 @@ static const struct acpi_device_id bxt_pinctrl_acpi_match[] = { MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match); static const struct platform_device_id bxt_pinctrl_platform_ids[] = { - { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data }, - { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data }, + { .name = "apollolake-pinctrl", .driver_data = (kernel_ulong_t)apl_pinctrl_soc_data }, + { .name = "broxton-pinctrl", .driver_data = (kernel_ulong_t)bxt_pinctrl_soc_data }, { } }; MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids); diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index baa7c9a62ff9..b45480e05312 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -7,7 +7,6 @@ * Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c index 578e1ee57acf..02fd1cc4fd1b 100644 --- a/drivers/pinctrl/intel/pinctrl-cedarfork.c +++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c @@ -6,7 +6,6 @@ * Author: Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c index 4a1d346fb30c..47636a9719ed 100644 --- a/drivers/pinctrl/intel/pinctrl-denverton.c +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -6,7 +6,6 @@ * Author: Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> @@ -250,7 +249,7 @@ static const struct acpi_device_id dnv_pinctrl_acpi_match[] = { MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match); static const struct platform_device_id dnv_pinctrl_platform_ids[] = { - { "denverton-pinctrl", (kernel_ulong_t)&dnv_soc_data }, + { .name = "denverton-pinctrl", .driver_data = (kernel_ulong_t)&dnv_soc_data }, { } }; MODULE_DEVICE_TABLE(platform, dnv_pinctrl_platform_ids); diff --git a/drivers/pinctrl/intel/pinctrl-elkhartlake.c b/drivers/pinctrl/intel/pinctrl-elkhartlake.c index 8a24ef12141d..822724c7571b 100644 --- a/drivers/pinctrl/intel/pinctrl-elkhartlake.c +++ b/drivers/pinctrl/intel/pinctrl-elkhartlake.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-emmitsburg.c b/drivers/pinctrl/intel/pinctrl-emmitsburg.c index 3b63b6dd2560..f5a602ba49af 100644 --- a/drivers/pinctrl/intel/pinctrl-emmitsburg.c +++ b/drivers/pinctrl/intel/pinctrl-emmitsburg.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-geminilake.c b/drivers/pinctrl/intel/pinctrl-geminilake.c index 8dcac4fe8493..21d0d5051b04 100644 --- a/drivers/pinctrl/intel/pinctrl-geminilake.c +++ b/drivers/pinctrl/intel/pinctrl-geminilake.c @@ -6,7 +6,6 @@ * Author: Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-intel-platform.c b/drivers/pinctrl/intel/pinctrl-intel-platform.c index 61dd579e3f97..c83e3859b655 100644 --- a/drivers/pinctrl/intel/pinctrl-intel-platform.c +++ b/drivers/pinctrl/intel/pinctrl-intel-platform.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 97bf5ec78db4..261ec2ee63ef 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1414,7 +1414,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) IRQF_SHARED | IRQF_NO_THREAD, dev_name(pctrl->dev), pctrl); if (ret) - return dev_err_probe(pctrl->dev, ret, "failed to request interrupt\n"); + return ret; /* Setup IRQ chip */ girq = &pctrl->chip.irq; @@ -1556,13 +1556,13 @@ static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, struct intel_community *community, unsigned short capability_offset) { - void __iomem *base = community->regs + capability_offset + 4; static const struct pwm_lpss_boardinfo info = { .clk_rate = 19200000, .npwm = 1, .base_unit_bits = 22, }; struct pwm_chip *chip; + void __iomem *base; if (!(community->features & PINCTRL_FEATURE_PWM)) return 0; @@ -1570,6 +1570,7 @@ static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, if (!IS_REACHABLE(CONFIG_PWM_LPSS)) return 0; + base = community->regs + capability_offset + 4; chip = devm_pwm_lpss_probe(pctrl->dev, base, &info); return PTR_ERR_OR_ZERO(chip); } diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c index a8f65c3dbb1c..55780654a847 100644 --- a/drivers/pinctrl/intel/pinctrl-jasperlake.c +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-lakefield.c b/drivers/pinctrl/intel/pinctrl-lakefield.c index 39872c352ac2..8a1ef3b75ea0 100644 --- a/drivers/pinctrl/intel/pinctrl-lakefield.c +++ b/drivers/pinctrl/intel/pinctrl-lakefield.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c index ebbc94047b6f..4bf5010afd71 100644 --- a/drivers/pinctrl/intel/pinctrl-lewisburg.c +++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c @@ -6,7 +6,6 @@ * Author: Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index 83b4d1862545..5cf54bc18f86 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -8,7 +8,6 @@ #include <linux/array_size.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/types.h> diff --git a/drivers/pinctrl/intel/pinctrl-meteorlake.c b/drivers/pinctrl/intel/pinctrl-meteorlake.c index 3f5070a339bf..6fefee7827ed 100644 --- a/drivers/pinctrl/intel/pinctrl-meteorlake.c +++ b/drivers/pinctrl/intel/pinctrl-meteorlake.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-meteorpoint.c b/drivers/pinctrl/intel/pinctrl-meteorpoint.c index bff7be1f137d..f7fe3c20951c 100644 --- a/drivers/pinctrl/intel/pinctrl-meteorpoint.c +++ b/drivers/pinctrl/intel/pinctrl-meteorpoint.c @@ -6,7 +6,6 @@ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-moorefield.c b/drivers/pinctrl/intel/pinctrl-moorefield.c index 30f9a4481827..59f46b0e2156 100644 --- a/drivers/pinctrl/intel/pinctrl-moorefield.c +++ b/drivers/pinctrl/intel/pinctrl-moorefield.c @@ -8,7 +8,6 @@ #include <linux/array_size.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/types.h> diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 308651091d9c..77ac32ab9577 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -7,7 +7,6 @@ * Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index ae231f7fba49..93234f4a9bd0 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -7,7 +7,6 @@ * Mika Westerberg <mika.westerberg@linux.intel.com> */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> @@ -330,6 +329,34 @@ static const struct pinctrl_pin_desc tgllp_pins[] = { PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), }; +static const unsigned int tgllp_i2c0_pins[] = { 5, 6 }; +static const unsigned int tgllp_i2c1_pins[] = { 7, 8 }; +static const unsigned int tgllp_pwm0_pins[] = { 99 }; +static const unsigned int tgllp_uart1_pins[] = { 85, 86, 87, 88 }; +static const unsigned int tgllp_ssp2_pins[] = { 108, 109, 110, 111 }; + +static const struct intel_pingroup tgllp_groups[] = { + PIN_GROUP("i2c0_grp", tgllp_i2c0_pins, 2), + PIN_GROUP("i2c1_grp", tgllp_i2c1_pins, 2), + PIN_GROUP("pwm0_grp", tgllp_pwm0_pins, 2), + PIN_GROUP("uart1_grp", tgllp_uart1_pins, 2), + PIN_GROUP("ssp2_grp", tgllp_ssp2_pins, 7), +}; + +static const char * const tgllp_i2c0_groups[] = { "i2c0_grp" }; +static const char * const tgllp_i2c1_groups[] = { "i2c1_grp" }; +static const char * const tgllp_pwm0_groups[] = { "pwm0_grp" }; +static const char * const tgllp_uart1_groups[] = { "uart1_grp" }; +static const char * const tgllp_ssp2_groups[] = { "ssp2_grp" }; + +static const struct intel_function tgllp_functions[] = { + FUNCTION("i2c0", tgllp_i2c0_groups), + FUNCTION("i2c1", tgllp_i2c1_groups), + FUNCTION("pwm0", tgllp_pwm0_groups), + FUNCTION("uart1", tgllp_uart1_groups), + FUNCTION("ssp2", tgllp_ssp2_groups), +}; + static const struct intel_padgroup tgllp_community0_gpps[] = { INTEL_GPP(0, 0, 25, 0), /* GPP_B */ INTEL_GPP(1, 26, 41, 32), /* GPP_T */ @@ -367,6 +394,10 @@ static const struct intel_community tgllp_communities[] = { static const struct intel_pinctrl_soc_data tgllp_soc_data = { .pins = tgllp_pins, .npins = ARRAY_SIZE(tgllp_pins), + .groups = tgllp_groups, + .ngroups = ARRAY_SIZE(tgllp_groups), + .functions = tgllp_functions, + .nfunctions = ARRAY_SIZE(tgllp_functions), .communities = tgllp_communities, .ncommunities = ARRAY_SIZE(tgllp_communities), }; diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 4819617d9368..30ef3dc5dfb1 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "MediaTek pinctrl drivers" - depends on ARCH_MEDIATEK || ARCH_AIROHA || RALINK || COMPILE_TEST + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST config EINT_MTK tristate "MediaTek External Interrupt Support" @@ -11,7 +11,7 @@ config EINT_MTK default PINCTRL_MTK_PARIS config PINCTRL_MTK - bool + tristate depends on OF select PINMUX select GENERIC_PINCONF @@ -22,13 +22,13 @@ config PINCTRL_MTK_V2 tristate config PINCTRL_MTK_MTMIPS - bool + tristate depends on RALINK select PINMUX select GENERIC_PINCONF config PINCTRL_MTK_MOORE - bool + tristate depends on OF select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS @@ -48,42 +48,42 @@ config PINCTRL_MTK_PARIS # For MIPS SoCs config PINCTRL_MT7620 - bool "MediaTek MT7620 pin control" + tristate "MediaTek MT7620 pin control" depends on SOC_MT7620 || COMPILE_TEST depends on RALINK default SOC_MT7620 select PINCTRL_MTK_MTMIPS config PINCTRL_MT7621 - bool "MediaTek MT7621 pin control" + tristate "MediaTek MT7621 pin control" depends on SOC_MT7621 || COMPILE_TEST depends on RALINK default SOC_MT7621 select PINCTRL_MTK_MTMIPS config PINCTRL_MT76X8 - bool "MediaTek MT76X8 pin control" + tristate "MediaTek MT76X8 pin control" depends on SOC_MT7620 || COMPILE_TEST depends on RALINK default SOC_MT7620 select PINCTRL_MTK_MTMIPS config PINCTRL_RT2880 - bool "Ralink RT2880 pin control" + tristate "Ralink RT2880 pin control" depends on SOC_RT288X || COMPILE_TEST depends on RALINK default SOC_RT288X select PINCTRL_MTK_MTMIPS config PINCTRL_RT305X - bool "Ralink RT305X pin control" + tristate "Ralink RT305X pin control" depends on SOC_RT305X || COMPILE_TEST depends on RALINK default SOC_RT305X select PINCTRL_MTK_MTMIPS config PINCTRL_RT3883 - bool "Ralink RT3883 pin control" + tristate "Ralink RT3883 pin control" depends on SOC_RT3883 || COMPILE_TEST depends on RALINK default SOC_RT3883 @@ -91,58 +91,43 @@ config PINCTRL_RT3883 # For ARMv7 SoCs config PINCTRL_MT2701 - bool "MediaTek MT2701 pin control" + tristate "MediaTek MT2701 pin control" depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST depends on OF default MACH_MT2701 select PINCTRL_MTK config PINCTRL_MT7623 - bool "MediaTek MT7623 pin control with generic binding" + tristate "MediaTek MT7623 pin control with generic binding" depends on MACH_MT7623 || COMPILE_TEST depends on OF default MACH_MT7623 select PINCTRL_MTK_MOORE config PINCTRL_MT7629 - bool "MediaTek MT7629 pin control" + tristate "MediaTek MT7629 pin control" depends on MACH_MT7629 || COMPILE_TEST depends on OF default MACH_MT7629 select PINCTRL_MTK_MOORE config PINCTRL_MT8135 - bool "MediaTek MT8135 pin control" + tristate "MediaTek MT8135 pin control" depends on MACH_MT8135 || COMPILE_TEST depends on OF default MACH_MT8135 select PINCTRL_MTK config PINCTRL_MT8127 - bool "MediaTek MT8127 pin control" + tristate "MediaTek MT8127 pin control" depends on MACH_MT8127 || COMPILE_TEST depends on OF default MACH_MT8127 select PINCTRL_MTK # For ARMv8 SoCs -config PINCTRL_AIROHA - tristate "Airoha EN7581 pin control" - depends on OF - depends on ARM64 || COMPILE_TEST - select PINMUX - select GENERIC_PINCONF - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GPIOLIB - select GPIOLIB_IRQCHIP - select REGMAP_MMIO - help - Say yes here to support pin controller and gpio driver - on Airoha EN7581 SoC. - config PINCTRL_MT2712 - bool "MediaTek MT2712 pin control" + tristate "MediaTek MT2712 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -168,21 +153,31 @@ config PINCTRL_MT6779 map specific eint which doesn't have real gpio pin. config PINCTRL_MT6795 - bool "MediaTek MT6795 pin control" + tristate "MediaTek MT6795 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT6797 - bool "MediaTek MT6797 pin control" + tristate "MediaTek MT6797 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + +config PINCTRL_MT6858 + tristate "MediaTek MT6858 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on the MediaTek MT6858 SoC. config PINCTRL_MT6878 - bool "MediaTek MT6878 pin control" + tristate "MediaTek MT6878 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -192,7 +187,7 @@ config PINCTRL_MT6878 on the MediaTek MT6878 SoC. config PINCTRL_MT6893 - bool "MediaTek Dimensity MT6893 pin control" + tristate "MediaTek Dimensity MT6893 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -202,63 +197,63 @@ config PINCTRL_MT6893 on the MediaTek Dimensity 1200 MT6893 Smartphone SoC. config PINCTRL_MT7622 - bool "MediaTek MT7622 pin control" + tristate "MediaTek MT7622 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7981 - bool "MediaTek MT7981 pin control" + tristate "MediaTek MT7981 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7986 - bool "MediaTek MT7986 pin control" + tristate "MediaTek MT7986 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT7988 - bool "Mediatek MT7988 pin control" + tristate "Mediatek MT7988 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE config PINCTRL_MT8167 - bool "MediaTek MT8167 pin control" + tristate "MediaTek MT8167 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8173 - bool "MediaTek MT8173 pin control" + tristate "MediaTek MT8173 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8183 - bool "MediaTek MT8183 pin control" + tristate "MediaTek MT8183 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8186 - bool "MediaTek MT8186 pin control" + tristate "MediaTek MT8186 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8188 - bool "MediaTek MT8188 pin control" + tristate "MediaTek MT8188 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -270,7 +265,7 @@ config PINCTRL_MT8188 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8189 - bool "MediaTek MT8189 pin control" + tristate "MediaTek MT8189 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -282,21 +277,21 @@ config PINCTRL_MT8189 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8192 - bool "MediaTek MT8192 pin control" + tristate "MediaTek MT8192 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8195 - bool "MediaTek MT8195 pin control" + tristate "MediaTek MT8195 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS config PINCTRL_MT8196 - bool "MediaTek MT8196 pin control" + tristate "MediaTek MT8196 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -308,14 +303,14 @@ config PINCTRL_MT8196 map specific eint which doesn't have real gpio pin. config PINCTRL_MT8365 - bool "MediaTek MT8365 pin control" + tristate "MediaTek MT8365 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK config PINCTRL_MT8516 - bool "MediaTek MT8516 pin control" + tristate "MediaTek MT8516 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK @@ -323,7 +318,7 @@ config PINCTRL_MT8516 # For PMIC config PINCTRL_MT6397 - bool "MediaTek MT6397 pin control" + tristate "MediaTek MT6397 pin control" depends on MFD_MT6397 || COMPILE_TEST depends on OF default MFD_MT6397 diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index ae765bd99965..6ee3833dc6e2 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers -obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o @@ -23,6 +22,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT6858) += pinctrl-mt6858.o obj-$(CONFIG_PINCTRL_MT6878) += pinctrl-mt6878.o obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 2a3c04eedc5f..827231dc0d24 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -12,8 +12,10 @@ */ #include <linux/delay.h> +#include <linux/device.h> #include <linux/err.h> #include <linux/gpio/driver.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> @@ -214,7 +216,7 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) writel(mask, reg); } - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { + if (type & IRQ_TYPE_EDGE_BOTH) { reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr); writel(mask, reg); } else { @@ -246,7 +248,7 @@ static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) } static void mtk_eint_chip_write_mask(const struct mtk_eint *eint, - void __iomem *base, unsigned int **buf) + unsigned int **buf) { int inst, port, port_num; void __iomem *reg; @@ -425,7 +427,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc) int mtk_eint_do_suspend(struct mtk_eint *eint) { - mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask); + mtk_eint_chip_write_mask(eint, eint->wake_mask); return 0; } @@ -433,7 +435,7 @@ EXPORT_SYMBOL_GPL(mtk_eint_do_suspend); int mtk_eint_do_resume(struct mtk_eint *eint) { - mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask); + mtk_eint_chip_write_mask(eint, eint->cur_mask); return 0; } @@ -509,6 +511,27 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) } EXPORT_SYMBOL_GPL(mtk_eint_find_irq); +static void mtk_eint_teardown(void *data) +{ + struct mtk_eint *eint = data; + unsigned int i, virq; + + /* Detach the demux handler so it can no longer reference freed data. */ + irq_set_chained_handler_and_data(eint->irq, NULL, NULL); + + /* Wait for any in-flight handler to finish before tearing down. */ + synchronize_irq(eint->irq); + + /* Dispose of all child mappings before the domain is removed. */ + for (i = 0; i < eint->hw->ap_num; i++) { + virq = irq_find_mapping(eint->domain, i); + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(eint->domain); +} + int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin) { unsigned int size, i, port, virq, inst = 0; @@ -601,7 +624,7 @@ int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin) irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler, eint); - return 0; + return devm_add_action_or_reset(eint->dev, mtk_eint_teardown, eint); err_eint: for (i = 0; i < eint->nbase; i++) { diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c deleted file mode 100644 index 995ba6175c95..000000000000 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ /dev/null @@ -1,3030 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Author: Lorenzo Bianconi <lorenzo@kernel.org> - * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> - * Author: Markus Gothe <markus.gothe@genexis.eu> - */ - -#include <dt-bindings/pinctrl/mt65xx.h> -#include <linux/bitfield.h> -#include <linux/bits.h> -#include <linux/cleanup.h> -#include <linux/gpio/driver.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/mfd/syscon.h> -#include <linux/of.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/regmap.h> - -#include "../core.h" -#include "../pinconf.h" -#include "../pinmux.h" - -#define PINCTRL_PIN_GROUP(id, table) \ - PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) - -#define PINCTRL_FUNC_DESC(id, table) \ - { \ - .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ - ARRAY_SIZE(table##_groups)),\ - .groups = table##_func_group, \ - .group_size = ARRAY_SIZE(table##_func_group), \ - } - -#define PINCTRL_CONF_DESC(p, offset, mask) \ - { \ - .pin = p, \ - .reg = { offset, mask }, \ - } - -/* MUX */ -#define REG_GPIO_2ND_I2C_MODE 0x0214 -#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14) -#define GPIO_I2C_MASTER_MODE_MODE BIT(13) -#define GPIO_I2S_MODE_MASK BIT(12) -#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) -#define GPIO_LAN3_LED1_MODE_MASK BIT(10) -#define GPIO_LAN3_LED0_MODE_MASK BIT(9) -#define GPIO_LAN2_LED1_MODE_MASK BIT(8) -#define GPIO_LAN2_LED0_MODE_MASK BIT(7) -#define GPIO_LAN1_LED1_MODE_MASK BIT(6) -#define GPIO_LAN1_LED0_MODE_MASK BIT(5) -#define GPIO_LAN0_LED1_MODE_MASK BIT(4) -#define GPIO_LAN0_LED0_MODE_MASK BIT(3) -#define PON_TOD_1PPS_MODE_MASK BIT(2) -#define GSW_TOD_1PPS_MODE_MASK BIT(1) -#define GPIO_2ND_I2C_MODE_MASK BIT(0) - -#define REG_GPIO_SPI_CS1_MODE 0x0218 -#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) -#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) -#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) -#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) -#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) -#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) -#define GPIO_PCM_SPI_MODE_MASK BIT(16) -#define GPIO_PCM2_MODE_MASK BIT(13) -#define GPIO_PCM1_MODE_MASK BIT(12) -#define GPIO_PCM_INT_MODE_MASK BIT(9) -#define GPIO_PCM_RESET_MODE_MASK BIT(8) -#define GPIO_SPI_QUAD_MODE_MASK BIT(4) -#define GPIO_SPI_CS4_MODE_MASK BIT(3) -#define GPIO_SPI_CS3_MODE_MASK BIT(2) -#define GPIO_SPI_CS2_MODE_MASK BIT(1) -#define GPIO_SPI_CS1_MODE_MASK BIT(0) - -#define REG_GPIO_PON_MODE 0x021c -#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) -#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) -#define GPIO_PCIE_RESET2_MASK BIT(12) -#define SIPO_RCLK_MODE_MASK BIT(11) -#define GPIO_PCIE_RESET1_MASK BIT(10) -#define GPIO_PCIE_RESET0_MASK BIT(9) -#define GPIO_UART5_MODE_MASK BIT(8) -#define GPIO_UART4_MODE_MASK BIT(7) -#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) -#define GPIO_HSUART_MODE_MASK BIT(5) -#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) -#define GPIO_UART2_MODE_MASK BIT(3) -#define GPIO_SIPO_MODE_MASK BIT(2) -#define GPIO_EMMC_MODE_MASK BIT(1) -#define GPIO_PON_MODE_MASK BIT(0) - -#define REG_NPU_UART_EN 0x0224 -#define JTAG_UDI_EN_MASK BIT(4) -#define JTAG_DFD_EN_MASK BIT(3) - -#define REG_FORCE_GPIO_EN 0x0228 -#define FORCE_GPIO_EN(n) BIT(n) - -/* LED MAP */ -#define REG_LAN_LED0_MAPPING 0x027c -#define REG_LAN_LED1_MAPPING 0x0280 - -#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) -#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) - -#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) -#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) - -#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) -#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) - -#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) -#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) - -#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) -#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) - -/* CONF */ -#define REG_I2C_SDA_E2 0x001c -#define AN7583_I2C1_SCL_E2_MASK BIT(16) -#define AN7583_I2C1_SDA_E2_MASK BIT(15) -#define SPI_MISO_E2_MASK BIT(14) -#define SPI_MOSI_E2_MASK BIT(13) -#define SPI_CLK_E2_MASK BIT(12) -#define SPI_CS0_E2_MASK BIT(11) -#define PCIE2_RESET_E2_MASK BIT(10) -#define PCIE1_RESET_E2_MASK BIT(9) -#define PCIE0_RESET_E2_MASK BIT(8) -#define AN7583_MDIO_0_E2_MASK BIT(5) -#define AN7583_MDC_0_E2_MASK BIT(4) -#define UART1_RXD_E2_MASK BIT(3) -#define UART1_TXD_E2_MASK BIT(2) -#define I2C_SCL_E2_MASK BIT(1) -#define I2C_SDA_E2_MASK BIT(0) - -#define REG_I2C_SDA_E4 0x0020 -#define AN7583_I2C1_SCL_E4_MASK BIT(16) -#define AN7583_I2C1_SDA_E4_MASK BIT(15) -#define SPI_MISO_E4_MASK BIT(14) -#define SPI_MOSI_E4_MASK BIT(13) -#define SPI_CLK_E4_MASK BIT(12) -#define SPI_CS0_E4_MASK BIT(11) -#define PCIE2_RESET_E4_MASK BIT(10) -#define PCIE1_RESET_E4_MASK BIT(9) -#define PCIE0_RESET_E4_MASK BIT(8) -#define AN7583_MDIO_0_E4_MASK BIT(5) -#define AN7583_MDC_0_E4_MASK BIT(4) -#define UART1_RXD_E4_MASK BIT(3) -#define UART1_TXD_E4_MASK BIT(2) -#define I2C_SCL_E4_MASK BIT(1) -#define I2C_SDA_E4_MASK BIT(0) - -#define REG_GPIO_L_E2 0x0024 -#define REG_GPIO_L_E4 0x0028 -#define REG_GPIO_H_E2 0x002c -#define REG_GPIO_H_E4 0x0030 - -#define REG_I2C_SDA_PU 0x0044 -#define AN7583_I2C1_SCL_PU_MASK BIT(16) -#define AN7583_I2C1_SDA_PU_MASK BIT(15) -#define SPI_MISO_PU_MASK BIT(14) -#define SPI_MOSI_PU_MASK BIT(13) -#define SPI_CLK_PU_MASK BIT(12) -#define SPI_CS0_PU_MASK BIT(11) -#define PCIE2_RESET_PU_MASK BIT(10) -#define PCIE1_RESET_PU_MASK BIT(9) -#define PCIE0_RESET_PU_MASK BIT(8) -#define AN7583_MDIO_0_PU_MASK BIT(5) -#define AN7583_MDC_0_PU_MASK BIT(4) -#define UART1_RXD_PU_MASK BIT(3) -#define UART1_TXD_PU_MASK BIT(2) -#define I2C_SCL_PU_MASK BIT(1) -#define I2C_SDA_PU_MASK BIT(0) - -#define REG_I2C_SDA_PD 0x0048 -#define AN7583_I2C1_SDA_PD_MASK BIT(16) -#define AN7583_I2C1_SCL_PD_MASK BIT(15) -#define SPI_MISO_PD_MASK BIT(14) -#define SPI_MOSI_PD_MASK BIT(13) -#define SPI_CLK_PD_MASK BIT(12) -#define SPI_CS0_PD_MASK BIT(11) -#define PCIE2_RESET_PD_MASK BIT(10) -#define PCIE1_RESET_PD_MASK BIT(9) -#define PCIE0_RESET_PD_MASK BIT(8) -#define AN7583_MDIO_0_PD_MASK BIT(5) -#define AN7583_MDC_0_PD_MASK BIT(4) -#define UART1_RXD_PD_MASK BIT(3) -#define UART1_TXD_PD_MASK BIT(2) -#define I2C_SCL_PD_MASK BIT(1) -#define I2C_SDA_PD_MASK BIT(0) - -#define REG_GPIO_L_PU 0x004c -#define REG_GPIO_L_PD 0x0050 -#define REG_GPIO_H_PU 0x0054 -#define REG_GPIO_H_PD 0x0058 - -#define REG_PCIE_RESET_OD 0x018c -#define PCIE2_RESET_OD_MASK BIT(2) -#define PCIE1_RESET_OD_MASK BIT(1) -#define PCIE0_RESET_OD_MASK BIT(0) - -/* GPIOs */ -#define REG_GPIO_CTRL 0x0000 -#define REG_GPIO_DATA 0x0004 -#define REG_GPIO_INT 0x0008 -#define REG_GPIO_INT_EDGE 0x000c -#define REG_GPIO_INT_LEVEL 0x0010 -#define REG_GPIO_OE 0x0014 -#define REG_GPIO_CTRL1 0x0020 - -/* PWM MODE CONF */ -#define REG_GPIO_FLASH_MODE_CFG 0x0034 -#define GPIO15_FLASH_MODE_CFG BIT(15) -#define GPIO14_FLASH_MODE_CFG BIT(14) -#define GPIO13_FLASH_MODE_CFG BIT(13) -#define GPIO12_FLASH_MODE_CFG BIT(12) -#define GPIO11_FLASH_MODE_CFG BIT(11) -#define GPIO10_FLASH_MODE_CFG BIT(10) -#define GPIO9_FLASH_MODE_CFG BIT(9) -#define GPIO8_FLASH_MODE_CFG BIT(8) -#define GPIO7_FLASH_MODE_CFG BIT(7) -#define GPIO6_FLASH_MODE_CFG BIT(6) -#define GPIO5_FLASH_MODE_CFG BIT(5) -#define GPIO4_FLASH_MODE_CFG BIT(4) -#define GPIO3_FLASH_MODE_CFG BIT(3) -#define GPIO2_FLASH_MODE_CFG BIT(2) -#define GPIO1_FLASH_MODE_CFG BIT(1) -#define GPIO0_FLASH_MODE_CFG BIT(0) - -#define REG_GPIO_CTRL2 0x0060 -#define REG_GPIO_CTRL3 0x0064 - -/* PWM MODE CONF EXT */ -#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 -#define GPIO51_FLASH_MODE_CFG BIT(31) -#define GPIO50_FLASH_MODE_CFG BIT(30) -#define GPIO49_FLASH_MODE_CFG BIT(29) -#define GPIO48_FLASH_MODE_CFG BIT(28) -#define GPIO47_FLASH_MODE_CFG BIT(27) -#define GPIO46_FLASH_MODE_CFG BIT(26) -#define GPIO45_FLASH_MODE_CFG BIT(25) -#define GPIO44_FLASH_MODE_CFG BIT(24) -#define GPIO43_FLASH_MODE_CFG BIT(23) -#define GPIO42_FLASH_MODE_CFG BIT(22) -#define GPIO41_FLASH_MODE_CFG BIT(21) -#define GPIO40_FLASH_MODE_CFG BIT(20) -#define GPIO39_FLASH_MODE_CFG BIT(19) -#define GPIO38_FLASH_MODE_CFG BIT(18) -#define GPIO37_FLASH_MODE_CFG BIT(17) -#define GPIO36_FLASH_MODE_CFG BIT(16) -#define GPIO31_FLASH_MODE_CFG BIT(15) -#define GPIO30_FLASH_MODE_CFG BIT(14) -#define GPIO29_FLASH_MODE_CFG BIT(13) -#define GPIO28_FLASH_MODE_CFG BIT(12) -#define GPIO27_FLASH_MODE_CFG BIT(11) -#define GPIO26_FLASH_MODE_CFG BIT(10) -#define GPIO25_FLASH_MODE_CFG BIT(9) -#define GPIO24_FLASH_MODE_CFG BIT(8) -#define GPIO23_FLASH_MODE_CFG BIT(7) -#define GPIO22_FLASH_MODE_CFG BIT(6) -#define GPIO21_FLASH_MODE_CFG BIT(5) -#define GPIO20_FLASH_MODE_CFG BIT(4) -#define GPIO19_FLASH_MODE_CFG BIT(3) -#define GPIO18_FLASH_MODE_CFG BIT(2) -#define GPIO17_FLASH_MODE_CFG BIT(1) -#define GPIO16_FLASH_MODE_CFG BIT(0) - -#define REG_GPIO_DATA1 0x0070 -#define REG_GPIO_OE1 0x0078 -#define REG_GPIO_INT1 0x007c -#define REG_GPIO_INT_EDGE1 0x0080 -#define REG_GPIO_INT_EDGE2 0x0084 -#define REG_GPIO_INT_EDGE3 0x0088 -#define REG_GPIO_INT_LEVEL1 0x008c -#define REG_GPIO_INT_LEVEL2 0x0090 -#define REG_GPIO_INT_LEVEL3 0x0094 - -#define AIROHA_NUM_PINS 64 -#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) -#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) - -static const u32 gpio_data_regs[] = { - REG_GPIO_DATA, - REG_GPIO_DATA1 -}; - -static const u32 gpio_out_regs[] = { - REG_GPIO_OE, - REG_GPIO_OE1 -}; - -static const u32 gpio_dir_regs[] = { - REG_GPIO_CTRL, - REG_GPIO_CTRL1, - REG_GPIO_CTRL2, - REG_GPIO_CTRL3 -}; - -static const u32 irq_status_regs[] = { - REG_GPIO_INT, - REG_GPIO_INT1 -}; - -static const u32 irq_level_regs[] = { - REG_GPIO_INT_LEVEL, - REG_GPIO_INT_LEVEL1, - REG_GPIO_INT_LEVEL2, - REG_GPIO_INT_LEVEL3 -}; - -static const u32 irq_edge_regs[] = { - REG_GPIO_INT_EDGE, - REG_GPIO_INT_EDGE1, - REG_GPIO_INT_EDGE2, - REG_GPIO_INT_EDGE3 -}; - -struct airoha_pinctrl_reg { - u32 offset; - u32 mask; -}; - -enum airoha_pinctrl_mux_func { - AIROHA_FUNC_MUX, - AIROHA_FUNC_PWM_MUX, - AIROHA_FUNC_PWM_EXT_MUX, -}; - -struct airoha_pinctrl_func_group { - const char *name; - struct { - enum airoha_pinctrl_mux_func mux; - u32 offset; - u32 mask; - u32 val; - } regmap[2]; - int regmap_size; -}; - -struct airoha_pinctrl_func { - const struct pinfunction desc; - const struct airoha_pinctrl_func_group *groups; - u8 group_size; -}; - -struct airoha_pinctrl_conf { - u32 pin; - struct airoha_pinctrl_reg reg; -}; - -struct airoha_pinctrl_gpiochip { - struct gpio_chip chip; - - /* gpio */ - const u32 *data; - const u32 *dir; - const u32 *out; - /* irq */ - const u32 *status; - const u32 *level; - const u32 *edge; - - u32 irq_type[AIROHA_NUM_PINS]; -}; - -struct airoha_pinctrl_confs_info { - const struct airoha_pinctrl_conf *confs; - unsigned int num_confs; -}; - -enum airoha_pinctrl_confs_type { - AIROHA_PINCTRL_CONFS_PULLUP, - AIROHA_PINCTRL_CONFS_PULLDOWN, - AIROHA_PINCTRL_CONFS_DRIVE_E2, - AIROHA_PINCTRL_CONFS_DRIVE_E4, - AIROHA_PINCTRL_CONFS_PCIE_RST_OD, - - AIROHA_PINCTRL_CONFS_MAX, -}; - -struct airoha_pinctrl { - struct pinctrl_dev *ctrl; - - struct pinctrl_desc desc; - const struct pingroup *grps; - const struct airoha_pinctrl_func *funcs; - const struct airoha_pinctrl_confs_info *confs_info; - - struct regmap *chip_scu; - struct regmap *regmap; - - struct airoha_pinctrl_gpiochip gpiochip; -}; - -struct airoha_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - const unsigned int num_pins; - const struct pingroup *grps; - const unsigned int num_grps; - const struct airoha_pinctrl_func *funcs; - const unsigned int num_funcs; - const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; -}; - -static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { - PINCTRL_PIN(0, "uart1_txd"), - PINCTRL_PIN(1, "uart1_rxd"), - PINCTRL_PIN(2, "i2c_scl"), - PINCTRL_PIN(3, "i2c_sda"), - PINCTRL_PIN(4, "spi_cs0"), - PINCTRL_PIN(5, "spi_clk"), - PINCTRL_PIN(6, "spi_mosi"), - PINCTRL_PIN(7, "spi_miso"), - PINCTRL_PIN(13, "gpio0"), - PINCTRL_PIN(14, "gpio1"), - PINCTRL_PIN(15, "gpio2"), - PINCTRL_PIN(16, "gpio3"), - PINCTRL_PIN(17, "gpio4"), - PINCTRL_PIN(18, "gpio5"), - PINCTRL_PIN(19, "gpio6"), - PINCTRL_PIN(20, "gpio7"), - PINCTRL_PIN(21, "gpio8"), - PINCTRL_PIN(22, "gpio9"), - PINCTRL_PIN(23, "gpio10"), - PINCTRL_PIN(24, "gpio11"), - PINCTRL_PIN(25, "gpio12"), - PINCTRL_PIN(26, "gpio13"), - PINCTRL_PIN(27, "gpio14"), - PINCTRL_PIN(28, "gpio15"), - PINCTRL_PIN(29, "gpio16"), - PINCTRL_PIN(30, "gpio17"), - PINCTRL_PIN(31, "gpio18"), - PINCTRL_PIN(32, "gpio19"), - PINCTRL_PIN(33, "gpio20"), - PINCTRL_PIN(34, "gpio21"), - PINCTRL_PIN(35, "gpio22"), - PINCTRL_PIN(36, "gpio23"), - PINCTRL_PIN(37, "gpio24"), - PINCTRL_PIN(38, "gpio25"), - PINCTRL_PIN(39, "gpio26"), - PINCTRL_PIN(40, "gpio27"), - PINCTRL_PIN(41, "gpio28"), - PINCTRL_PIN(42, "gpio29"), - PINCTRL_PIN(43, "gpio30"), - PINCTRL_PIN(44, "gpio31"), - PINCTRL_PIN(45, "gpio32"), - PINCTRL_PIN(46, "gpio33"), - PINCTRL_PIN(47, "gpio34"), - PINCTRL_PIN(48, "gpio35"), - PINCTRL_PIN(49, "gpio36"), - PINCTRL_PIN(50, "gpio37"), - PINCTRL_PIN(51, "gpio38"), - PINCTRL_PIN(52, "gpio39"), - PINCTRL_PIN(53, "gpio40"), - PINCTRL_PIN(54, "gpio41"), - PINCTRL_PIN(55, "gpio42"), - PINCTRL_PIN(56, "gpio43"), - PINCTRL_PIN(57, "gpio44"), - PINCTRL_PIN(58, "gpio45"), - PINCTRL_PIN(59, "gpio46"), - PINCTRL_PIN(61, "pcie_reset0"), - PINCTRL_PIN(62, "pcie_reset1"), - PINCTRL_PIN(63, "pcie_reset2"), -}; - -static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 }; -static const int en7581_pon_tod_1pps_pins[] = { 46 }; -static const int en7581_gsw_tod_1pps_pins[] = { 46 }; -static const int en7581_sipo_pins[] = { 16, 17 }; -static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 }; -static const int en7581_mdio_pins[] = { 14, 15 }; -static const int en7581_uart2_pins[] = { 48, 55 }; -static const int en7581_uart2_cts_rts_pins[] = { 46, 47 }; -static const int en7581_hsuart_pins[] = { 28, 29 }; -static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 }; -static const int en7581_uart4_pins[] = { 38, 39 }; -static const int en7581_uart5_pins[] = { 18, 19 }; -static const int en7581_i2c0_pins[] = { 2, 3 }; -static const int en7581_i2c1_pins[] = { 14, 15 }; -static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; -static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; -static const int en7581_i2s_pins[] = { 26, 27, 28, 29 }; -static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 }; -static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 }; -static const int en7581_spi_quad_pins[] = { 32, 33 }; -static const int en7581_spi_pins[] = { 4, 5, 6, 7 }; -static const int en7581_spi_cs1_pins[] = { 34 }; -static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; -static const int en7581_pcm_spi_int_pins[] = { 14 }; -static const int en7581_pcm_spi_rst_pins[] = { 15 }; -static const int en7581_pcm_spi_cs1_pins[] = { 43 }; -static const int en7581_pcm_spi_cs2_pins[] = { 40 }; -static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 }; -static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 }; -static const int en7581_pcm_spi_cs3_pins[] = { 41 }; -static const int en7581_pcm_spi_cs4_pins[] = { 42 }; -static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 }; -static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 }; -static const int en7581_gpio0_pins[] = { 13 }; -static const int en7581_gpio1_pins[] = { 14 }; -static const int en7581_gpio2_pins[] = { 15 }; -static const int en7581_gpio3_pins[] = { 16 }; -static const int en7581_gpio4_pins[] = { 17 }; -static const int en7581_gpio5_pins[] = { 18 }; -static const int en7581_gpio6_pins[] = { 19 }; -static const int en7581_gpio7_pins[] = { 20 }; -static const int en7581_gpio8_pins[] = { 21 }; -static const int en7581_gpio9_pins[] = { 22 }; -static const int en7581_gpio10_pins[] = { 23 }; -static const int en7581_gpio11_pins[] = { 24 }; -static const int en7581_gpio12_pins[] = { 25 }; -static const int en7581_gpio13_pins[] = { 26 }; -static const int en7581_gpio14_pins[] = { 27 }; -static const int en7581_gpio15_pins[] = { 28 }; -static const int en7581_gpio16_pins[] = { 29 }; -static const int en7581_gpio17_pins[] = { 30 }; -static const int en7581_gpio18_pins[] = { 31 }; -static const int en7581_gpio19_pins[] = { 32 }; -static const int en7581_gpio20_pins[] = { 33 }; -static const int en7581_gpio21_pins[] = { 34 }; -static const int en7581_gpio22_pins[] = { 35 }; -static const int en7581_gpio23_pins[] = { 36 }; -static const int en7581_gpio24_pins[] = { 37 }; -static const int en7581_gpio25_pins[] = { 38 }; -static const int en7581_gpio26_pins[] = { 39 }; -static const int en7581_gpio27_pins[] = { 40 }; -static const int en7581_gpio28_pins[] = { 41 }; -static const int en7581_gpio29_pins[] = { 42 }; -static const int en7581_gpio30_pins[] = { 43 }; -static const int en7581_gpio31_pins[] = { 44 }; -static const int en7581_gpio33_pins[] = { 46 }; -static const int en7581_gpio34_pins[] = { 47 }; -static const int en7581_gpio35_pins[] = { 48 }; -static const int en7581_gpio36_pins[] = { 49 }; -static const int en7581_gpio37_pins[] = { 50 }; -static const int en7581_gpio38_pins[] = { 51 }; -static const int en7581_gpio39_pins[] = { 52 }; -static const int en7581_gpio40_pins[] = { 53 }; -static const int en7581_gpio41_pins[] = { 54 }; -static const int en7581_gpio42_pins[] = { 55 }; -static const int en7581_gpio43_pins[] = { 56 }; -static const int en7581_gpio44_pins[] = { 57 }; -static const int en7581_gpio45_pins[] = { 58 }; -static const int en7581_gpio46_pins[] = { 59 }; -static const int en7581_pcie_reset0_pins[] = { 61 }; -static const int en7581_pcie_reset1_pins[] = { 62 }; -static const int en7581_pcie_reset2_pins[] = { 63 }; - -static const struct pingroup en7581_pinctrl_groups[] = { - PINCTRL_PIN_GROUP("pon", en7581_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", en7581_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", en7581_mdio), - PINCTRL_PIN_GROUP("uart2", en7581_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), - PINCTRL_PIN_GROUP("uart4", en7581_uart4), - PINCTRL_PIN_GROUP("uart5", en7581_uart5), - PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), - PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), - PINCTRL_PIN_GROUP("i2s", en7581_i2s), - PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), - PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), - PINCTRL_PIN_GROUP("spi", en7581_spi), - PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), - PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), - PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), - PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), - PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), - PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), - PINCTRL_PIN_GROUP("emmc", en7581_emmc), - PINCTRL_PIN_GROUP("pnand", en7581_pnand), - PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), - PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), - PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), - PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), - PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), - PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), - PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), - PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), - PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), - PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), - PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), - PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), - PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), - PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), - PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), - PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), - PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), - PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), - PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), - PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), - PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), - PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), - PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), - PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), - PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), - PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), - PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), - PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), - PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), - PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), - PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), - PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), - PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), - PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), - PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), - PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), - PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), - PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), - PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), - PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), - PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), - PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), - PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), - PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), - PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), - PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), - PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), - PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), -}; - -static struct pinctrl_pin_desc an7583_pinctrl_pins[] = { - PINCTRL_PIN(2, "gpio0"), - PINCTRL_PIN(3, "gpio1"), - PINCTRL_PIN(4, "gpio2"), - PINCTRL_PIN(5, "gpio3"), - PINCTRL_PIN(6, "gpio4"), - PINCTRL_PIN(7, "gpio5"), - PINCTRL_PIN(8, "gpio6"), - PINCTRL_PIN(9, "gpio7"), - PINCTRL_PIN(10, "gpio8"), - PINCTRL_PIN(11, "gpio9"), - PINCTRL_PIN(12, "gpio10"), - PINCTRL_PIN(13, "gpio11"), - PINCTRL_PIN(14, "gpio12"), - PINCTRL_PIN(15, "gpio13"), - PINCTRL_PIN(16, "gpio14"), - PINCTRL_PIN(17, "gpio15"), - PINCTRL_PIN(18, "gpio16"), - PINCTRL_PIN(19, "gpio17"), - PINCTRL_PIN(20, "gpio18"), - PINCTRL_PIN(21, "gpio19"), - PINCTRL_PIN(22, "gpio20"), - PINCTRL_PIN(23, "gpio21"), - PINCTRL_PIN(24, "gpio22"), - PINCTRL_PIN(25, "gpio23"), - PINCTRL_PIN(26, "gpio24"), - PINCTRL_PIN(27, "gpio25"), - PINCTRL_PIN(28, "gpio26"), - PINCTRL_PIN(29, "gpio27"), - PINCTRL_PIN(30, "gpio28"), - PINCTRL_PIN(31, "gpio29"), - PINCTRL_PIN(32, "gpio30"), - PINCTRL_PIN(33, "gpio31"), - PINCTRL_PIN(34, "gpio32"), - PINCTRL_PIN(35, "gpio33"), - PINCTRL_PIN(36, "gpio34"), - PINCTRL_PIN(37, "gpio35"), - PINCTRL_PIN(38, "gpio36"), - PINCTRL_PIN(39, "gpio37"), - PINCTRL_PIN(40, "gpio38"), - PINCTRL_PIN(41, "i2c0_scl"), - PINCTRL_PIN(42, "i2c0_sda"), - PINCTRL_PIN(43, "i2c1_scl"), - PINCTRL_PIN(44, "i2c1_sda"), - PINCTRL_PIN(45, "spi_clk"), - PINCTRL_PIN(46, "spi_cs"), - PINCTRL_PIN(47, "spi_mosi"), - PINCTRL_PIN(48, "spi_miso"), - PINCTRL_PIN(49, "uart_txd"), - PINCTRL_PIN(50, "uart_rxd"), - PINCTRL_PIN(51, "pcie_reset0"), - PINCTRL_PIN(52, "pcie_reset1"), - PINCTRL_PIN(53, "mdc_0"), - PINCTRL_PIN(54, "mdio_0"), -}; - -static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 }; -static const int an7583_pon_tod_1pps_pins[] = { 32 }; -static const int an7583_gsw_tod_1pps_pins[] = { 32 }; -static const int an7583_sipo_pins[] = { 34, 35 }; -static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 }; -static const int an7583_mdio_pins[] = { 43, 44 }; -static const int an7583_uart2_pins[] = { 34, 35 }; -static const int an7583_uart2_cts_rts_pins[] = { 32, 33 }; -static const int an7583_hsuart_pins[] = { 30, 31 }; -static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 }; -static const int an7583_npu_uart_pins[] = { 7, 8 }; -static const int an7583_uart4_pins[] = { 7, 8 }; -static const int an7583_uart5_pins[] = { 23, 24 }; -static const int an7583_i2c0_pins[] = { 41, 42 }; -static const int an7583_i2c1_pins[] = { 43, 44 }; -static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; -static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; -static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 }; -static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 }; -static const int an7583_spi_pins[] = { 28, 29, 30, 31 }; -static const int an7583_spi_quad_pins[] = { 25, 26 }; -static const int an7583_spi_cs1_pins[] = { 27 }; -static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; -static const int an7583_pcm_spi_rst_pins[] = { 14 }; -static const int an7583_pcm_spi_cs1_pins[] = { 24 }; -static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 }; -static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 }; -static const int an7583_gpio0_pins[] = { 2 }; -static const int an7583_gpio1_pins[] = { 3 }; -static const int an7583_gpio2_pins[] = { 4 }; -static const int an7583_gpio3_pins[] = { 5 }; -static const int an7583_gpio4_pins[] = { 6 }; -static const int an7583_gpio5_pins[] = { 7 }; -static const int an7583_gpio6_pins[] = { 8 }; -static const int an7583_gpio7_pins[] = { 9 }; -static const int an7583_gpio8_pins[] = { 10 }; -static const int an7583_gpio9_pins[] = { 11 }; -static const int an7583_gpio10_pins[] = { 12 }; -static const int an7583_gpio11_pins[] = { 13 }; -static const int an7583_gpio12_pins[] = { 14 }; -static const int an7583_gpio13_pins[] = { 15 }; -static const int an7583_gpio14_pins[] = { 16 }; -static const int an7583_gpio15_pins[] = { 17 }; -static const int an7583_gpio16_pins[] = { 18 }; -static const int an7583_gpio17_pins[] = { 19 }; -static const int an7583_gpio18_pins[] = { 20 }; -static const int an7583_gpio19_pins[] = { 21 }; -static const int an7583_gpio20_pins[] = { 22 }; -static const int an7583_gpio21_pins[] = { 24 }; -static const int an7583_gpio23_pins[] = { 25 }; -static const int an7583_gpio24_pins[] = { 26 }; -static const int an7583_gpio25_pins[] = { 27 }; -static const int an7583_gpio26_pins[] = { 28 }; -static const int an7583_gpio27_pins[] = { 29 }; -static const int an7583_gpio28_pins[] = { 30 }; -static const int an7583_gpio29_pins[] = { 31 }; -static const int an7583_gpio30_pins[] = { 32 }; -static const int an7583_gpio31_pins[] = { 33 }; -static const int an7583_gpio33_pins[] = { 35 }; -static const int an7583_gpio34_pins[] = { 36 }; -static const int an7583_gpio35_pins[] = { 37 }; -static const int an7583_gpio36_pins[] = { 38 }; -static const int an7583_gpio37_pins[] = { 39 }; -static const int an7583_gpio38_pins[] = { 40 }; -static const int an7583_gpio39_pins[] = { 41 }; -static const int an7583_gpio40_pins[] = { 42 }; -static const int an7583_gpio41_pins[] = { 43 }; -static const int an7583_gpio42_pins[] = { 44 }; -static const int an7583_gpio43_pins[] = { 45 }; -static const int an7583_gpio44_pins[] = { 46 }; -static const int an7583_gpio45_pins[] = { 47 }; -static const int an7583_gpio46_pins[] = { 48 }; -static const int an7583_gpio47_pins[] = { 49 }; -static const int an7583_gpio48_pins[] = { 50 }; -static const int an7583_pcie_reset0_pins[] = { 51 }; -static const int an7583_pcie_reset1_pins[] = { 52 }; - -static const struct pingroup an7583_pinctrl_groups[] = { - PINCTRL_PIN_GROUP("pon", an7583_pon), - PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), - PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), - PINCTRL_PIN_GROUP("sipo", an7583_sipo), - PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), - PINCTRL_PIN_GROUP("mdio", an7583_mdio), - PINCTRL_PIN_GROUP("uart2", an7583_uart2), - PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), - PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), - PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), - PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), - PINCTRL_PIN_GROUP("uart4", an7583_uart4), - PINCTRL_PIN_GROUP("uart5", an7583_uart5), - PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), - PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), - PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), - PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), - PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), - PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), - PINCTRL_PIN_GROUP("spi", an7583_spi), - PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), - PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), - PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), - PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), - PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), - PINCTRL_PIN_GROUP("emmc", an7583_emmc), - PINCTRL_PIN_GROUP("pnand", an7583_pnand), - PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), - PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), - PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), - PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), - PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), - PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), - PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), - PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), - PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), - PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), - PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), - PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), - PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), - PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), - PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), - PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), - PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), - PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), - PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), - PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), - PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), - PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), - PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), - PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), - PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), - PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), - PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), - PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), - PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), - PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), - PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), - PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), - PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), - PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), - PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), - PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), - PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), - PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), - PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), - PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), - PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), - PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), - PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), - PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), - PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), - PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), - PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), - PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), - PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), -}; - -static const char *const pon_groups[] = { "pon" }; -static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; -static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; -static const char *const mdio_groups[] = { "mdio" }; -static const char *const an7583_mdio_groups[] = { "mdio" }; -static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", - "hsuart_cts_rts", "uart4", - "uart5" }; -static const char *const i2c_groups[] = { "i2c1" }; -static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; -static const char *const pcm_groups[] = { "pcm1", "pcm2" }; -static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; -static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", - "pcm_spi_rst", "pcm_spi_cs1", - "pcm_spi_cs2_p156", - "pcm_spi_cs2_p128", - "pcm_spi_cs3", "pcm_spi_cs4" }; -static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", - "pcm_spi_rst", "pcm_spi_cs1", - "pcm_spi_cs2", "pcm_spi_cs3", - "pcm_spi_cs4" }; -static const char *const i2s_groups[] = { "i2s" }; -static const char *const emmc_groups[] = { "emmc" }; -static const char *const pnand_groups[] = { "pnand" }; -static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1", - "pcie_reset2" }; -static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" }; -static const char *const pwm_groups[] = { "gpio0", "gpio1", - "gpio2", "gpio3", - "gpio4", "gpio5", - "gpio6", "gpio7", - "gpio8", "gpio9", - "gpio10", "gpio11", - "gpio12", "gpio13", - "gpio14", "gpio15", - "gpio16", "gpio17", - "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio22", "gpio23", - "gpio24", "gpio25", - "gpio26", "gpio27", - "gpio28", "gpio29", - "gpio30", "gpio31", - "gpio36", "gpio37", - "gpio38", "gpio39", - "gpio40", "gpio41", - "gpio42", "gpio43", - "gpio44", "gpio45", - "gpio46", "gpio47" }; -static const char *const phy1_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy2_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy3_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy4_led0_groups[] = { "gpio33", "gpio34", - "gpio35", "gpio42" }; -static const char *const phy1_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy2_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy3_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const phy4_led1_groups[] = { "gpio43", "gpio44", - "gpio45", "gpio46" }; -static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2", - "gpio3", "gpio4" }; -static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; -static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9", - "gpio10", "gpio11" }; - -static const struct airoha_pinctrl_func_group pon_func_group[] = { - { - .name = "pon", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PON_MODE_MASK, - GPIO_PON_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { - { - .name = "pon_tod_1pps", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - PON_TOD_1PPS_MODE_MASK, - PON_TOD_1PPS_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "gsw_tod_1pps", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GSW_TOD_1PPS_MODE_MASK, - GSW_TOD_1PPS_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group sipo_func_group[] = { - { - .name = "sipo", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, - GPIO_SIPO_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "sipo_rclk", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, - GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group mdio_func_group[] = { - { - .name = "mdio", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_FORCE_GPIO_EN, - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), - FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) - }, - .regmap_size = 2, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { - { - .name = "mdio", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_SGMII_MDIO_MODE_MASK, - GPIO_SGMII_MDIO_MODE_MASK - }, - .regmap[1] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE, - GPIO_MDC_IO_MASTER_MODE_MODE - }, - .regmap_size = 2, - }, -}; - -static const struct airoha_pinctrl_func_group uart_func_group[] = { - { - .name = "uart2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART2_MODE_MASK, - GPIO_UART2_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "uart2_cts_rts", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, - GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "hsuart", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, - GPIO_HSUART_MODE_MASK - }, - .regmap_size = 1, - }, - { - .name = "hsuart_cts_rts", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, - GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "uart4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART4_MODE_MASK, - GPIO_UART4_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "uart5", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_UART5_MODE_MASK, - GPIO_UART5_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group i2c_func_group[] = { - { - .name = "i2c1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_2ND_I2C_MODE_MASK, - GPIO_2ND_I2C_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group jtag_func_group[] = { - { - .name = "jtag_udi", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_NPU_UART_EN, - JTAG_UDI_EN_MASK, - JTAG_UDI_EN_MASK - }, - .regmap_size = 1, - }, { - .name = "jtag_dfd", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_NPU_UART_EN, - JTAG_DFD_EN_MASK, - JTAG_DFD_EN_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcm_func_group[] = { - { - .name = "pcm1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM1_MODE_MASK, - GPIO_PCM1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM2_MODE_MASK, - GPIO_PCM2_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group spi_func_group[] = { - { - .name = "spi_quad", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_QUAD_MODE_MASK, - GPIO_SPI_QUAD_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS1_MODE_MASK, - GPIO_SPI_CS1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS2_MODE_MASK, - GPIO_SPI_CS2_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs3", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS3_MODE_MASK, - GPIO_SPI_CS3_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "spi_cs4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_SPI_CS4_MODE_MASK, - GPIO_SPI_CS4_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { - { - .name = "pcm_spi", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_MODE_MASK, - GPIO_PCM_SPI_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_int", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_INT_MODE_MASK, - GPIO_PCM_INT_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_rst", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_RESET_MODE_MASK, - GPIO_PCM_RESET_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS1_MODE_MASK, - GPIO_PCM_SPI_CS1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs2_p128", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS2_MODE_P128_MASK, - GPIO_PCM_SPI_CS2_MODE_P128_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs2_p156", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS2_MODE_P156_MASK, - GPIO_PCM_SPI_CS2_MODE_P156_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs3", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS3_MODE_MASK, - GPIO_PCM_SPI_CS3_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS4_MODE_MASK, - GPIO_PCM_SPI_CS4_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = { - { - .name = "pcm_spi", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_MODE_MASK, - GPIO_PCM_SPI_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_int", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_INT_MODE_MASK, - GPIO_PCM_INT_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_rst", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_RESET_MODE_MASK, - GPIO_PCM_RESET_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS1_MODE_MASK, - GPIO_PCM_SPI_CS1_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, - AN7583_GPIO_PCM_SPI_CS2_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs3", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS3_MODE_MASK, - GPIO_PCM_SPI_CS3_MODE_MASK - }, - .regmap_size = 1, - }, { - .name = "pcm_spi_cs4", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_SPI_CS1_MODE, - GPIO_PCM_SPI_CS4_MODE_MASK, - GPIO_PCM_SPI_CS4_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group i2s_func_group[] = { - { - .name = "i2s", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_2ND_I2C_MODE, - GPIO_I2S_MODE_MASK, - GPIO_I2S_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group emmc_func_group[] = { - { - .name = "emmc", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_EMMC_MODE_MASK, - GPIO_EMMC_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pnand_func_group[] = { - { - .name = "pnand", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PARALLEL_NAND_MODE_MASK, - GPIO_PARALLEL_NAND_MODE_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { - { - .name = "pcie_reset0", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET0_MASK, - GPIO_PCIE_RESET0_MASK - }, - .regmap_size = 1, - }, { - .name = "pcie_reset1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET1_MASK, - GPIO_PCIE_RESET1_MASK - }, - .regmap_size = 1, - }, { - .name = "pcie_reset2", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET2_MASK, - GPIO_PCIE_RESET2_MASK - }, - .regmap_size = 1, - }, -}; - -static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { - { - .name = "pcie_reset0", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET0_MASK, - GPIO_PCIE_RESET0_MASK - }, - .regmap_size = 1, - }, { - .name = "pcie_reset1", - .regmap[0] = { - AIROHA_FUNC_MUX, - REG_GPIO_PON_MODE, - GPIO_PCIE_RESET1_MASK, - GPIO_PCIE_RESET1_MASK - }, - .regmap_size = 1, - }, -}; - -/* PWM */ -#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_MUX, \ - REG_GPIO_FLASH_MODE_CFG, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } \ - -#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_PWM_EXT_MUX, \ - REG_GPIO_FLASH_MODE_CFG_EXT, \ - (mux_val), \ - (mux_val) \ - }, \ - .regmap_size = 1, \ - } \ - -static const struct airoha_pinctrl_func_group pwm_func_group[] = { - AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), - AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG), -}; - -#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED0_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size = 2, \ - } - -#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ - { \ - .name = (gpio), \ - .regmap[0] = { \ - AIROHA_FUNC_MUX, \ - REG_GPIO_2ND_I2C_MODE, \ - (mux_val), \ - (mux_val), \ - }, \ - .regmap[1] = { \ - AIROHA_FUNC_MUX, \ - REG_LAN_LED1_MAPPING, \ - (map_mask), \ - (map_val), \ - }, \ - .regmap_size = 2, \ - } - -static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = { - AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), - AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), - AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = { - AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, - LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, - LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, - LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), - AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, - LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), -}; - -static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { - PINCTRL_FUNC_DESC("pon", pon), - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), - PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", mdio), - PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", i2c), - PINCTRL_FUNC_DESC("jtag", jtag), - PINCTRL_FUNC_DESC("pcm", pcm), - PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), - PINCTRL_FUNC_DESC("i2s", i2s), - PINCTRL_FUNC_DESC("emmc", emmc), - PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), - PINCTRL_FUNC_DESC("pwm", pwm), - PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), -}; - -static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { - PINCTRL_FUNC_DESC("pon", pon), - PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), - PINCTRL_FUNC_DESC("sipo", sipo), - PINCTRL_FUNC_DESC("mdio", an7583_mdio), - PINCTRL_FUNC_DESC("uart", uart), - PINCTRL_FUNC_DESC("i2c", i2c), - PINCTRL_FUNC_DESC("jtag", jtag), - PINCTRL_FUNC_DESC("pcm", pcm), - PINCTRL_FUNC_DESC("spi", spi), - PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), - PINCTRL_FUNC_DESC("emmc", emmc), - PINCTRL_FUNC_DESC("pnand", pnand), - PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), - PINCTRL_FUNC_DESC("pwm", pwm), - PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), - PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), - PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), - PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), - PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), - PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), - PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), - PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { - PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), - PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), - PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), - PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), - PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), - PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), - PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), - PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), - PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), - PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), - PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), - PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), - PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), - PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), - PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), - PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), - PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), - PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), - PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), - PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), - PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), - PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), - PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), - PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), - PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), - PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), - PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), - PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), - PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), - PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), - PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), - PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), - PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), - PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), - PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { - PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), - PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), - PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), - PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), - PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), - PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), - PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), - PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), - PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), - PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), - PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), - PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), - PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), - PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), - PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), - PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), - PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), - PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), - PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)), - PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), - PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), - PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), - PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), - PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), - PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), - PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), - PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), - PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), - PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), - PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), - PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), - PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), - PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), - PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), - PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), - PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), - PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), - PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), - PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), - PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), - PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), - PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), - PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), - PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), - PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), - PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), - PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), - PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), - PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), - PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), - PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), - PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), -}; - -static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { - PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), - PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), - PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), -}; - -static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = { - PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), - PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), -}; - -static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, - struct pinctrl_gpio_range *range, - int pin) -{ - if (!range) - range = pinctrl_find_gpio_range_from_pin_nolock(pctrl_dev, - pin); - if (!range) - return -EINVAL; - - return pin - range->pin_base; -} - -/* gpio callbacks */ -static int airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio, - int value) -{ - struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); - u32 offset = gpio % AIROHA_PIN_BANK_SIZE; - u8 index = gpio / AIROHA_PIN_BANK_SIZE; - - return regmap_update_bits(pinctrl->regmap, - pinctrl->gpiochip.data[index], - BIT(offset), value ? BIT(offset) : 0); -} - -static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio) -{ - struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); - u32 val, pin = gpio % AIROHA_PIN_BANK_SIZE; - u8 index = gpio / AIROHA_PIN_BANK_SIZE; - int err; - - err = regmap_read(pinctrl->regmap, - pinctrl->gpiochip.data[index], &val); - - return err ? err : !!(val & BIT(pin)); -} - -static int airoha_gpio_direction_output(struct gpio_chip *chip, - unsigned int gpio, int value) -{ - int err; - - err = pinctrl_gpio_direction_output(chip, gpio); - if (err) - return err; - - return airoha_gpio_set(chip, gpio, value); -} - -/* irq callbacks */ -static void airoha_irq_unmask(struct irq_data *data) -{ - u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; - u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; - u32 mask = GENMASK(2 * offset + 1, 2 * offset); - struct airoha_pinctrl_gpiochip *gpiochip; - struct airoha_pinctrl *pinctrl; - u32 val = BIT(2 * offset); - - gpiochip = irq_data_get_irq_chip_data(data); - if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))) - return; - - pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); - switch (gpiochip->irq_type[data->hwirq]) { - case IRQ_TYPE_LEVEL_LOW: - val = val << 1; - fallthrough; - case IRQ_TYPE_LEVEL_HIGH: - regmap_update_bits(pinctrl->regmap, gpiochip->level[index], - mask, val); - break; - case IRQ_TYPE_EDGE_FALLING: - val = val << 1; - fallthrough; - case IRQ_TYPE_EDGE_RISING: - regmap_update_bits(pinctrl->regmap, gpiochip->edge[index], - mask, val); - break; - case IRQ_TYPE_EDGE_BOTH: - regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask); - break; - default: - break; - } -} - -static void airoha_irq_mask(struct irq_data *data) -{ - u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; - u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; - u32 mask = GENMASK(2 * offset + 1, 2 * offset); - struct airoha_pinctrl_gpiochip *gpiochip; - struct airoha_pinctrl *pinctrl; - - gpiochip = irq_data_get_irq_chip_data(data); - pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); - - regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); - regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask); -} - -static int airoha_irq_type(struct irq_data *data, unsigned int type) -{ - struct airoha_pinctrl_gpiochip *gpiochip; - - gpiochip = irq_data_get_irq_chip_data(data); - if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) - return -EINVAL; - - if (type == IRQ_TYPE_PROBE) { - if (gpiochip->irq_type[data->hwirq]) - return 0; - - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - } - gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK; - - return 0; -} - -static irqreturn_t airoha_irq_handler(int irq, void *data) -{ - struct airoha_pinctrl *pinctrl = data; - bool handled = false; - int i; - - for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) { - struct gpio_irq_chip *girq = &pinctrl->gpiochip.chip.irq; - u32 regmap; - unsigned long status; - int irq; - - if (regmap_read(pinctrl->regmap, pinctrl->gpiochip.status[i], - ®map)) - continue; - - status = regmap; - for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) { - u32 offset = irq + i * AIROHA_PIN_BANK_SIZE; - - generic_handle_irq(irq_find_mapping(girq->domain, - offset)); - regmap_write(pinctrl->regmap, - pinctrl->gpiochip.status[i], BIT(irq)); - } - handled |= !!status; - } - - return handled ? IRQ_HANDLED : IRQ_NONE; -} - -static const struct irq_chip airoha_gpio_irq_chip = { - .name = "airoha-gpio-irq", - .irq_unmask = airoha_irq_unmask, - .irq_mask = airoha_irq_mask, - .irq_mask_ack = airoha_irq_mask, - .irq_set_type = airoha_irq_type, - .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, -}; - -static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, - struct platform_device *pdev) -{ - struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip; - struct gpio_chip *gc = &chip->chip; - struct gpio_irq_chip *girq = &gc->irq; - struct device *dev = &pdev->dev; - int irq, err; - - chip->data = gpio_data_regs; - chip->dir = gpio_dir_regs; - chip->out = gpio_out_regs; - chip->status = irq_status_regs; - chip->level = irq_level_regs; - chip->edge = irq_edge_regs; - - gc->parent = dev; - gc->label = dev_name(dev); - gc->request = gpiochip_generic_request; - gc->free = gpiochip_generic_free; - gc->direction_input = pinctrl_gpio_direction_input; - gc->direction_output = airoha_gpio_direction_output; - gc->set = airoha_gpio_set; - gc->get = airoha_gpio_get; - gc->base = -1; - gc->ngpio = AIROHA_NUM_PINS; - - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_simple_irq; - gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip); - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED, - dev_name(dev), pinctrl); - if (err) { - dev_err(dev, "error requesting irq %d: %d\n", irq, err); - return err; - } - - return devm_gpiochip_add_data(dev, gc, pinctrl); -} - -/* pinmux callbacks */ -static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, - unsigned int selector, - unsigned int group) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - const struct airoha_pinctrl_func *func; - const struct function_desc *desc; - struct group_desc *grp; - int i; - - desc = pinmux_generic_get_function(pctrl_dev, selector); - if (!desc) - return -EINVAL; - - grp = pinctrl_generic_get_group(pctrl_dev, group); - if (!grp) - return -EINVAL; - - dev_dbg(pctrl_dev->dev, "enable function %s group %s\n", - desc->func->name, grp->grp.name); - - func = desc->data; - for (i = 0; i < func->group_size; i++) { - const struct airoha_pinctrl_func_group *group; - int j; - - group = &func->groups[i]; - if (strcmp(group->name, grp->grp.name)) - continue; - - for (j = 0; j < group->regmap_size; j++) { - switch (group->regmap[j].mux) { - case AIROHA_FUNC_PWM_EXT_MUX: - case AIROHA_FUNC_PWM_MUX: - regmap_update_bits(pinctrl->regmap, - group->regmap[j].offset, - group->regmap[j].mask, - group->regmap[j].val); - break; - default: - regmap_update_bits(pinctrl->chip_scu, - group->regmap[j].offset, - group->regmap[j].mask, - group->regmap[j].val); - break; - } - } - return 0; - } - - return -EINVAL; -} - -static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev, - struct pinctrl_gpio_range *range, - unsigned int p, bool input) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - u32 mask, index; - int err, pin; - - pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p); - if (pin < 0) - return pin; - - /* set output enable */ - mask = BIT(pin % AIROHA_PIN_BANK_SIZE); - index = pin / AIROHA_PIN_BANK_SIZE; - err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index], - mask, !input ? mask : 0); - if (err) - return err; - - /* set direction */ - mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); - index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; - return regmap_update_bits(pinctrl->regmap, - pinctrl->gpiochip.dir[index], mask, - !input ? mask : 0); -} - -static const struct pinmux_ops airoha_pmxops = { - .get_functions_count = pinmux_generic_get_function_count, - .get_function_name = pinmux_generic_get_function_name, - .get_function_groups = pinmux_generic_get_function_groups, - .gpio_set_direction = airoha_pinmux_set_direction, - .set_mux = airoha_pinmux_set_mux, - .strict = true, -}; - -/* pinconf callbacks */ -static const struct airoha_pinctrl_reg * -airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf, - int conf_size, int pin) -{ - int i; - - for (i = 0; i < conf_size; i++) { - if (conf[i].pin == pin) - return &conf[i].reg; - } - - return NULL; -} - -static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, - enum airoha_pinctrl_confs_type conf_type, - int pin, u32 *val) -{ - const struct airoha_pinctrl_confs_info *confs_info; - const struct airoha_pinctrl_reg *reg; - - confs_info = &pinctrl->confs_info[conf_type]; - - reg = airoha_pinctrl_get_conf_reg(confs_info->confs, - confs_info->num_confs, - pin); - if (!reg) - return -EINVAL; - - if (regmap_read(pinctrl->chip_scu, reg->offset, val)) - return -EINVAL; - - *val = (*val & reg->mask) >> __ffs(reg->mask); - - return 0; -} - -static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, - enum airoha_pinctrl_confs_type conf_type, - int pin, u32 val) -{ - const struct airoha_pinctrl_confs_info *confs_info; - const struct airoha_pinctrl_reg *reg = NULL; - - confs_info = &pinctrl->confs_info[conf_type]; - - reg = airoha_pinctrl_get_conf_reg(confs_info->confs, - confs_info->num_confs, - pin); - if (!reg) - return -EINVAL; - - - if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask, - val << __ffs(reg->mask))) - return -EINVAL; - - return 0; -} - -#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ - (pin), (val)) -#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ - (pin), (val)) -#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ - (pin), (val)) -#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ - (pin), (val)) -#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ - airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ - (pin), (val)) -#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ - (pin), (val)) -#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ - (pin), (val)) -#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ - (pin), (val)) -#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ - (pin), (val)) -#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ - airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ - (pin), (val)) - -static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - u32 val, mask; - int err, pin; - u8 index; - - pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); - if (pin < 0) - return pin; - - index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; - err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val); - if (err) - return err; - - mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); - return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE; -} - -static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev, - unsigned int pin, unsigned long *config) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - enum pin_config_param param = pinconf_to_config_param(*config); - u32 arg; - - switch (param) { - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_UP: { - u32 pull_up, pull_down; - - if (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) || - airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down)) - return -EINVAL; - - if (param == PIN_CONFIG_BIAS_PULL_UP && - !(pull_up && !pull_down)) - return -EINVAL; - else if (param == PIN_CONFIG_BIAS_PULL_DOWN && - !(pull_down && !pull_up)) - return -EINVAL; - else if (pull_up || pull_down) - return -EINVAL; - - arg = 1; - break; - } - case PIN_CONFIG_DRIVE_STRENGTH: { - u32 e2, e4; - - if (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) || - airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4)) - return -EINVAL; - - arg = e4 << 1 | e2; - break; - } - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg)) - return -EINVAL; - break; - case PIN_CONFIG_OUTPUT_ENABLE: - case PIN_CONFIG_INPUT_ENABLE: - arg = airoha_pinconf_get_direction(pctrl_dev, pin); - if (arg != param) - return -EINVAL; - - arg = 1; - break; - default: - return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev, - unsigned int p, bool value) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - int pin; - - pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); - if (pin < 0) - return pin; - - return airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value); -} - -static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, - unsigned int pin, unsigned long *configs, - unsigned int num_configs) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - int i; - - for (i = 0; i < num_configs; i++) { - u32 param = pinconf_to_config_param(configs[i]); - u32 arg = pinconf_to_config_argument(configs[i]); - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); - airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); - break; - case PIN_CONFIG_BIAS_PULL_UP: - airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); - airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1); - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1); - airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); - break; - case PIN_CONFIG_DRIVE_STRENGTH: { - u32 e2 = 0, e4 = 0; - - switch (arg) { - case MTK_DRIVE_2mA: - break; - case MTK_DRIVE_4mA: - e2 = 1; - break; - case MTK_DRIVE_6mA: - e4 = 1; - break; - case MTK_DRIVE_8mA: - e2 = 1; - e4 = 1; - break; - default: - return -EINVAL; - } - - airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2); - airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4); - break; - } - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg); - break; - case PIN_CONFIG_OUTPUT_ENABLE: - case PIN_CONFIG_INPUT_ENABLE: - case PIN_CONFIG_LEVEL: { - bool input = param == PIN_CONFIG_INPUT_ENABLE; - int err; - - err = airoha_pinmux_set_direction(pctrl_dev, NULL, pin, - input); - if (err) - return err; - - if (param == PIN_CONFIG_LEVEL) { - err = airoha_pinconf_set_pin_value(pctrl_dev, - pin, !!arg); - if (err) - return err; - } - break; - } - default: - return -ENOTSUPP; - } - } - - return 0; -} - -static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev, - unsigned int group, unsigned long *config) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - u32 cur_config = 0; - int i; - - for (i = 0; i < pinctrl->grps[group].npins; i++) { - if (airoha_pinconf_get(pctrl_dev, - pinctrl->grps[group].pins[i], - config)) - return -ENOTSUPP; - - if (i && cur_config != *config) - return -ENOTSUPP; - - cur_config = *config; - } - - return 0; -} - -static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev, - unsigned int group, unsigned long *configs, - unsigned int num_configs) -{ - struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); - int i; - - for (i = 0; i < pinctrl->grps[group].npins; i++) { - int err; - - err = airoha_pinconf_set(pctrl_dev, - pinctrl->grps[group].pins[i], - configs, num_configs); - if (err) - return err; - } - - return 0; -} - -static const struct pinconf_ops airoha_confops = { - .is_generic = true, - .pin_config_get = airoha_pinconf_get, - .pin_config_set = airoha_pinconf_set, - .pin_config_group_get = airoha_pinconf_group_get, - .pin_config_group_set = airoha_pinconf_group_set, - .pin_config_config_dbg_show = pinconf_generic_dump_config, -}; - -static const struct pinctrl_ops airoha_pctlops = { - .get_groups_count = pinctrl_generic_get_group_count, - .get_group_name = pinctrl_generic_get_group_name, - .get_group_pins = pinctrl_generic_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map_all, - .dt_free_map = pinconf_generic_dt_free_map, -}; - -static int airoha_pinctrl_probe(struct platform_device *pdev) -{ - const struct airoha_pinctrl_match_data *data; - struct device *dev = &pdev->dev; - struct airoha_pinctrl *pinctrl; - struct regmap *map; - int err, i; - - data = device_get_match_data(dev); - - pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL); - if (!pinctrl) - return -ENOMEM; - - pinctrl->regmap = device_node_to_regmap(dev->parent->of_node); - if (IS_ERR(pinctrl->regmap)) - return PTR_ERR(pinctrl->regmap); - - map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); - if (IS_ERR(map)) - return PTR_ERR(map); - - pinctrl->chip_scu = map; - - /* Init pinctrl desc struct */ - pinctrl->desc.name = KBUILD_MODNAME; - pinctrl->desc.owner = THIS_MODULE; - pinctrl->desc.pctlops = &airoha_pctlops; - pinctrl->desc.pmxops = &airoha_pmxops; - pinctrl->desc.confops = &airoha_confops; - pinctrl->desc.pins = data->pins; - pinctrl->desc.npins = data->num_pins; - - err = devm_pinctrl_register_and_init(dev, &pinctrl->desc, - pinctrl, &pinctrl->ctrl); - if (err) - return err; - - /* build pin groups */ - for (i = 0; i < data->num_grps; i++) { - const struct pingroup *grp = &data->grps[i]; - - err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name, - grp->pins, grp->npins, - (void *)grp); - if (err < 0) { - dev_err(&pdev->dev, "Failed to register group %s\n", - grp->name); - return err; - } - } - - /* build functions */ - for (i = 0; i < data->num_funcs; i++) { - const struct airoha_pinctrl_func *func; - - func = &data->funcs[i]; - err = pinmux_generic_add_pinfunction(pinctrl->ctrl, - &func->desc, - (void *)func); - if (err < 0) { - dev_err(dev, "Failed to register function %s\n", - func->desc.name); - return err; - } - } - - pinctrl->grps = data->grps; - pinctrl->funcs = data->funcs; - pinctrl->confs_info = data->confs_info; - - err = pinctrl_enable(pinctrl->ctrl); - if (err) - return err; - - /* build gpio-chip */ - return airoha_pinctrl_add_gpiochip(pinctrl, pdev); -} - -static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = { - .pins = en7581_pinctrl_pins, - .num_pins = ARRAY_SIZE(en7581_pinctrl_pins), - .grps = en7581_pinctrl_groups, - .num_grps = ARRAY_SIZE(en7581_pinctrl_groups), - .funcs = en7581_pinctrl_funcs, - .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs), - .confs_info = { - [AIROHA_PINCTRL_CONFS_PULLUP] = { - .confs = en7581_pinctrl_pullup_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf), - }, - [AIROHA_PINCTRL_CONFS_PULLDOWN] = { - .confs = en7581_pinctrl_pulldown_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { - .confs = en7581_pinctrl_drive_e2_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { - .confs = en7581_pinctrl_drive_e4_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), - }, - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { - .confs = en7581_pinctrl_pcie_rst_od_conf, - .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), - }, - }, -}; - -static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = { - .pins = an7583_pinctrl_pins, - .num_pins = ARRAY_SIZE(an7583_pinctrl_pins), - .grps = an7583_pinctrl_groups, - .num_grps = ARRAY_SIZE(an7583_pinctrl_groups), - .funcs = an7583_pinctrl_funcs, - .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs), - .confs_info = { - [AIROHA_PINCTRL_CONFS_PULLUP] = { - .confs = an7583_pinctrl_pullup_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf), - }, - [AIROHA_PINCTRL_CONFS_PULLDOWN] = { - .confs = an7583_pinctrl_pulldown_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { - .confs = an7583_pinctrl_drive_e2_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), - }, - [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { - .confs = an7583_pinctrl_drive_e4_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), - }, - [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { - .confs = an7583_pinctrl_pcie_rst_od_conf, - .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), - }, - }, -}; - -static const struct of_device_id airoha_pinctrl_of_match[] = { - { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data }, - { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); - -static struct platform_driver airoha_pinctrl_driver = { - .probe = airoha_pinctrl_probe, - .driver = { - .name = "pinctrl-airoha", - .of_match_table = airoha_pinctrl_of_match, - }, -}; -module_platform_driver(airoha_pinctrl_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); -MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); -MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); -MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC"); diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 70f608347a5f..fdfbe007b84f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -10,6 +10,7 @@ #include <dt-bindings/pinctrl/mt65xx.h> #include <linux/gpio/driver.h> +#include <linux/module.h> #include <linux/pinctrl/consumer.h> @@ -402,7 +403,8 @@ static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { const unsigned int *pins; - unsigned int i, npins, old = 0; + unsigned int i, npins; + unsigned long old = 0; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); @@ -520,6 +522,23 @@ static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, return pinctrl_gpio_direction_output(chip, gpio); } +static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct mtk_pinctrl *hw = gpiochip_get_data(chip); + const struct mtk_pin_desc *desc; + int ret, dir; + + desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; + if (!desc->name) + return -ENOTSUPP; + + ret = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &dir); + if (ret) + return ret; + + return dir ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) { struct mtk_pinctrl *hw = gpiochip_get_data(chip); @@ -566,6 +585,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->parent = hw->dev; chip->request = gpiochip_generic_request; chip->free = gpiochip_generic_free; + chip->get_direction = mtk_gpio_get_direction; chip->direction_input = pinctrl_gpio_direction_input; chip->direction_output = mtk_gpio_direction_output; chip->get = mtk_gpio_get; @@ -575,7 +595,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->base = -1; chip->ngpio = hw->soc->npins; - ret = gpiochip_add_data(chip, hw); + ret = devm_gpiochip_add_data(hw->dev, chip, hw); if (ret < 0) return ret; @@ -589,10 +609,8 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) if (!of_property_present(hw->dev->of_node, "gpio-ranges")) { ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, chip->ngpio); - if (ret < 0) { - gpiochip_remove(chip); + if (ret < 0) return ret; - } } return 0; @@ -726,3 +744,7 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_moore_pinctrl_probe, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Moore"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 6b1c7122b0fb..9e04f5b7cbba 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -542,3 +542,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT2701 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index bb7394ae252b..c7df168c314d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -591,3 +591,7 @@ static int __init mtk_pinctrl_init(void) } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT2712 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index 03d0f65d7bcc..13cee2a209c2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -49,6 +49,7 @@ static const struct of_device_id mt6397_pctrl_match[] = { { .compatible = "mediatek,mt6397-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, mt6397_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt6397_pinctrl_probe, @@ -59,3 +60,7 @@ static struct platform_driver mtk_pinctrl_driver = { }; builtin_platform_driver(mtk_pinctrl_driver); + +MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6795.c b/drivers/pinctrl/mediatek/pinctrl-mt6795.c index ee3ae3d2fa7e..82df5cafc3d3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6795.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6795.c @@ -607,6 +607,7 @@ static const struct of_device_id mt6795_pctrl_match[] = { { .compatible = "mediatek,mt6795-pinctrl", .data = &mt6795_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6795_pctrl_match); static struct platform_driver mt6795_pinctrl_driver = { .driver = { @@ -622,3 +623,6 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mt6795_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6795 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c index 53f240491259..6d4a5b16035f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6797.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -61,6 +61,7 @@ static const struct of_device_id mt6797_pinctrl_of_match[] = { { .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6797_pinctrl_of_match); static struct platform_driver mt6797_pinctrl_driver = { .driver = { @@ -75,3 +76,6 @@ static int __init mt6797_pinctrl_init(void) return platform_driver_register(&mt6797_pinctrl_driver); } arch_initcall(mt6797_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6797 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6858.c b/drivers/pinctrl/mediatek/pinctrl-mt6858.c new file mode 100644 index 000000000000..996b826e00d0 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6858.c @@ -0,0 +1,1409 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Alice Chao <alice.chao@mediatek.com> + * Copyright (c) 2026 Jolla Mobile Ltd + * Nikolai Burov <nikolai.burov@jolla.com> + */ + +#include <linux/module.h> +#include "pinctrl-mtk-mt6858.h" +#include "pinctrl-paris.h" + +/* MT6858 have multiple bases to program pin configuration listed as the below: + * GPIO_BASE: 0x10005000 + * IOCFG_LM_BASE: 0x11B20000 + * IOCFG_RB_BASE: 0x11C10000 + * IOCFG_BM2_BASE: 0x11D10000 + * IOCFG_BM_BASE: 0x11D30000 + * IOCFG_BM1_BASE: 0x11D40000 + * IOCFG_LT_BASE: 0x11E20000 + * IOCFG_LT1_BASE: 0x11E30000 + * IOCFG_RT_BASE: 0x11ED0000 + * IOCFG_RT1_BASE: 0x11EE0000 + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +static const struct mtk_pin_field_calc mt6858_pin_mode_range[] = { + /* Pin mode field is 5 bits with 8 bit stride */ + PIN_FIELD(0, 196, 0x0300, 0x10, 0, 8), +}; + +static const struct mtk_pin_field_calc mt6858_pin_dir_range[] = { + PIN_FIELD(0, 196, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_di_range[] = { + PIN_FIELD(0, 196, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_do_range[] = { + PIN_FIELD(0, 196, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(82, 82, 8, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 8, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 8, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 8, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 8, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 8, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 4, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(92, 92, 4, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(93, 93, 4, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(161, 161, 5, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0060, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0020, 0x10, 3, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0110, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0110, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0110, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0110, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0110, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0110, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0110, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(44, 44, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(48, 48, 5, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0100, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0100, 0x10, 17, 1), + PIN_FIELD_BASE(51, 51, 1, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(52, 52, 1, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(53, 53, 5, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(54, 54, 5, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(55, 55, 5, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00f0, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00f0, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00f0, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0110, 0x10, 25, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0110, 0x10, 26, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0110, 0x10, 28, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0110, 0x10, 27, 1), + PIN_FIELD_BASE(66, 66, 1, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(67, 67, 1, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, 1, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00f0, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00f0, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00f0, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00f0, 0x10, 27, 1), + PIN_FIELD_BASE(82, 82, 8, 0x0110, 0x10, 13, 1), + PIN_FIELD_BASE(83, 83, 8, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(84, 84, 8, 0x0110, 0x10, 15, 1), + PIN_FIELD_BASE(85, 85, 8, 0x0110, 0x10, 16, 1), + PIN_FIELD_BASE(86, 86, 8, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(87, 87, 8, 0x0110, 0x10, 18, 1), + PIN_FIELD_BASE(88, 88, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(90, 90, 4, 0x0100, 0x10, 15, 1), + PIN_FIELD_BASE(91, 91, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(92, 92, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(93, 93, 4, 0x0100, 0x10, 16, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0100, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0100, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0100, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(123, 123, 3, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(126, 126, 2, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0110, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0110, 0x10, 20, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00f0, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0110, 0x10, 21, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0110, 0x10, 23, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0110, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0110, 0x10, 24, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00e0, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 5, 0x00e0, 0x10, 25, 1), + PIN_FIELD_BASE(163, 163, 5, 0x00e0, 0x10, 24, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00e0, 0x10, 26, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0100, 0x10, 14, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0100, 0x10, 14, 1), + PIN_FIELD_BASE(173, 173, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(175, 175, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(176, 176, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(177, 177, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(178, 178, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(179, 179, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(180, 180, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(182, 182, 9, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x00c0, 0x10, 3, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(50, 50, 4, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(63, 63, 8, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, 8, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(65, 65, 8, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(94, 94, 4, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(136, 136, 8, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(158, 158, 8, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(159, 159, 8, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(160, 160, 8, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0080, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(2, 2, 8, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 8, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 8, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(5, 5, 8, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(6, 6, 8, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(7, 7, 8, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(8, 8, 5, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(9, 9, 5, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(11, 11, 5, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(13, 13, 7, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 7, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 7, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 7, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 7, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(23, 23, 8, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(35, 35, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, 8, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(37, 37, 8, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 8, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 5, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(49, 49, 4, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(50, 50, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(53, 53, 5, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(54, 54, 5, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 5, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(62, 62, 8, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(63, 63, 8, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(64, 64, 8, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(65, 65, 8, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(94, 94, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(95, 95, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(96, 96, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(97, 97, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(98, 98, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(99, 99, 9, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 9, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 9, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(102, 102, 9, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 9, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 9, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 9, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(117, 117, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(119, 119, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(120, 120, 3, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(121, 121, 3, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(122, 122, 7, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 3, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 1, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(126, 126, 2, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(127, 127, 2, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 2, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(129, 129, 2, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 3, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(133, 133, 3, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(134, 134, 3, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 8, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(136, 136, 8, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 7, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(138, 138, 7, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(139, 139, 3, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(140, 140, 3, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(143, 143, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(144, 144, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(145, 145, 3, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(146, 146, 3, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(147, 147, 2, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(148, 148, 2, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(150, 150, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(151, 151, 3, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(152, 152, 3, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(153, 153, 2, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 2, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(155, 155, 2, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 2, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(157, 157, 8, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(158, 158, 8, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(159, 159, 8, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(160, 160, 8, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(161, 161, 5, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(162, 162, 5, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(163, 163, 5, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(164, 164, 5, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(171, 171, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(182, 182, 9, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(195, 195, 9, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(196, 196, 6, 0x0060, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_pupd_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00a0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_r0_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00c0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_r1_range[] = { + PIN_FIELD_BASE(18, 18, 6, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(20, 20, 6, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 8, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 8, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(84, 84, 8, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(85, 85, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(86, 86, 8, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(87, 87, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(88, 88, 4, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 4, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 4, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 4, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 4, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 4, 0x00d0, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt6858_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(2, 2, 8, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(3, 3, 8, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(4, 4, 8, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(5, 5, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(7, 7, 8, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(8, 8, 5, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(9, 9, 5, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(10, 10, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(11, 11, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(13, 13, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(15, 15, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(16, 16, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(17, 17, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(19, 19, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(20, 20, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(21, 21, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(22, 22, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, 8, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(25, 25, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(27, 27, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(28, 28, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(29, 29, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(30, 30, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(31, 31, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(36, 36, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(38, 38, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(39, 39, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(40, 40, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(41, 41, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(42, 42, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(44, 44, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(48, 48, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, 4, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(50, 50, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(51, 51, 1, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(52, 52, 1, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(53, 53, 5, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 5, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(55, 55, 5, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(57, 57, 5, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(58, 58, 3, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(59, 59, 3, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(60, 60, 3, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(62, 62, 8, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(63, 63, 8, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(64, 64, 8, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(65, 65, 8, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(66, 66, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(67, 67, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(71, 71, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(72, 72, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(73, 73, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(78, 78, 3, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, 3, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(80, 80, 3, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, 3, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(82, 82, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(83, 83, 8, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(84, 84, 8, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(85, 85, 8, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(86, 86, 8, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(87, 87, 8, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(88, 88, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(89, 89, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(90, 90, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(91, 91, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(92, 92, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(93, 93, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(94, 94, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(95, 95, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(96, 96, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(97, 97, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(98, 98, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(99, 99, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(101, 101, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(102, 102, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(103, 103, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(105, 105, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(106, 106, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(109, 109, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(110, 110, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(111, 111, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(112, 112, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(113, 113, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(114, 114, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(115, 115, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(116, 116, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(117, 117, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(118, 118, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(119, 119, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(120, 120, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(121, 121, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(122, 122, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(123, 123, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(124, 124, 1, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(125, 125, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(126, 126, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(127, 127, 2, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(128, 128, 2, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(129, 129, 2, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(130, 130, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(131, 131, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(132, 132, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(133, 133, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(134, 134, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(135, 135, 8, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(136, 136, 8, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(137, 137, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(138, 138, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(139, 139, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(140, 140, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(143, 143, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(144, 144, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(145, 145, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(146, 146, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(147, 147, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(148, 148, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(149, 149, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(150, 150, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(151, 151, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(152, 152, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(153, 153, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(154, 154, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(155, 155, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(156, 156, 2, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(162, 162, 5, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(163, 163, 5, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(164, 164, 5, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(171, 171, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(172, 172, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(173, 173, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(174, 174, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(175, 175, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(176, 176, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(178, 178, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(179, 179, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(180, 180, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(181, 181, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(182, 182, 9, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(183, 183, 9, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(184, 184, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(185, 185, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(186, 186, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(187, 187, 9, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(188, 188, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(189, 189, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(190, 190, 9, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(191, 191, 9, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(192, 192, 9, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(193, 193, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(194, 194, 9, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(195, 195, 9, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(196, 196, 6, 0x0000, 0x10, 9, 3), +}; + +static const struct mtk_pin_field_calc mt6858_pin_drv_adv_range[] = { + PIN_FIELD_BASE(36, 36, 8, 0x0030, 0x10, 0, 5), + PIN_FIELD_BASE(37, 37, 8, 0x0030, 0x10, 5, 5), + PIN_FIELD_BASE(38, 38, 8, 0x0030, 0x10, 10, 5), + PIN_FIELD_BASE(39, 39, 8, 0x0030, 0x10, 15, 5), + PIN_FIELD_BASE(126, 126, 2, 0x0020, 0x10, 18, 5), + PIN_FIELD_BASE(127, 127, 2, 0x0020, 0x10, 23, 5), + PIN_FIELD_BASE(128, 128, 2, 0x0030, 0x10, 0, 5), + PIN_FIELD_BASE(129, 129, 2, 0x0030, 0x10, 5, 5), + PIN_FIELD_BASE(139, 139, 3, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 3, 0x0030, 0x10, 18, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 3, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 3, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(145, 145, 3, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 3, 0x0030, 0x10, 24, 3), + PIN_FIELD_BASE(147, 147, 2, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 2, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 5, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 3, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 3, 0x0030, 0x10, 27, 3), + PIN_FIELD_BASE(153, 153, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(154, 154, 2, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(155, 155, 2, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 2, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0030, 0x10, 20, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0030, 0x10, 26, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0030, 0x10, 23, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0030, 0x10, 29, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 5, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(163, 163, 5, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(164, 164, 5, 0x0030, 0x10, 15, 3), +}; + +static const struct mtk_pin_field_calc mt6858_pin_rsel_range[] = { + PIN_FIELD_BASE(139, 139, 3, 0x00e0, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 3, 0x00e0, 0x10, 18, 3), + PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 9, 3), + PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 3, 0x00e0, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 3, 0x00e0, 0x10, 3, 3), + PIN_FIELD_BASE(145, 145, 3, 0x00e0, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 3, 0x00e0, 0x10, 24, 3), + PIN_FIELD_BASE(147, 147, 2, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 2, 0x00b0, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 5, 0x00d0, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 5, 0x00d0, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 3, 0x00e0, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 3, 0x00e0, 0x10, 27, 3), + PIN_FIELD_BASE(153, 153, 2, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(154, 154, 2, 0x00b0, 0x10, 12, 3), + PIN_FIELD_BASE(155, 155, 2, 0x00b0, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 2, 0x00b0, 0x10, 15, 3), + PIN_FIELD_BASE(157, 157, 8, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(158, 158, 8, 0x0100, 0x10, 6, 3), + PIN_FIELD_BASE(159, 159, 8, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(160, 160, 8, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(161, 161, 5, 0x00d0, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 5, 0x00d0, 0x10, 12, 3), + PIN_FIELD_BASE(163, 163, 5, 0x00d0, 0x10, 9, 3), + PIN_FIELD_BASE(164, 164, 5, 0x00d0, 0x10, 15, 3), +}; + +static const unsigned int mt6858_pull_type[] = { + MTK_PULL_PU_PD_TYPE, /* 0 */ + MTK_PULL_PU_PD_TYPE, /* 1 */ + MTK_PULL_PU_PD_TYPE, /* 2 */ + MTK_PULL_PU_PD_TYPE, /* 3 */ + MTK_PULL_PU_PD_TYPE, /* 4 */ + MTK_PULL_PU_PD_TYPE, /* 5 */ + MTK_PULL_PU_PD_TYPE, /* 6 */ + MTK_PULL_PU_PD_TYPE, /* 7 */ + MTK_PULL_PU_PD_TYPE, /* 8 */ + MTK_PULL_PU_PD_TYPE, /* 9 */ + MTK_PULL_PU_PD_TYPE, /* 10 */ + MTK_PULL_PU_PD_TYPE, /* 11 */ + MTK_PULL_PU_PD_TYPE, /* 12 */ + MTK_PULL_PU_PD_TYPE, /* 13 */ + MTK_PULL_PU_PD_TYPE, /* 14 */ + MTK_PULL_PU_PD_TYPE, /* 15 */ + MTK_PULL_PU_PD_TYPE, /* 16 */ + MTK_PULL_PU_PD_TYPE, /* 17 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 18 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 19 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 20 */ + MTK_PULL_PU_PD_TYPE, /* 21 */ + MTK_PULL_PU_PD_TYPE, /* 22 */ + MTK_PULL_PU_PD_TYPE, /* 23 */ + MTK_PULL_PU_PD_TYPE, /* 24 */ + MTK_PULL_PU_PD_TYPE, /* 25 */ + MTK_PULL_PU_PD_TYPE, /* 26 */ + MTK_PULL_PU_PD_TYPE, /* 27 */ + MTK_PULL_PU_PD_TYPE, /* 28 */ + MTK_PULL_PU_PD_TYPE, /* 29 */ + MTK_PULL_PU_PD_TYPE, /* 30 */ + MTK_PULL_PU_PD_TYPE, /* 31 */ + MTK_PULL_PU_PD_TYPE, /* 32 */ + MTK_PULL_PU_PD_TYPE, /* 33 */ + MTK_PULL_PU_PD_TYPE, /* 34 */ + MTK_PULL_PU_PD_TYPE, /* 35 */ + MTK_PULL_PU_PD_TYPE, /* 36 */ + MTK_PULL_PU_PD_TYPE, /* 37 */ + MTK_PULL_PU_PD_TYPE, /* 38 */ + MTK_PULL_PU_PD_TYPE, /* 39 */ + MTK_PULL_PU_PD_TYPE, /* 40 */ + MTK_PULL_PU_PD_TYPE, /* 41 */ + MTK_PULL_PU_PD_TYPE, /* 42 */ + MTK_PULL_PU_PD_TYPE, /* 43 */ + MTK_PULL_PU_PD_TYPE, /* 44 */ + MTK_PULL_PU_PD_TYPE, /* 45 */ + MTK_PULL_PU_PD_TYPE, /* 46 */ + MTK_PULL_PU_PD_TYPE, /* 47 */ + MTK_PULL_PU_PD_TYPE, /* 48 */ + MTK_PULL_PU_PD_TYPE, /* 49 */ + MTK_PULL_PU_PD_TYPE, /* 50 */ + MTK_PULL_PU_PD_TYPE, /* 51 */ + MTK_PULL_PU_PD_TYPE, /* 52 */ + MTK_PULL_PU_PD_TYPE, /* 53 */ + MTK_PULL_PU_PD_TYPE, /* 54 */ + MTK_PULL_PU_PD_TYPE, /* 55 */ + MTK_PULL_PU_PD_TYPE, /* 56 */ + MTK_PULL_PU_PD_TYPE, /* 57 */ + MTK_PULL_PU_PD_TYPE, /* 58 */ + MTK_PULL_PU_PD_TYPE, /* 59 */ + MTK_PULL_PU_PD_TYPE, /* 60 */ + MTK_PULL_PU_PD_TYPE, /* 61 */ + MTK_PULL_PU_PD_TYPE, /* 62 */ + MTK_PULL_PU_PD_TYPE, /* 63 */ + MTK_PULL_PU_PD_TYPE, /* 64 */ + MTK_PULL_PU_PD_TYPE, /* 65 */ + MTK_PULL_PU_PD_TYPE, /* 66 */ + MTK_PULL_PU_PD_TYPE, /* 67 */ + MTK_PULL_PU_PD_TYPE, /* 68 */ + MTK_PULL_PU_PD_TYPE, /* 69 */ + MTK_PULL_PU_PD_TYPE, /* 70 */ + MTK_PULL_PU_PD_TYPE, /* 71 */ + MTK_PULL_PU_PD_TYPE, /* 72 */ + MTK_PULL_PU_PD_TYPE, /* 73 */ + MTK_PULL_PU_PD_TYPE, /* 74 */ + MTK_PULL_PU_PD_TYPE, /* 75 */ + MTK_PULL_PU_PD_TYPE, /* 76 */ + MTK_PULL_PU_PD_TYPE, /* 77 */ + MTK_PULL_PU_PD_TYPE, /* 78 */ + MTK_PULL_PU_PD_TYPE, /* 79 */ + MTK_PULL_PU_PD_TYPE, /* 80 */ + MTK_PULL_PU_PD_TYPE, /* 81 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 82 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 83 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 84 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 85 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 86 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 87 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 88 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 89 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 90 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 91 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 92 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 93 */ + MTK_PULL_PU_PD_TYPE, /* 94 */ + MTK_PULL_PU_PD_TYPE, /* 95 */ + MTK_PULL_PU_PD_TYPE, /* 96 */ + MTK_PULL_PU_PD_TYPE, /* 97 */ + MTK_PULL_PU_PD_TYPE, /* 98 */ + MTK_PULL_PU_PD_TYPE, /* 99 */ + MTK_PULL_PU_PD_TYPE, /* 100 */ + MTK_PULL_PU_PD_TYPE, /* 101 */ + MTK_PULL_PU_PD_TYPE, /* 102 */ + MTK_PULL_PU_PD_TYPE, /* 103 */ + MTK_PULL_PU_PD_TYPE, /* 104 */ + MTK_PULL_PU_PD_TYPE, /* 105 */ + MTK_PULL_PU_PD_TYPE, /* 106 */ + MTK_PULL_PU_PD_TYPE, /* 107 */ + MTK_PULL_PU_PD_TYPE, /* 108 */ + MTK_PULL_PU_PD_TYPE, /* 109 */ + MTK_PULL_PU_PD_TYPE, /* 110 */ + MTK_PULL_PU_PD_TYPE, /* 111 */ + MTK_PULL_PU_PD_TYPE, /* 112 */ + MTK_PULL_PU_PD_TYPE, /* 113 */ + MTK_PULL_PU_PD_TYPE, /* 114 */ + MTK_PULL_PU_PD_TYPE, /* 115 */ + MTK_PULL_PU_PD_TYPE, /* 116 */ + MTK_PULL_PU_PD_TYPE, /* 117 */ + MTK_PULL_PU_PD_TYPE, /* 118 */ + MTK_PULL_PU_PD_TYPE, /* 119 */ + MTK_PULL_PU_PD_TYPE, /* 120 */ + MTK_PULL_PU_PD_TYPE, /* 121 */ + MTK_PULL_PU_PD_TYPE, /* 122 */ + MTK_PULL_PU_PD_TYPE, /* 123 */ + MTK_PULL_PU_PD_TYPE, /* 124 */ + MTK_PULL_PU_PD_TYPE, /* 125 */ + MTK_PULL_PU_PD_TYPE, /* 126 */ + MTK_PULL_PU_PD_TYPE, /* 127 */ + MTK_PULL_PU_PD_TYPE, /* 128 */ + MTK_PULL_PU_PD_TYPE, /* 129 */ + MTK_PULL_PU_PD_TYPE, /* 130 */ + MTK_PULL_PU_PD_TYPE, /* 131 */ + MTK_PULL_PU_PD_TYPE, /* 132 */ + MTK_PULL_PU_PD_TYPE, /* 133 */ + MTK_PULL_PU_PD_TYPE, /* 134 */ + MTK_PULL_PU_PD_TYPE, /* 135 */ + MTK_PULL_PU_PD_TYPE, /* 136 */ + MTK_PULL_PU_PD_TYPE, /* 137 */ + MTK_PULL_PU_PD_TYPE, /* 138 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 139 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 140 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 141 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 142 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 143 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 144 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 145 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 146 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 147 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 148 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 149 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 150 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 151 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 152 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 153 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 154 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 155 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 156 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 157 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 158 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 159 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 160 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 161 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 162 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 163 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 164 */ + MTK_PULL_PU_PD_TYPE, /* 165 */ + MTK_PULL_PU_PD_TYPE, /* 166 */ + MTK_PULL_PU_PD_TYPE, /* 167 */ + MTK_PULL_PU_PD_TYPE, /* 168 */ + MTK_PULL_PU_PD_TYPE, /* 169 */ + MTK_PULL_PU_PD_TYPE, /* 170 */ + MTK_PULL_PU_PD_TYPE, /* 171 */ + MTK_PULL_PU_PD_TYPE, /* 172 */ + MTK_PULL_PU_PD_TYPE, /* 173 */ + MTK_PULL_PU_PD_TYPE, /* 174 */ + MTK_PULL_PU_PD_TYPE, /* 175 */ + MTK_PULL_PU_PD_TYPE, /* 176 */ + MTK_PULL_PU_PD_TYPE, /* 177 */ + MTK_PULL_PU_PD_TYPE, /* 178 */ + MTK_PULL_PU_PD_TYPE, /* 179 */ + MTK_PULL_PU_PD_TYPE, /* 180 */ + MTK_PULL_PU_PD_TYPE, /* 181 */ + MTK_PULL_PU_PD_TYPE, /* 182 */ + MTK_PULL_PU_PD_TYPE, /* 183 */ + MTK_PULL_PU_PD_TYPE, /* 184 */ + MTK_PULL_PU_PD_TYPE, /* 185 */ + MTK_PULL_PU_PD_TYPE, /* 186 */ + MTK_PULL_PU_PD_TYPE, /* 187 */ + MTK_PULL_PU_PD_TYPE, /* 188 */ + MTK_PULL_PU_PD_TYPE, /* 189 */ + MTK_PULL_PU_PD_TYPE, /* 190 */ + MTK_PULL_PU_PD_TYPE, /* 191 */ + MTK_PULL_PU_PD_TYPE, /* 192 */ + MTK_PULL_PU_PD_TYPE, /* 193 */ + MTK_PULL_PU_PD_TYPE, /* 194 */ + MTK_PULL_PU_PD_TYPE, /* 195 */ + MTK_PULL_PU_PD_TYPE, /* 196 */ +}; + +static const struct mtk_pin_reg_calc mt6858_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6858_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6858_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6858_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6858_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6858_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6858_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6858_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6858_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6858_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6858_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6858_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6858_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt6858_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6858_pin_rsel_range), +}; + +static const char * const mt6858_pinctrl_register_base_names[] = { + "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1", "rt", "rt1", +}; + +static const struct mtk_eint_hw mt6858_eint_hw = { + .port_mask = 0xf, + .ports = 3, + .ap_num = 217, + .db_cnt = 36, + .db_time = debounce_time_mt6878, +}; + +static const struct mtk_pin_soc mt6858_data = { + .reg_cal = mt6858_reg_cals, + .pins = mtk_pins_mt6858, + .npins = ARRAY_SIZE(mtk_pins_mt6858), + .ngrps = ARRAY_SIZE(mtk_pins_mt6858), + .eint_hw = &mt6858_eint_hw, + .eint_pin = eint_pins_mt6858, + .nfuncs = 16, + .gpio_m = 0, + .base_names = mt6858_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6858_pinctrl_register_base_names), + .pull_type = mt6858_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt6858_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6858-pinctrl", .data = &mt6858_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mt6858_pinctrl_of_match); + +static struct platform_driver mt6858_pinctrl_driver = { + .driver = { + .name = "mt6858-pinctrl", + .of_match_table = mt6858_pinctrl_of_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt6858_pinctrl_init(void) +{ + return platform_driver_register(&mt6858_pinctrl_driver); +} +arch_initcall(mt6858_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6858 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6878.c b/drivers/pinctrl/mediatek/pinctrl-mt6878.c index b59ae089128a..7b5a15f4aba1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6878.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6878.c @@ -1459,6 +1459,7 @@ static const struct of_device_id mt6878_pinctrl_of_match[] = { { .compatible = "mediatek,mt6878-pinctrl", .data = &mt6878_data }, { } }; +MODULE_DEVICE_TABLE(of, mt6878_pinctrl_of_match); static struct platform_driver mt6878_pinctrl_driver = { .driver = { @@ -1476,3 +1477,4 @@ static int __init mt6878_pinctrl_init(void) arch_initcall(mt6878_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT6878 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6893.c b/drivers/pinctrl/mediatek/pinctrl-mt6893.c index 468ce0109b07..5ff1e7722889 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6893.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6893.c @@ -859,6 +859,7 @@ static const struct of_device_id mt6893_pinctrl_of_match[] = { { .compatible = "mediatek,mt6893-pinctrl", .data = &mt6893_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt6893_pinctrl_of_match); static struct platform_driver mt6893_pinctrl_driver = { .driver = { @@ -877,3 +878,4 @@ static int __init mt6893_pinctrl_init(void) arch_initcall(mt6893_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT6893 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7620.c b/drivers/pinctrl/mediatek/pinctrl-mt7620.c index d2624b9b5bc4..7bfa6a8a3ce3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -135,3 +135,7 @@ static int __init mt7620_pinctrl_init(void) return platform_driver_register(&mt7620_pinctrl_driver); } core_initcall_sync(mt7620_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7620 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7621.c b/drivers/pinctrl/mediatek/pinctrl-mt7621.c index b18c1a47bbeb..5a893d8505a3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -115,3 +115,7 @@ static int __init mt7621_pinctrl_init(void) return platform_driver_register(&mt7621_pinctrl_driver); } core_initcall_sync(mt7621_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7621 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index d5777889448a..36a9a9f302ca 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -874,6 +874,7 @@ static const struct of_device_id mt7622_pinctrl_of_match[] = { { .compatible = "mediatek,mt7622-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, mt7622_pinctrl_of_match); static int mt7622_pinctrl_probe(struct platform_device *pdev) { @@ -893,3 +894,7 @@ static int __init mt7622_pinctrl_init(void) return platform_driver_register(&mt7622_pinctrl_driver); } arch_initcall(mt7622_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7622 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index 69c06c2c0e21..26fa489db13c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -1413,6 +1413,7 @@ static const struct of_device_id mt7623_pctrl_match[] = { { .compatible = "mediatek,mt7623-moore-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7623_pctrl_match); static int mt7623_pinctrl_probe(struct platform_device *pdev) { @@ -1440,3 +1441,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7623 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index cc0694881ac9..385d66b8e3fb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -430,6 +430,7 @@ static const struct of_device_id mt7629_pinctrl_of_match[] = { { .compatible = "mediatek,mt7629-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7629_pinctrl_of_match); static int mt7629_pinctrl_probe(struct platform_device *pdev) { @@ -449,3 +450,7 @@ static int __init mt7629_pinctrl_init(void) return platform_driver_register(&mt7629_pinctrl_driver); } arch_initcall(mt7629_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7629 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 2bc8d4409ca2..336d4e36e884 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -247,3 +247,7 @@ static int __init mt76x8_pinctrl_init(void) return platform_driver_register(&mt76x8_pinctrl_driver); } core_initcall_sync(mt76x8_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT76X8 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 22c8f2480346..2325cc8b9345 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -1039,6 +1039,7 @@ static const struct of_device_id mt7981_pinctrl_of_match[] = { { .compatible = "mediatek,mt7981-pinctrl", }, {} }; +MODULE_DEVICE_TABLE(of, mt7981_pinctrl_of_match); static int mt7981_pinctrl_probe(struct platform_device *pdev) { @@ -1058,3 +1059,7 @@ static int __init mt7981_pinctrl_init(void) return platform_driver_register(&mt7981_pinctrl_driver); } arch_initcall(mt7981_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7981 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 5dda4b7467fd..6cbf90879eb5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -965,11 +965,13 @@ static const struct of_device_id mt7986a_pinctrl_of_match[] = { {.compatible = "mediatek,mt7986a-pinctrl",}, {} }; +MODULE_DEVICE_TABLE(of, mt7986a_pinctrl_of_match); static const struct of_device_id mt7986b_pinctrl_of_match[] = { {.compatible = "mediatek,mt7986b-pinctrl",}, {} }; +MODULE_DEVICE_TABLE(of, mt7986b_pinctrl_of_match); static int mt7986a_pinctrl_probe(struct platform_device *pdev) { @@ -997,15 +999,18 @@ static struct platform_driver mt7986b_pinctrl_driver = { .probe = mt7986b_pinctrl_probe, }; -static int __init mt7986a_pinctrl_init(void) -{ - return platform_driver_register(&mt7986a_pinctrl_driver); -} +static struct platform_driver * const mt7986_pinctrl_drivers[] = { + &mt7986a_pinctrl_driver, + &mt7986b_pinctrl_driver, +}; -static int __init mt7986b_pinctrl_init(void) +static int __init mt7986_pinctrl_init(void) { - return platform_driver_register(&mt7986b_pinctrl_driver); + return platform_register_drivers(mt7986_pinctrl_drivers, + ARRAY_SIZE(mt7986_pinctrl_drivers)); } +arch_initcall(mt7986_pinctrl_init); -arch_initcall(mt7986a_pinctrl_init); -arch_initcall(mt7986b_pinctrl_init); +MODULE_DESCRIPTION("MediaTek MT7986 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index fd3a7ff0a04d..14b5f4b695a2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1525,6 +1525,7 @@ static const struct of_device_id mt7988_pinctrl_of_match[] = { { .compatible = "mediatek,mt7988-pinctrl" }, {} }; +MODULE_DEVICE_TABLE(of, mt7988_pinctrl_of_match); static int mt7988_pinctrl_probe(struct platform_device *pdev) { @@ -1544,3 +1545,7 @@ static int __init mt7988_pinctrl_init(void) return platform_driver_register(&mt7988_pinctrl_driver); } arch_initcall(mt7988_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT7988 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index f5030a9ea40b..296eed43c10a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -293,6 +293,7 @@ static const struct of_device_id mt8127_pctrl_match[] = { { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8127_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -307,3 +308,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 77c6ac464e86..713b362832db 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -322,6 +322,7 @@ static const struct of_device_id mt8135_pctrl_match[] = { { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8135_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -336,3 +337,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8135 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index 143c26622272..cc45b0954009 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -244,7 +244,7 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = { MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12), MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0), MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1), - MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2), + MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2), MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11), MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10), MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11), @@ -343,3 +343,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8167 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index b214deeafbf1..fbb92a1b9d2c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -341,6 +341,7 @@ static const struct of_device_id mt8173_pctrl_match[] = { }, { } }; +MODULE_DEVICE_TABLE(of, mt8173_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mt8173_pinctrl_probe, @@ -356,3 +357,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8173 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index 93e482c6b5fd..edc68f998d8c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -571,6 +571,7 @@ static const struct of_device_id mt8183_pinctrl_of_match[] = { { .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8183_pinctrl_of_match); static struct platform_driver mt8183_pinctrl_driver = { .driver = { @@ -586,3 +587,6 @@ static int __init mt8183_pinctrl_init(void) return platform_driver_register(&mt8183_pinctrl_driver); } arch_initcall(mt8183_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8183 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c index dd19e74856a9..d4817838c531 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8186.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c @@ -1249,6 +1249,7 @@ static const struct of_device_id mt8186_pinctrl_of_match[] = { { .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8186_pinctrl_of_match); static struct platform_driver mt8186_pinctrl_driver = { .driver = { @@ -1265,3 +1266,6 @@ static int __init mt8186_pinctrl_init(void) } arch_initcall(mt8186_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8186 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8188.c b/drivers/pinctrl/mediatek/pinctrl-mt8188.c index 3975e99d9cf4..35dde16ab449 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8188.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8188.c @@ -1653,6 +1653,7 @@ static const struct of_device_id mt8188_pinctrl_of_match[] = { { .compatible = "mediatek,mt8188-pinctrl", .data = &mt8188_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8188_pinctrl_of_match); static struct platform_driver mt8188_pinctrl_driver = { .driver = { @@ -1671,3 +1672,4 @@ static int __init mt8188_pinctrl_init(void) arch_initcall(mt8188_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8188 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c index cd4cdff309a1..1b1f9b4b6ad1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -1679,6 +1679,7 @@ static const struct of_device_id mt8189_pinctrl_of_match[] = { { .compatible = "mediatek,mt8189-pinctrl", .data = &mt8189_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt8189_pinctrl_of_match); static struct platform_driver mt8189_pinctrl_driver = { .driver = { @@ -1696,3 +1697,4 @@ static int __init mt8189_pinctrl_init(void) arch_initcall(mt8189_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8189 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index 3f8a9dbcb704..b2ae3a62418d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1414,6 +1414,7 @@ static const struct of_device_id mt8192_pinctrl_of_match[] = { { .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8192_pinctrl_of_match); static struct platform_driver mt8192_pinctrl_driver = { .driver = { @@ -1431,3 +1432,4 @@ static int __init mt8192_pinctrl_init(void) arch_initcall(mt8192_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8192 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 83345c52b2fa..3a9912c0c095 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -963,6 +963,7 @@ static const struct of_device_id mt8195_pinctrl_of_match[] = { { .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data }, { } }; +MODULE_DEVICE_TABLE(of, mt8195_pinctrl_of_match); static struct platform_driver mt8195_pinctrl_driver = { .driver = { @@ -978,3 +979,6 @@ static int __init mt8195_pinctrl_init(void) return platform_driver_register(&mt8195_pinctrl_driver); } arch_initcall(mt8195_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8195 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8196.c b/drivers/pinctrl/mediatek/pinctrl-mt8196.c index dec957c1724b..2e36bf3c45eb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8196.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8196.c @@ -1839,6 +1839,7 @@ static const struct of_device_id mt8196_pinctrl_of_match[] = { { .compatible = "mediatek,mt8196-pinctrl", .data = &mt8196_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, mt8196_pinctrl_of_match); static struct platform_driver mt8196_pinctrl_driver = { .driver = { @@ -1856,3 +1857,4 @@ static int __init mt8196_pinctrl_init(void) arch_initcall(mt8196_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8196 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index c20b9e2e02dd..564227f7ca2d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -477,6 +477,7 @@ static const struct of_device_id mt8365_pctrl_match[] = { { .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data }, {} }; +MODULE_DEVICE_TABLE(of, mt8365_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { .probe = mtk_pctrl_common_probe, @@ -494,4 +495,6 @@ static int __init mtk_pinctrl_init(void) arch_initcall(mtk_pinctrl_init); MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index abda75d4354e..d4f0a0bc5438 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -244,7 +244,7 @@ static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = { MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12), MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0), MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1), - MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2), + MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2), MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11), MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10), MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11), @@ -343,3 +343,7 @@ static int __init mtk_pinctrl_init(void) return platform_driver_register(&mtk_pinctrl_driver); } arch_initcall(mtk_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8516 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 4918d38abfc2..faa6dbf0f635 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -69,6 +69,7 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) spin_unlock_irqrestore(&pctl->lock, flags); } +EXPORT_SYMBOL_NS_GPL(mtk_rmw, "MTK_PINCTRL"); static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, @@ -1242,11 +1243,7 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, if (err) return err; - err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); - if (err) - return err; - - return err; + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1); } EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 3f518dce6d23..1a977acd6883 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -7,6 +7,7 @@ #include <linux/io.h> #include <linux/gpio/driver.h> +#include <linux/module.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/pinctrl/consumer.h> @@ -190,6 +191,7 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, regmap_write(regmap, reg_addr, bit); return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_pconf_spec_set_ies_smt_range, "MTK_PINCTRL"); static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( struct mtk_pinctrl *pctl, unsigned long pin) { @@ -297,6 +299,7 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, return 0; } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_spec_pull_set_samereg, "MTK_PINCTRL"); static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, unsigned int pin, bool enable, bool isup, unsigned int arg) @@ -802,20 +805,27 @@ static const struct pinmux_ops mtk_pmx_ops = { .get_function_name = mtk_pmx_get_func_name, .get_function_groups = mtk_pmx_get_func_groups, .set_mux = mtk_pmx_set_mux, - .gpio_set_direction = mtk_pmx_gpio_set_direction, .gpio_request_enable = mtk_pmx_gpio_request_enable, }; +static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct mtk_pinctrl *pctl = gpiochip_get_data(chip); + + return mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, true); +} + static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { + struct mtk_pinctrl *pctl = gpiochip_get_data(chip); int ret; ret = mtk_gpio_set(chip, offset, value); if (ret) return ret; - return pinctrl_gpio_direction_output(chip, offset); + return mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, offset, false); } static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) @@ -895,7 +905,7 @@ static const struct gpio_chip mtk_gpio_chip = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .get_direction = mtk_gpio_get_direction, - .direction_input = pinctrl_gpio_direction_input, + .direction_input = mtk_gpio_direction_input, .direction_output = mtk_gpio_direction_output, .get = mtk_gpio_get, .set = mtk_gpio_set, @@ -1123,31 +1133,26 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->chip->parent = &pdev->dev; pctl->chip->base = -1; - ret = gpiochip_add_data(pctl->chip, pctl); + ret = devm_gpiochip_add_data(&pdev->dev, pctl->chip, pctl); if (ret) return -EINVAL; /* Register the GPIO to pin mappings. */ ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 0, 0, pctl->devdata->npins); - if (ret) { - ret = -EINVAL; - goto chip_error; - } + if (ret) + return -EINVAL; /* Only initialize EINT if we have EINT pins */ if (data->eint_hw.ap_num > 0) { ret = mtk_eint_init(pctl, pdev); if (ret) - goto chip_error; + return ret; } return 0; - -chip_error: - gpiochip_remove(pctl->chip); - return ret; } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_init, "MTK_PINCTRL"); int mtk_pctrl_common_probe(struct platform_device *pdev) { @@ -1159,3 +1164,7 @@ int mtk_pctrl_common_probe(struct platform_device *pdev) return mtk_pctrl_init(pdev, data, NULL); } +EXPORT_SYMBOL_NS_GPL(mtk_pctrl_common_probe, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h new file mode 100644 index 000000000000..208db809717f --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6858.h @@ -0,0 +1,2378 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Alice Chao <alice.chao@mediatek.com> + * Copyright (c) 2026 Jolla Mobile Ltd + * Nikolai Burov <nikolai.burov@jolla.com> + */ + +#ifndef __PINCTRL_MTK_MT6858_H +#define __PINCTRL_MTK_MT6858_H + +#include "pinctrl-paris.h" + +#define EINT_INVALID_BASE 0xff + +#define MTK_PIN_VEINT(_number) \ + MTK_PIN( \ + _number, "veint" #_number, \ + MTK_EINT_FUNCTION(0, _number), \ + DRV_GRP4, \ + MTK_FUNCTION(0, NULL) \ + ) + +static const struct mtk_pin_desc mtk_pins_mt6858[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "TP_GPIO0_AO"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(5, "SCP_SCL4"), + MTK_FUNCTION(7, "DBG_MON_A0"), + MTK_FUNCTION(8, "IOBIST0") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "TP_GPIO1_AO"), + MTK_FUNCTION(2, "SRCLKENA2"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(4, "SCP_DMIC_CLK"), + MTK_FUNCTION(5, "DMIC_CLK"), + MTK_FUNCTION(6, "SCP_SCL5"), + MTK_FUNCTION(7, "DBG_MON_A1"), + MTK_FUNCTION(8, "IOBIST1") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "TP_GPIO2_AO"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(4, "SCP_DMIC_DAT"), + MTK_FUNCTION(5, "DMIC_DAT"), + MTK_FUNCTION(6, "SCP_SDA5"), + MTK_FUNCTION(7, "DBG_MON_A2"), + MTK_FUNCTION(8, "IOBIST2") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "TP_GPIO3_AO"), + MTK_FUNCTION(2, "SPI7_CLK"), + MTK_FUNCTION(3, "TP_UTXD2_VLP"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_UTXD0"), + MTK_FUNCTION(8, "IOBIST3") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "TP_GPIO4_AO"), + MTK_FUNCTION(2, "SPI7_CSB"), + MTK_FUNCTION(3, "TP_URXD2_VLP"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(5, "MD_MCIF_URXD0"), + MTK_FUNCTION(8, "IOBIST4") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "TP_GPIO5_AO"), + MTK_FUNCTION(2, "SPI7_MO"), + MTK_FUNCTION(8, "IOBIST5") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "TP_GPIO6_AO"), + MTK_FUNCTION(2, "SPI7_MI"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "MD32_0_GPIO0"), + MTK_FUNCTION(8, "IOBIST6") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "TP_GPIO7_AO"), + MTK_FUNCTION(2, "SRCLKENA1"), + MTK_FUNCTION(3, "PWM_1"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(5, "SCP_SDA4"), + MTK_FUNCTION(6, "MD_INT4"), + MTK_FUNCTION(8, "IOBIST7") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SSPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TRSTN_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TRST_B"), + MTK_FUNCTION(8, "IOBIST8") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SSPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TCK_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TCK"), + MTK_FUNCTION(8, "IOBIST9") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "SSPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TMS_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TMS"), + MTK_FUNCTION(8, "IOBIST10") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "SSPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TDI_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDI"), + MTK_FUNCTION(8, "IOBIST11") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SSPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(2, "SCP_JTAG0_TDO_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDO"), + MTK_FUNCTION(8, "IOBIST12") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "TP_GPIO8_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TRSTN"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(4, "SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TRSTN_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN"), + MTK_FUNCTION(8, "IOBIST13") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "TP_GPIO9_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TCK"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(4, "SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TCK_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TCK"), + MTK_FUNCTION(8, "IOBIST14") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "TP_GPIO10_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TMS"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(4, "SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TMS_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TMS"), + MTK_FUNCTION(8, "IOBIST15") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "TP_GPIO11_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TDI"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(4, "SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TDI_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TDI"), + MTK_FUNCTION(8, "IOBIST16") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "TP_GPIO12_AO"), + MTK_FUNCTION(2, "HFRP_JTAG0_TDO"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(4, "SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(5, "SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(6, "SCP_JTAG0_TDO_VLP"), + MTK_FUNCTION(7, "IO_JTAG_TDO"), + MTK_FUNCTION(8, "IOBIST17") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "TSFDC_EN"), + MTK_FUNCTION(8, "IOBIST18") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "TP_UTXD2_VCORE"), + MTK_FUNCTION(4, "SSPM_UTXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(8, "IOBIST19") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "TP_URXD2_VCORE"), + MTK_FUNCTION(4, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(8, "IOBIST20") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "CONN_WIFI_TXD"), + MTK_FUNCTION(3, "CONN_BT_TXD"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "TP_UTXD1_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(7, "MD_UTXD1"), + MTK_FUNCTION(8, "IOBIST21") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(3, "PMSR_SMAP"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "TP_URXD1_VCORE"), + MTK_FUNCTION(6, "CONN_BGF_UART0_RXD"), + MTK_FUNCTION(7, "MD_URXD1"), + MTK_FUNCTION(8, "IOBIST22") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_A6"), + MTK_FUNCTION(8, "IOBIST23") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(2, "I2SIN2_MCK"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_B0"), + MTK_FUNCTION(8, "IOBIST24") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(4, "PWM_3"), + MTK_FUNCTION(7, "DBG_MON_A8"), + MTK_FUNCTION(8, "IOBIST25") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "MD32_0_GPIO0"), + MTK_FUNCTION(4, "PWM_0"), + MTK_FUNCTION(5, "VBUSVALID"), + MTK_FUNCTION(8, "IOBIST26") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(6, "DAP_SONIC_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A10"), + MTK_FUNCTION(8, "IOBIST27") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(6, "DAP_SONIC_SWD"), + MTK_FUNCTION(7, "DBG_MON_A11"), + MTK_FUNCTION(8, "IOBIST28") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(3, "SCL10"), + MTK_FUNCTION(6, "DAP_MD32_SWCK"), + MTK_FUNCTION(7, "DBG_MON_A12"), + MTK_FUNCTION(8, "IOBIST29") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(3, "SDA10"), + MTK_FUNCTION(6, "DAP_MD32_SWD"), + MTK_FUNCTION(7, "DBG_MON_A13"), + MTK_FUNCTION(8, "IOBIST30") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(3, "SCL12"), + MTK_FUNCTION(7, "DBG_MON_A14"), + MTK_FUNCTION(8, "IOBIST31") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(3, "SDA12"), + MTK_FUNCTION(7, "DBG_MON_A15"), + MTK_FUNCTION(8, "IOBIST32") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(7, "DBG_MON_A16"), + MTK_FUNCTION(8, "IOBIST33") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(3, "VBUSVALID"), + MTK_FUNCTION(7, "DBG_MON_A17"), + MTK_FUNCTION(8, "IOBIST34") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(7, "DBG_MON_A18"), + MTK_FUNCTION(8, "IOBIST35") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(7, "DBG_MON_A19"), + MTK_FUNCTION(8, "IOBIST36") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(7, "DBG_MON_A20"), + MTK_FUNCTION(8, "IOBIST37") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(7, "DBG_MON_A21"), + MTK_FUNCTION(8, "IOBIST38") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(7, "DBG_MON_A22"), + MTK_FUNCTION(8, "IOBIST39") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "I2SIN1_MCK"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "IRRX_IN"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(8, "IOBIST40") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "I2SIN1_BCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TMSC"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(8, "IOBIST41") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_AICE_TCKC"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(8, "IOBIST42") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "I2SOUT1_DO"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TMSC"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(8, "IOBIST43") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "I2SIN1_DI"), + MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(8, "IOBIST44") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "I2SIN2_BCK"), + MTK_FUNCTION(2, "SCL11"), + MTK_FUNCTION(3, "BPI_BUS10"), + MTK_FUNCTION(4, "MD_UCTS0"), + MTK_FUNCTION(5, "TP_UCTS1_VCORE"), + MTK_FUNCTION(6, "HFRP_UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B1"), + MTK_FUNCTION(8, "IOBIST45") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "I2SIN2_LRCK"), + MTK_FUNCTION(2, "SDA11"), + MTK_FUNCTION(3, "BPI_BUS11"), + MTK_FUNCTION(4, "MD_URTS0"), + MTK_FUNCTION(5, "TP_URTS1_VCORE"), + MTK_FUNCTION(6, "HFRP_URTS1"), + MTK_FUNCTION(7, "DBG_MON_B2"), + MTK_FUNCTION(8, "IOBIST46") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "I2SOUT2_DO"), + MTK_FUNCTION(2, "SCL1"), + MTK_FUNCTION(3, "BPI_BUS12"), + MTK_FUNCTION(4, "MD_UCTS1"), + MTK_FUNCTION(5, "TP_UCTS2_VCORE"), + MTK_FUNCTION(6, "UCTS2"), + MTK_FUNCTION(7, "DBG_MON_B3"), + MTK_FUNCTION(8, "IOBIST47") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "I2SIN2_DI"), + MTK_FUNCTION(2, "SDA1"), + MTK_FUNCTION(3, "BPI_BUS13"), + MTK_FUNCTION(4, "MD_URTS1"), + MTK_FUNCTION(5, "TP_URTS2_VCORE"), + MTK_FUNCTION(6, "URTS2"), + MTK_FUNCTION(7, "DBG_MON_B4"), + MTK_FUNCTION(8, "IOBIST48") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "HFRP_UTXD1"), + MTK_FUNCTION(5, "MD32_0_TXD"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(8, "IOBIST49") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "HFRP_URXD1"), + MTK_FUNCTION(5, "MD32_0_RXD"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(8, "IOBIST50") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "TP_UTXD1_VLP"), + MTK_FUNCTION(3, "TP_UTXD2_VLP"), + MTK_FUNCTION(4, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0"), + MTK_FUNCTION(7, "MD_UTXD0"), + MTK_FUNCTION(8, "IOBIST51") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "TP_URXD1_VLP"), + MTK_FUNCTION(3, "TP_URXD2_VLP"), + MTK_FUNCTION(4, "CONN_BGF_UART0_RXD"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(6, "MD_MCIF_URXD0"), + MTK_FUNCTION(7, "MD_URXD0"), + MTK_FUNCTION(8, "IOBIST52") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "JTRSTN_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(8, "IOBIST53") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "JTCK_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(8, "IOBIST54") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "JTMS_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(8, "IOBIST55") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "JTDI_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(8, "IOBIST56") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "JTDO_SEL1_VCORE"), + MTK_FUNCTION(2, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(8, "IOBIST57") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SPI4_CLK"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "TP_UTXD1_VCORE"), + MTK_FUNCTION(5, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(6, "EXTIF0_ACT"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK"), + MTK_FUNCTION(8, "IOBIST58") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SPI4_CSB"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "TP_URXD1_VCORE"), + MTK_FUNCTION(5, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(6, "EXTIF0_PRI"), + MTK_FUNCTION(7, "DAP_SONIC_SWD"), + MTK_FUNCTION(8, "IOBIST59") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SPI4_MO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B"), + MTK_FUNCTION(7, "DAP_MD32_SWCK"), + MTK_FUNCTION(8, "IOBIST60") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "SPI4_MI"), + MTK_FUNCTION(7, "DAP_MD32_SWD"), + MTK_FUNCTION(8, "IOBIST61") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "SCP_SPI1_CK"), + MTK_FUNCTION(2, "SPI1_CLK"), + MTK_FUNCTION(3, "TP_UTXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "UTXD0"), + MTK_FUNCTION(7, "DBG_MON_A25"), + MTK_FUNCTION(8, "IOBIST62") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "SCP_SPI1_CS"), + MTK_FUNCTION(2, "SPI1_CSB"), + MTK_FUNCTION(3, "TP_URXD1_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "URXD0"), + MTK_FUNCTION(7, "DBG_MON_A26"), + MTK_FUNCTION(8, "IOBIST63") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "SCP_SPI1_MO"), + MTK_FUNCTION(2, "SPI1_MO"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A9"), + MTK_FUNCTION(8, "IOBIST64") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "SCP_SPI1_MI"), + MTK_FUNCTION(2, "SPI1_MI"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(8, "IOBIST65") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "SCP_SPI2_CK"), + MTK_FUNCTION(2, "SPI2_CLK"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "UTXD1"), + MTK_FUNCTION(7, "DBG_MON_B13"), + MTK_FUNCTION(8, "IOBIST66") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SCP_SPI2_CS"), + MTK_FUNCTION(2, "SPI2_CSB"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "URXD1"), + MTK_FUNCTION(7, "DBG_MON_B14"), + MTK_FUNCTION(8, "IOBIST67") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SCP_SPI2_MO"), + MTK_FUNCTION(2, "SPI2_MO"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "DBG_MON_B15"), + MTK_FUNCTION(8, "IOBIST68") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "SCP_SPI2_MI"), + MTK_FUNCTION(2, "SPI2_MI"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "DBG_MON_B16"), + MTK_FUNCTION(8, "IOBIST69") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "SCP_SPI3_CK"), + MTK_FUNCTION(2, "SPI3_CLK"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(5, "TP_GPIO8_AO"), + MTK_FUNCTION(7, "DBG_MON_B17"), + MTK_FUNCTION(8, "IOBIST70") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "SCP_SPI3_CS"), + MTK_FUNCTION(2, "SPI3_CSB"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO9_AO"), + MTK_FUNCTION(7, "DBG_MON_B18"), + MTK_FUNCTION(8, "IOBIST71") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "SCP_SPI3_MO"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(5, "TP_GPIO10_AO"), + MTK_FUNCTION(7, "DBG_MON_B19"), + MTK_FUNCTION(8, "IOBIST72") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "SCP_SPI3_MI"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(5, "TP_GPIO11_AO"), + MTK_FUNCTION(7, "DBG_MON_B20"), + MTK_FUNCTION(8, "IOBIST73") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "SCP_SPI0_CK"), + MTK_FUNCTION(2, "SPI0_CLK"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "BPI_BUS14"), + MTK_FUNCTION(5, "TP_GPIO12_AO"), + MTK_FUNCTION(7, "DBG_MON_B5"), + MTK_FUNCTION(8, "IOBIST74") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SCP_SPI0_CS"), + MTK_FUNCTION(2, "SPI0_CSB"), + MTK_FUNCTION(4, "BPI_BUS15"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(7, "DBG_MON_B6"), + MTK_FUNCTION(8, "IOBIST75") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SCP_SPI0_MO"), + MTK_FUNCTION(2, "SPI0_MO"), + MTK_FUNCTION(4, "BPI_BUS16"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_B7"), + MTK_FUNCTION(8, "IOBIST76") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SCP_SPI0_MI"), + MTK_FUNCTION(2, "SPI0_MI"), + MTK_FUNCTION(4, "BPI_BUS17"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(7, "DBG_MON_B8"), + MTK_FUNCTION(8, "IOBIST77") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "MD32_0_TXD"), + MTK_FUNCTION(3, "PTA_TXD"), + MTK_FUNCTION(4, "TP_UTXD2_VCORE"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VCORE"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(7, "DBG_MON_B21"), + MTK_FUNCTION(8, "IOBIST78") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "MD32_0_RXD"), + MTK_FUNCTION(3, "PTA_RXD"), + MTK_FUNCTION(4, "TP_URXD2_VCORE"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(7, "DBG_MON_B22"), + MTK_FUNCTION(8, "IOBIST79") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(7, "DBG_MON_B23"), + MTK_FUNCTION(8, "IOBIST80") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(7, "DBG_MON_B24"), + MTK_FUNCTION(8, "IOBIST81") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_DSP_JCK"), + MTK_FUNCTION(8, "IOBIST82") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "TSFDC_VCO_RST"), + MTK_FUNCTION(8, "IOBIST83") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "TSFDC_TSSEL2"), + MTK_FUNCTION(8, "IOBIST84") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "TSFDC_TSSEL1"), + MTK_FUNCTION(8, "IOBIST85") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(6, "TSFDC_TSSEL0"), + MTK_FUNCTION(8, "IOBIST86") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "IRRX_IN"), + MTK_FUNCTION(4, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "TSFDC_RCK_SELB"), + MTK_FUNCTION(8, "IOBIST87") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(4, "CONN_DSP_L5_JINTP"), + MTK_FUNCTION(6, "TSFDC_26M"), + MTK_FUNCTION(8, "IOBIST88") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(5, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(6, "TSFDC_SDO"), + MTK_FUNCTION(8, "IOBIST89") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JCK"), + MTK_FUNCTION(5, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(6, "TSFDC_FOUT"), + MTK_FUNCTION(8, "IOBIST90") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JMS"), + MTK_FUNCTION(5, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(6, "TSFDC_SCK"), + MTK_FUNCTION(8, "IOBIST91") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JDI"), + MTK_FUNCTION(5, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(6, "TSFDC_SDI"), + MTK_FUNCTION(8, "IOBIST92") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(4, "CONN_DSP_L5_JDO"), + MTK_FUNCTION(5, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(6, "TSFDC_SCF"), + MTK_FUNCTION(8, "IOBIST93") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(6, "MD_MCIF_UTXD0"), + MTK_FUNCTION(8, "IOBIST94") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "SRCLKENA1"), + MTK_FUNCTION(6, "MD_MCIF_URXD0"), + MTK_FUNCTION(8, "IOBIST95") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_B25"), + MTK_FUNCTION(8, "IOBIST96") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(7, "DBG_MON_B26"), + MTK_FUNCTION(8, "IOBIST97") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(7, "DBG_MON_B27"), + MTK_FUNCTION(8, "IOBIST98") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "SCL6"), + MTK_FUNCTION(8, "IOBIST99") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "CONN_BPI_BUS18_ANT1"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "AGPS_SYNC"), + MTK_FUNCTION(5, "SDA6"), + MTK_FUNCTION(8, "IOBIST100") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "CONN_BPI_BUS19_ANT2"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "CONN_WF_MCU_TRST_B"), + MTK_FUNCTION(8, "IOBIST101") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "CONN_BPI_BUS20_ANT3"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_WF_MCU_TCK"), + MTK_FUNCTION(8, "IOBIST102") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "CONN_BPI_BUS21_ANT4"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_WF_MCU_TMS"), + MTK_FUNCTION(8, "IOBIST103") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_WF_MCU_TDI"), + MTK_FUNCTION(8, "IOBIST104") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_WF_MCU_TDO"), + MTK_FUNCTION(8, "IOBIST105") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(2, "CONN_BPI_BUS10"), + MTK_FUNCTION(4, "MFG_TSFDC_EN"), + MTK_FUNCTION(5, "I2SOUT4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL7"), + MTK_FUNCTION(8, "IOBIST106") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0"), + MTK_FUNCTION(4, "MFG_TSFDC_VCO_RST"), + MTK_FUNCTION(5, "I2SOUT4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL8"), + MTK_FUNCTION(8, "IOBIST107") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL2"), + MTK_FUNCTION(5, "I2SOUT4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL9"), + MTK_FUNCTION(8, "IOBIST108") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL1"), + MTK_FUNCTION(5, "I2SOUT4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL10"), + MTK_FUNCTION(8, "IOBIST109") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "MFG_TSFDC_TSSEL0"), + MTK_FUNCTION(5, "I2SIN4_BCK"), + MTK_FUNCTION(6, "ANT_SEL11"), + MTK_FUNCTION(8, "IOBIST110") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(4, "MFG_TSFDC_RCK_SELB"), + MTK_FUNCTION(5, "I2SIN4_DATA0"), + MTK_FUNCTION(6, "ANT_SEL12"), + MTK_FUNCTION(8, "IOBIST111") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "CONN_BPI_BUS6"), + MTK_FUNCTION(3, "MIPI3_D_SDATA"), + MTK_FUNCTION(4, "MFG_TSFDC_SDO"), + MTK_FUNCTION(5, "I2SIN4_DATA1"), + MTK_FUNCTION(6, "ANT_SEL13"), + MTK_FUNCTION(8, "IOBIST112") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "CONN_BPI_BUS7"), + MTK_FUNCTION(3, "MIPI3_D_SCLK"), + MTK_FUNCTION(4, "MFG_TSFDC_FOUT"), + MTK_FUNCTION(5, "I2SIN4_DATA2"), + MTK_FUNCTION(6, "ANT_SEL14"), + MTK_FUNCTION(8, "IOBIST113") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "CONN_BPI_BUS8"), + MTK_FUNCTION(3, "MIPI4_D_SDATA"), + MTK_FUNCTION(4, "SCL9"), + MTK_FUNCTION(5, "I2SIN4_DATA3"), + MTK_FUNCTION(6, "ANT_SEL15"), + MTK_FUNCTION(8, "IOBIST114") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "CONN_BPI_BUS9"), + MTK_FUNCTION(3, "MIPI4_D_SCLK"), + MTK_FUNCTION(4, "SDA9"), + MTK_FUNCTION(5, "I2SIN4_LRCK"), + MTK_FUNCTION(6, "ANT_SEL16"), + MTK_FUNCTION(8, "IOBIST115") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL"), + MTK_FUNCTION(8, "IOBIST116") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "DIGRF_IRQ"), + MTK_FUNCTION(8, "IOBIST117") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(8, "IOBIST118") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(3, "CONN_WIFI_TXD"), + MTK_FUNCTION(4, "GPS_PPS"), + MTK_FUNCTION(5, "PMSR_SMAP"), + MTK_FUNCTION(6, "AGPS_SYNC"), + MTK_FUNCTION(8, "IOBIST119") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "KPCOL0_VLP"), + MTK_FUNCTION(8, "IOBIST120") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(8, "IOBIST121") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "WATCHDOG"), + MTK_FUNCTION(8, "IOBIST122") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(8, "IOBIST123") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SRCLKENA0"), + MTK_FUNCTION(8, "IOBIST124") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "RTC32K_CK"), + MTK_FUNCTION(8, "IOBIST125") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "SPMI_M_SCL"), + MTK_FUNCTION(8, "IOBIST126") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "SPMI_M_SDA"), + MTK_FUNCTION(8, "IOBIST127") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "SPMI_P_SCL"), + MTK_FUNCTION(8, "IOBIST128") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "SPMI_P_SDA"), + MTK_FUNCTION(8, "IOBIST129") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(3, "BPI_BUS13"), + MTK_FUNCTION(8, "IOBIST130") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "SPI6_CLK"), + MTK_FUNCTION(2, "KPROW2"), + MTK_FUNCTION(3, "BPI_BUS14"), + MTK_FUNCTION(4, "CONN_BT_TXD"), + MTK_FUNCTION(5, "MD32_1_TXD"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(8, "IOBIST131") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "SPI6_CSB"), + MTK_FUNCTION(2, "KPCOL2"), + MTK_FUNCTION(3, "BPI_BUS15"), + MTK_FUNCTION(5, "MD32_1_RXD"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(8, "IOBIST132") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SPI6_MO"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "BPI_BUS16"), + MTK_FUNCTION(4, "CMFLASH2"), + MTK_FUNCTION(8, "IOBIST133") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SPI6_MI"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "BPI_BUS17"), + MTK_FUNCTION(4, "CMFLASH3"), + MTK_FUNCTION(8, "IOBIST134") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "SCP_DMIC_CLK"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "TP_GPIO13_AO"), + MTK_FUNCTION(7, "DBG_MON_A23"), + MTK_FUNCTION(8, "IOBIST135") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SCP_DMIC_DAT"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_A24"), + MTK_FUNCTION(8, "IOBIST136") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(2, "IRRX_IN"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(5, "TP_GPIO15_AO"), + MTK_FUNCTION(6, "UFS_MPHY_SCL"), + MTK_FUNCTION(8, "IOBIST137") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "UFS_MPHY_SDA"), + MTK_FUNCTION(8, "IOBIST138") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(4, "BPI_BUS18"), + MTK_FUNCTION(7, "DBG_MON_B28"), + MTK_FUNCTION(8, "IOBIST139") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(4, "BPI_BUS19"), + MTK_FUNCTION(7, "DBG_MON_B29"), + MTK_FUNCTION(8, "IOBIST140") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "SCL9"), + MTK_FUNCTION(4, "BPI_BUS20"), + MTK_FUNCTION(7, "DBG_MON_B30"), + MTK_FUNCTION(8, "IOBIST141") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "SDA9"), + MTK_FUNCTION(4, "BPI_BUS21"), + MTK_FUNCTION(7, "DBG_MON_B31"), + MTK_FUNCTION(8, "IOBIST142") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(7, "DBG_MON_B9"), + MTK_FUNCTION(8, "IOBIST143") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(7, "DBG_MON_B10"), + MTK_FUNCTION(8, "IOBIST144") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "DMIC1_CLK"), + MTK_FUNCTION(7, "DBG_MON_B11"), + MTK_FUNCTION(8, "IOBIST145") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "DMIC1_DAT"), + MTK_FUNCTION(7, "DBG_MON_B12"), + MTK_FUNCTION(8, "IOBIST146") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(7, "DBG_MON_A31"), + MTK_FUNCTION(8, "IOBIST147") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(7, "DBG_MON_A7"), + MTK_FUNCTION(8, "IOBIST148") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(8, "IOBIST149") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(8, "IOBIST150") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "SCL11"), + MTK_FUNCTION(8, "IOBIST151") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "SDA11"), + MTK_FUNCTION(8, "IOBIST152") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(7, "DBG_MON_A3"), + MTK_FUNCTION(8, "IOBIST153") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(7, "DBG_MON_A4"), + MTK_FUNCTION(8, "IOBIST154") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(7, "DBG_MON_A5"), + MTK_FUNCTION(8, "IOBIST155") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(8, "IOBIST156") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL5"), + MTK_FUNCTION(4, "TP_UCTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "DBG_MON_A27"), + MTK_FUNCTION(8, "IOBIST157") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA5"), + MTK_FUNCTION(4, "TP_URTS1_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "DBG_MON_A28"), + MTK_FUNCTION(8, "IOBIST158") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(3, "SCP_SCL4"), + MTK_FUNCTION(4, "TP_UCTS2_VLP"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A29"), + MTK_FUNCTION(8, "IOBIST159") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(3, "SCP_SDA4"), + MTK_FUNCTION(4, "TP_URTS2_VLP"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "DBG_MON_A30"), + MTK_FUNCTION(8, "IOBIST160") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SCP_SCL2"), + MTK_FUNCTION(2, "SCL10"), + MTK_FUNCTION(3, "SCP_DMIC_CLK"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "EXTIF0_PRI"), + MTK_FUNCTION(8, "IOBIST161") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "SCP_SDA2"), + MTK_FUNCTION(2, "SDA10"), + MTK_FUNCTION(3, "SCP_DMIC_DAT"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "EXTIF0_GNT_B"), + MTK_FUNCTION(8, "IOBIST162") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "SCP_SCL3"), + MTK_FUNCTION(2, "SCL12"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(8, "IOBIST163") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "SCP_SDA3"), + MTK_FUNCTION(2, "SDA12"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(8, "IOBIST164") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI0_SCLK"), + MTK_FUNCTION(3, "BPI_BUS18"), + MTK_FUNCTION(6, "ANT_SEL17"), + MTK_FUNCTION(8, "IOBIST165") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI0_SDATA"), + MTK_FUNCTION(3, "BPI_BUS19"), + MTK_FUNCTION(6, "ANT_SEL18"), + MTK_FUNCTION(8, "IOBIST166") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI1_SCLK"), + MTK_FUNCTION(3, "BPI_BUS20"), + MTK_FUNCTION(6, "ANT_SEL19"), + MTK_FUNCTION(8, "IOBIST167") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI1_SDATA"), + MTK_FUNCTION(3, "BPI_BUS21"), + MTK_FUNCTION(6, "ANT_SEL20"), + MTK_FUNCTION(8, "IOBIST168") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "MIPI2_D_SCLK"), + MTK_FUNCTION(3, "BPI_BUS10"), + MTK_FUNCTION(6, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(8, "IOBIST169") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "MIPI2_D_SDATA"), + MTK_FUNCTION(3, "BPI_BUS11"), + MTK_FUNCTION(6, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(8, "IOBIST170") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MIPI_M_SCLK"), + MTK_FUNCTION(8, "IOBIST171") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MIPI_M_SDATA"), + MTK_FUNCTION(8, "IOBIST172") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "AUD_CLK_MOSI"), + MTK_FUNCTION(8, "IOBIST173") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(8, "IOBIST174") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "AUD_DAT_MOSI0"), + MTK_FUNCTION(8, "IOBIST175") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "AUD_DAT_MOSI1"), + MTK_FUNCTION(8, "IOBIST176") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(8, "IOBIST177") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "AUD_CLK_MISO"), + MTK_FUNCTION(8, "IOBIST178") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "VOW_DAT_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO0"), + MTK_FUNCTION(8, "IOBIST179") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "VOW_CLK_MISO"), + MTK_FUNCTION(3, "AUD_DAT_MISO1"), + MTK_FUNCTION(8, "IOBIST180") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(8, "IOBIST181") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(8, "IOBIST182") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(8, "IOBIST183") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(8, "IOBIST184") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(8, "IOBIST185") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(8, "IOBIST186") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(8, "IOBIST187") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "CONN_WF_CTRL0"), + MTK_FUNCTION(8, "IOBIST188") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(8, "IOBIST189") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(8, "IOBIST190") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "CONN_TOP_CLK_2"), + MTK_FUNCTION(8, "IOBIST191") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "CONN_TOP_DATA_2"), + MTK_FUNCTION(8, "IOBIST192") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "CONN_HRST_B_2"), + MTK_FUNCTION(8, "IOBIST193") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(2, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(8, "IOBIST194") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(2, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(3, "ANT_SEL21"), + MTK_FUNCTION(5, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(8, "IOBIST195") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "PAD_RESET_DRAM_0"), + MTK_FUNCTION(8, "IOBIST196") + ), + MTK_PIN_VEINT(197), + MTK_PIN_VEINT(198), + MTK_PIN_VEINT(199), + MTK_PIN_VEINT(200), + MTK_PIN_VEINT(201), + MTK_PIN_VEINT(202), + MTK_PIN_VEINT(203), + MTK_PIN_VEINT(204), + MTK_PIN_VEINT(205), + MTK_PIN_VEINT(206), + MTK_PIN_VEINT(207), + MTK_PIN_VEINT(208), + MTK_PIN_VEINT(209), + MTK_PIN_VEINT(210), + MTK_PIN_VEINT(211), + MTK_PIN_VEINT(212), + MTK_PIN_VEINT(213), + MTK_PIN_VEINT(214), + MTK_PIN_VEINT(215), + MTK_PIN_VEINT(216), +}; + +static struct mtk_eint_pin eint_pins_mt6858[] = { + MTK_EINT_PIN(0, 2, 0, 1), + MTK_EINT_PIN(1, 2, 1, 1), + MTK_EINT_PIN(2, 2, 2, 1), + MTK_EINT_PIN(3, 2, 3, 1), + MTK_EINT_PIN(4, 2, 4, 1), + MTK_EINT_PIN(5, 2, 5, 1), + MTK_EINT_PIN(6, 2, 6, 1), + MTK_EINT_PIN(7, 2, 7, 1), + MTK_EINT_PIN(8, 0, 0, 1), + MTK_EINT_PIN(9, 0, 1, 1), + MTK_EINT_PIN(10, 0, 2, 1), + MTK_EINT_PIN(11, 0, 3, 1), + MTK_EINT_PIN(12, 0, 4, 1), + MTK_EINT_PIN(13, 1, 0, 1), + MTK_EINT_PIN(14, 1, 1, 1), + MTK_EINT_PIN(15, 1, 2, 1), + MTK_EINT_PIN(16, 1, 3, 1), + MTK_EINT_PIN(17, 1, 4, 1), + MTK_EINT_PIN(18, 1, 5, 1), + MTK_EINT_PIN(19, 1, 6, 1), + MTK_EINT_PIN(20, 1, 7, 1), + MTK_EINT_PIN(21, 0, 5, 1), + MTK_EINT_PIN(22, 0, 6, 1), + MTK_EINT_PIN(23, 2, 8, 1), + MTK_EINT_PIN(24, 0, 7, 1), + MTK_EINT_PIN(25, 2, 18, 0), + MTK_EINT_PIN(26, 0, 8, 1), + MTK_EINT_PIN(27, 2, 9, 1), + MTK_EINT_PIN(28, 2, 10, 1), + MTK_EINT_PIN(29, 2, 11, 1), + MTK_EINT_PIN(30, 2, 12, 1), + MTK_EINT_PIN(31, 2, 13, 1), + MTK_EINT_PIN(32, 2, 14, 1), + MTK_EINT_PIN(33, 2, 15, 1), + MTK_EINT_PIN(34, 2, 16, 1), + MTK_EINT_PIN(35, 0, 9, 1), + MTK_EINT_PIN(36, 2, 17, 1), + MTK_EINT_PIN(37, 2, 19, 0), + MTK_EINT_PIN(38, 2, 20, 0), + MTK_EINT_PIN(39, 2, 21, 0), + MTK_EINT_PIN(40, 0, 10, 0), + MTK_EINT_PIN(41, 0, 11, 0), + MTK_EINT_PIN(42, 0, 12, 0), + MTK_EINT_PIN(43, 0, 13, 0), + MTK_EINT_PIN(44, 0, 14, 0), + MTK_EINT_PIN(45, 0, 15, 0), + MTK_EINT_PIN(46, 0, 16, 0), + MTK_EINT_PIN(47, 0, 17, 0), + MTK_EINT_PIN(48, 0, 18, 0), + MTK_EINT_PIN(49, 0, 19, 0), + MTK_EINT_PIN(50, 0, 20, 0), + MTK_EINT_PIN(51, 0, 21, 0), + MTK_EINT_PIN(52, 0, 22, 0), + MTK_EINT_PIN(53, 0, 23, 0), + MTK_EINT_PIN(54, 0, 24, 0), + MTK_EINT_PIN(55, 0, 25, 0), + MTK_EINT_PIN(56, 0, 26, 0), + MTK_EINT_PIN(57, 0, 27, 0), + MTK_EINT_PIN(58, 0, 28, 0), + MTK_EINT_PIN(59, 0, 29, 0), + MTK_EINT_PIN(60, 0, 30, 0), + MTK_EINT_PIN(61, 0, 31, 0), + MTK_EINT_PIN(62, 2, 22, 0), + MTK_EINT_PIN(63, 2, 23, 0), + MTK_EINT_PIN(64, 2, 24, 0), + MTK_EINT_PIN(65, 2, 25, 0), + MTK_EINT_PIN(66, 0, 32, 0), + MTK_EINT_PIN(67, 0, 33, 0), + MTK_EINT_PIN(68, 0, 34, 0), + MTK_EINT_PIN(69, 0, 35, 0), + MTK_EINT_PIN(70, 0, 36, 0), + MTK_EINT_PIN(71, 0, 37, 0), + MTK_EINT_PIN(72, 0, 38, 0), + MTK_EINT_PIN(73, 0, 39, 0), + MTK_EINT_PIN(74, 0, 40, 0), + MTK_EINT_PIN(75, 0, 41, 0), + MTK_EINT_PIN(76, 0, 42, 0), + MTK_EINT_PIN(77, 0, 43, 0), + MTK_EINT_PIN(78, 0, 44, 0), + MTK_EINT_PIN(79, 0, 45, 0), + MTK_EINT_PIN(80, 0, 46, 0), + MTK_EINT_PIN(81, 0, 47, 0), + MTK_EINT_PIN(82, 2, 26, 0), + MTK_EINT_PIN(83, 2, 27, 0), + MTK_EINT_PIN(84, 2, 28, 0), + MTK_EINT_PIN(85, 2, 29, 0), + MTK_EINT_PIN(86, 2, 30, 0), + MTK_EINT_PIN(87, 2, 31, 0), + MTK_EINT_PIN(88, 0, 48, 0), + MTK_EINT_PIN(89, 0, 49, 0), + MTK_EINT_PIN(90, 0, 50, 0), + MTK_EINT_PIN(91, 0, 51, 0), + MTK_EINT_PIN(92, 0, 52, 0), + MTK_EINT_PIN(93, 0, 53, 0), + MTK_EINT_PIN(94, 0, 54, 0), + MTK_EINT_PIN(95, 0, 55, 0), + MTK_EINT_PIN(96, 0, 56, 0), + MTK_EINT_PIN(97, 0, 57, 0), + MTK_EINT_PIN(98, 0, 58, 0), + MTK_EINT_PIN(99, 2, 32, 0), + MTK_EINT_PIN(100, 2, 33, 0), + MTK_EINT_PIN(101, 2, 34, 0), + MTK_EINT_PIN(102, 2, 35, 0), + MTK_EINT_PIN(103, 2, 36, 0), + MTK_EINT_PIN(104, 2, 37, 0), + MTK_EINT_PIN(105, 2, 38, 0), + MTK_EINT_PIN(106, 0, 59, 0), + MTK_EINT_PIN(107, 0, 60, 0), + MTK_EINT_PIN(108, 0, 61, 0), + MTK_EINT_PIN(109, 0, 62, 0), + MTK_EINT_PIN(110, 0, 63, 0), + MTK_EINT_PIN(111, 0, 64, 0), + MTK_EINT_PIN(112, 0, 65, 0), + MTK_EINT_PIN(113, 0, 66, 0), + MTK_EINT_PIN(114, 0, 67, 0), + MTK_EINT_PIN(115, 0, 68, 0), + MTK_EINT_PIN(116, 0, 69, 0), + MTK_EINT_PIN(117, 0, 70, 0), + MTK_EINT_PIN(118, 0, 71, 0), + MTK_EINT_PIN(119, 0, 72, 0), + MTK_EINT_PIN(120, 0, 73, 0), + MTK_EINT_PIN(121, 0, 74, 0), + MTK_EINT_PIN(122, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(123, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(124, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(125, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(126, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(127, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(128, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(129, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(130, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(131, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(132, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(133, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(134, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(135, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(136, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(137, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(138, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(139, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(140, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(141, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(142, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(143, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(144, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(145, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(146, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(147, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(148, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(149, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(150, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(151, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(152, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(153, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(154, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(155, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(156, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(157, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(158, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(159, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(160, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(161, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(162, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(163, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(164, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(165, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(166, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(167, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(168, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(169, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(170, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(171, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(172, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(173, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(174, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(175, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(176, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(177, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(178, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(179, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(180, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(181, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(182, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(183, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(184, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(185, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(186, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(187, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(188, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(189, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(190, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(191, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(192, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(193, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(194, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(195, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(196, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(197, 3, 0, 0), + MTK_EINT_PIN(198, 3, 1, 0), + MTK_EINT_PIN(199, 3, 2, 0), + MTK_EINT_PIN(200, 3, 3, 0), + MTK_EINT_PIN(201, 3, 4, 0), + MTK_EINT_PIN(202, 3, 5, 0), + MTK_EINT_PIN(203, 3, 6, 0), + MTK_EINT_PIN(204, 3, 7, 0), + MTK_EINT_PIN(205, 3, 8, 0), + MTK_EINT_PIN(206, 3, 9, 0), + MTK_EINT_PIN(207, 3, 10, 0), + MTK_EINT_PIN(208, 3, 11, 0), + MTK_EINT_PIN(209, 3, 12, 0), + MTK_EINT_PIN(210, 3, 13, 0), + MTK_EINT_PIN(211, 3, 14, 0), + MTK_EINT_PIN(212, 3, 15, 0), + MTK_EINT_PIN(213, 3, 16, 0), + MTK_EINT_PIN(214, 3, 17, 0), + MTK_EINT_PIN(215, 3, 18, 0), + MTK_EINT_PIN(216, 3, 19, 0), +}; + +#endif /* __PINCTRL_MTK_MT6858_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h index 39e17532c460..3f519aa01cfd 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018 MediaTek Inc. * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtmips.c b/drivers/pinctrl/mediatek/pinctrl-mtmips.c index efd77b6c56a1..b2d7a79ff9cc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtmips.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c @@ -349,3 +349,7 @@ int mtmips_pinctrl_init(struct platform_device *pdev, return PTR_ERR_OR_ZERO(dev); } +EXPORT_SYMBOL_NS_GPL(mtmips_pinctrl_init, "MTK_PINCTRL"); + +MODULE_DESCRIPTION("MediaTek MIPS Pinctrl Common Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 6bf37d8085fa..09098b68f725 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -771,7 +771,6 @@ static const struct pinmux_ops mtk_pmxops = { .get_function_name = mtk_pmx_get_func_name, .get_function_groups = mtk_pmx_get_func_groups, .set_mux = mtk_pmx_set_mux, - .gpio_set_direction = mtk_pinmux_gpio_set_direction, .gpio_request_enable = mtk_pinmux_gpio_request_enable, }; @@ -886,19 +885,22 @@ static int mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) { - return pinctrl_gpio_direction_input(chip, gpio); + struct mtk_pinctrl *hw = gpiochip_get_data(chip); + + return mtk_pinmux_gpio_set_direction(hw->pctrl, NULL, gpio, true); } static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, int value) { + struct mtk_pinctrl *hw = gpiochip_get_data(chip); int ret; ret = mtk_gpio_set(chip, gpio, value); if (ret) return ret; - return pinctrl_gpio_direction_output(chip, gpio); + return mtk_pinmux_gpio_set_direction(hw->pctrl, NULL, gpio, false); } static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) @@ -955,7 +957,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->base = -1; chip->ngpio = hw->soc->npins; - ret = gpiochip_add_data(chip, hw); + ret = devm_gpiochip_add_data(hw->dev, chip, hw); if (ret < 0) return ret; diff --git a/drivers/pinctrl/mediatek/pinctrl-rt2880.c b/drivers/pinctrl/mediatek/pinctrl-rt2880.c index e0366721a515..e7099325c5ef 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -59,3 +59,7 @@ static int __init rt2880_pinctrl_init(void) return platform_driver_register(&rt2880_pinctrl_driver); } core_initcall_sync(rt2880_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek RT2880 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt305x.c b/drivers/pinctrl/mediatek/pinctrl-rt305x.c index 77bd4d1f6122..fa6407e86f79 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -138,3 +138,7 @@ static int __init rt305x_pinctrl_init(void) return platform_driver_register(&rt305x_pinctrl_driver); } core_initcall_sync(rt305x_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek RT305X Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/mediatek/pinctrl-rt3883.c b/drivers/pinctrl/mediatek/pinctrl-rt3883.c index eeaf344c3647..838bf811cd0c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -106,3 +106,7 @@ static int __init rt3883_pinctrl_init(void) return platform_driver_register(&rt3883_pinctrl_driver); } core_initcall_sync(rt3883_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek RT3883 Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("MTK_PINCTRL"); diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c index e2293a872dcb..39eb8cc7fc0d 100644 --- a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -55,14 +55,18 @@ struct aml_pio_control { * partial bank(subordinate) pins mux config use other bank(main) mux registgers * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0 * m_bit_offs: bit offset the main bank mux register + * s_bit_offs: start bit that subordinate bank use mux register * sid: start pin_id of subordinate bank * eid: end pin_id of subordinate bank + * next: subordinate bank reused multiple other bank groups. */ struct multi_mux { unsigned int m_bank_id; unsigned int m_bit_offs; + unsigned int s_bit_offs; unsigned int sid; unsigned int eid; + const struct multi_mux *next; }; struct aml_pctl_data { @@ -124,12 +128,51 @@ static const char *aml_bank_name[31] = { "GPIOCC", "TEST_N", "ANALOG" }; +static const struct multi_mux multi_mux_a9[] = { + { + .m_bank_id = AMLOGIC_GPIO_C, + .m_bit_offs = 4, + .s_bit_offs = 0, + .sid = (AMLOGIC_GPIO_D << 8) + 16, + .eid = (AMLOGIC_GPIO_D << 8) + 16, + .next = &multi_mux_a9[1], + }, { + .m_bank_id = AMLOGIC_GPIO_AO, + .m_bit_offs = 0, + .s_bit_offs = 52, + .sid = (AMLOGIC_GPIO_D << 8) + 17, + .eid = (AMLOGIC_GPIO_D << 8) + 17, + .next = NULL, + }, { + .m_bank_id = AMLOGIC_GPIO_A, + .m_bit_offs = 0, + .s_bit_offs = 80, + .sid = (AMLOGIC_GPIO_Y << 8) + 8, + .eid = (AMLOGIC_GPIO_Y << 8) + 9, + .next = NULL, + }, { + .m_bank_id = AMLOGIC_GPIO_CC, + .m_bit_offs = 24, + .s_bit_offs = 0, + .sid = (AMLOGIC_GPIO_X << 8) + 16, + .eid = (AMLOGIC_GPIO_X << 8) + 17, + .next = NULL, + }, +}; + +static const struct aml_pctl_data a9_priv_data = { + .number = ARRAY_SIZE(multi_mux_a9), + .p_mux = multi_mux_a9, +}; + static const struct multi_mux multi_mux_s7[] = { { .m_bank_id = AMLOGIC_GPIO_CC, .m_bit_offs = 24, + .s_bit_offs = 0, .sid = (AMLOGIC_GPIO_X << 8) + 16, .eid = (AMLOGIC_GPIO_X << 8) + 19, + .next = NULL, }, }; @@ -142,13 +185,17 @@ static const struct multi_mux multi_mux_s6[] = { { .m_bank_id = AMLOGIC_GPIO_CC, .m_bit_offs = 24, + .s_bit_offs = 0, .sid = (AMLOGIC_GPIO_X << 8) + 16, .eid = (AMLOGIC_GPIO_X << 8) + 19, + .next = NULL, }, { .m_bank_id = AMLOGIC_GPIO_F, .m_bit_offs = 4, + .s_bit_offs = 0, .sid = (AMLOGIC_GPIO_D << 8) + 6, .eid = (AMLOGIC_GPIO_D << 8) + 6, + .next = NULL, }, }; @@ -177,31 +224,34 @@ static int aml_pctl_set_function(struct aml_pinctrl *info, struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int shift; int reg; - int i; + int i, loop_count; unsigned int offset = bank->mux_bit_offs; const struct multi_mux *p_mux; /* peculiar mux reg set */ - if (bank->p_mux) { - p_mux = bank->p_mux; + loop_count = 10; + p_mux = bank->p_mux; + while (p_mux && loop_count) { if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) { bank = NULL; for (i = 0; i < info->nbanks; i++) { if (info->banks[i].bank_id == p_mux->m_bank_id) { bank = &info->banks[i]; - break; + break; } } if (!bank || !bank->reg_mux) return -EINVAL; - shift = (pin_id - p_mux->sid) << 2; + shift = ((pin_id - p_mux->sid) << 2) + p_mux->s_bit_offs; reg = (shift / 32) * 4; offset = shift % 32; return regmap_update_bits(bank->reg_mux, reg, 0xf << offset, (func & 0xf) << offset); } + p_mux = p_mux->next; + loop_count--; } /* normal mux reg set */ @@ -250,7 +300,7 @@ static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, int i; for (i = 0; i < group->npins; i++) { - range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]); + range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, group->pins[i]); aml_pctl_set_function(info, range, group->pins[i], group->func[i]); } @@ -292,7 +342,7 @@ static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) { struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(info->pctl, pin); + pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int reg, bit, val; int ret, conf; @@ -326,7 +376,7 @@ static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, u16 *drive_strength_ua) { struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(info->pctl, pin); + pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int reg, bit; unsigned int val; @@ -365,7 +415,7 @@ static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, unsigned int reg_type) { struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(info->pctl, pin); + pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int reg, bit, val; int ret; @@ -419,9 +469,15 @@ static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, break; case PIN_CONFIG_OUTPUT_ENABLE: ret = aml_pinconf_get_output(info, pin); - if (ret <= 0) + if (ret < 0) + return -EINVAL; + arg = ret; + break; + case PIN_CONFIG_INPUT_ENABLE: + ret = aml_pinconf_get_output(info, pin); + if (ret < 0) return -EINVAL; - arg = 1; + arg = !ret; break; case PIN_CONFIG_LEVEL: ret = aml_pinconf_get_output(info, pin); @@ -449,7 +505,7 @@ static int aml_pinconf_disable_bias(struct aml_pinctrl *info, unsigned int pin) { struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(info->pctl, pin); + pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int reg, bit = 0; @@ -462,7 +518,7 @@ static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, bool pull_up) { struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(info->pctl, pin); + pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int reg, bit, val = 0; int ret; @@ -484,7 +540,7 @@ static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, u16 drive_strength_ua) { struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(info->pctl, pin); + pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int reg, bit, ds_val; @@ -519,7 +575,7 @@ static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, bool arg) { struct pinctrl_gpio_range *range = - pinctrl_find_gpio_range_from_pin(info->pctl, pin); + pinctrl_find_gpio_range_from_pin_nolock(info->pctl, pin); struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); unsigned int reg, bit; @@ -548,11 +604,11 @@ static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, { int ret; - ret = aml_pinconf_set_output(info, pin, true); + ret = aml_pinconf_set_drive(info, pin, high); if (ret) return ret; - return aml_pinconf_set_drive(info, pin, high); + return aml_pinconf_set_output(info, pin, true); } static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, @@ -569,6 +625,7 @@ static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, switch (param) { case PIN_CONFIG_DRIVE_STRENGTH_UA: case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: case PIN_CONFIG_LEVEL: arg = pinconf_to_config_argument(configs[i]); break; @@ -593,6 +650,9 @@ static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, case PIN_CONFIG_OUTPUT_ENABLE: ret = aml_pinconf_set_output(info, pin, arg); break; + case PIN_CONFIG_INPUT_ENABLE: + ret = aml_pinconf_set_output(info, pin, !arg); + break; case PIN_CONFIG_LEVEL: ret = aml_pinconf_set_output_drive(info, pin, arg); break; @@ -921,15 +981,14 @@ static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, unsigned int bit, reg; int ret; - aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); - ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); + aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); + ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), + value ? BIT(bit) : 0); if (ret < 0) return ret; - aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); - - return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), - value ? BIT(bit) : 0); + aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); } static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) @@ -1159,6 +1218,7 @@ static int aml_pctl_probe(struct platform_device *pdev) static const struct of_device_id aml_pctl_of_match[] = { { .compatible = "amlogic,pinctrl-a4", }, + { .compatible = "amlogic,pinctrl-a9", .data = &a9_priv_data, }, { .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, }, { .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, }, { /* sentinel */ } diff --git a/drivers/pinctrl/meson/pinctrl-meson-s4.c b/drivers/pinctrl/meson/pinctrl-meson-s4.c index 872948699e9f..365dafe457a9 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-s4.c +++ b/drivers/pinctrl/meson/pinctrl-meson-s4.c @@ -854,7 +854,7 @@ static const char * const i2c1_groups[] = { static const char * const i2c2_groups[] = { "i2c2_sda_d", "i2c2_scl_d", "i2c2_sda_h8", "i2c2_scl_h9", - "i2c2_sda_h0", "i2c2_scl_h1l," + "i2c2_sda_h0", "i2c2_scl_h1", }; static const char * const i2c3_groups[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 4507dc8b5563..9fc30aee96a5 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -252,11 +252,11 @@ static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, { int ret; - ret = meson_pinconf_set_output(pc, pin, true); + ret = meson_pinconf_set_drive(pc, pin, high); if (ret) return ret; - return meson_pinconf_set_drive(pc, pin, high); + return meson_pinconf_set_output(pc, pin, true); } static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, @@ -498,9 +498,9 @@ static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, break; case PIN_CONFIG_OUTPUT_ENABLE: ret = meson_pinconf_get_output(pc, pin); - if (ret <= 0) + if (ret < 0) return -EINVAL; - arg = 1; + arg = ret; break; case PIN_CONFIG_LEVEL: ret = meson_pinconf_get_output(pc, pin); @@ -619,7 +619,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.set = meson_gpio_set; pc->chip.base = -1; pc->chip.ngpio = pc->data->num_pins; - pc->chip.can_sleep = true; + pc->chip.can_sleep = false; ret = gpiochip_add_data(&pc->chip, pc); if (ret) { diff --git a/drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c index 1b060a038920..a390caa83181 100644 --- a/drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c +++ b/drivers/pinctrl/microchip/pinctrl-mpfs-iomux0.c @@ -4,7 +4,6 @@ #include <linux/cleanup.h> #include <linux/module.h> #include <linux/mfd/syscon.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c index 15d73ea1028c..92d38e5336de 100644 --- a/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c +++ b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c @@ -3,7 +3,6 @@ #include <linux/bitfield.h> #include <linux/module.h> #include <linux/mfd/syscon.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> @@ -87,7 +86,7 @@ static struct mpfs_pinctrl_bank_voltage mpfs_pinctrl_bank_voltages[8] = { { .uv = 1800000, .val = 4 }, { .uv = 2500000, .val = 6 }, { .uv = 3300000, .val = 8 }, - { .uv = 0, .val = 0x3f }, // pin unused + { .uv = 0, .val = 0xf }, // pin unused }; static int mpfs_pinctrl_get_drive_strength_ma(u32 drive_strength) @@ -157,10 +156,10 @@ static void mpfs_pinctrl_set_bank_voltage(struct mpfs_pinctrl *pctrl, unsigned i u32 val = FIELD_PREP(MPFS_PINCTRL_BANK_VOLTAGE_MASK, bank_voltage); if (pin < MPFS_PINCTRL_BANK2_START) - regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR, + regmap_update_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR, MPFS_PINCTRL_BANK_VOLTAGE_MASK, val); else - regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR, + regmap_update_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR, MPFS_PINCTRL_BANK_VOLTAGE_MASK, val); } diff --git a/drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c b/drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c index a0b3e839cf3b..633ef40e1c27 100644 --- a/drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c +++ b/drivers/pinctrl/microchip/pinctrl-pic64gx-gpio2.c @@ -3,7 +3,6 @@ #include <linux/bitfield.h> #include <linux/module.h> #include <linux/mfd/syscon.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c index f01344201628..dafa85c105a1 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c +++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c @@ -1014,7 +1014,8 @@ static int ma35_pinctrl_parse_groups(struct fwnode_handle *fwnode, struct group_ grp->data = pin; for (i = 0, j = 0; i < count; i += 3, j++) { - pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE; + pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE + + (elems[i + 1] >= 8 ? 4 : 0); pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32; pin->muxval = elems[i + 2]; pin->configs = configs; diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c index eafa06ca0879..132615959e67 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c +++ b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c @@ -7,7 +7,6 @@ */ #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> @@ -113,6 +112,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x0, "GPA14"), MA35_MUX(0x2, "UART7_RXD"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL3_DM"), MA35_MUX(0x6, "NAND_nWP"), MA35_MUX(0x7, "EBI_AD14"), MA35_MUX(0x9, "EBI_ADR14")), @@ -123,6 +123,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x3, "UART6_RXD"), MA35_MUX(0x4, "I2C4_SDA"), MA35_MUX(0x5, "CAN2_RXD"), + MA35_MUX(0x6, "USBHL0_DM"), MA35_MUX(0x7, "EBI_ALE"), MA35_MUX(0x9, "QEI0_A"), MA35_MUX(0xb, "TM1"), @@ -187,6 +188,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x1, "EPWM2_CH5"), MA35_MUX(0x2, "UART2_RXD"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL2_DM"), MA35_MUX(0x5, "SPI0_MOSI"), MA35_MUX(0x6, "EBI_MCLK"), MA35_MUX(0x7, "CCAP1_VSYNC"), @@ -202,6 +204,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x1, "EPWM2_BRAKE1"), MA35_MUX(0x2, "UART2_TXD"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL2_DP"), MA35_MUX(0x5, "SPI0_MISO"), MA35_MUX(0x6, "I2S1_MCLK"), MA35_MUX(0x7, "CCAP1_SFIELD"), @@ -220,6 +223,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x4, "I2C3_SDA"), MA35_MUX(0x5, "CAN2_RXD"), MA35_MUX(0x6, "I2S1_LRCK"), + MA35_MUX(0x7, "USBHL1_DM"), MA35_MUX(0x8, "ADC0_CH4"), MA35_MUX(0x9, "EBI_ADR16"), MA35_MUX(0xe, "ECAP2_IC0")), @@ -231,6 +235,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x4, "I2C3_SCL"), MA35_MUX(0x5, "CAN2_TXD"), MA35_MUX(0x6, "I2S1_BCLK"), + MA35_MUX(0x7, "USBHL1_DP"), MA35_MUX(0x8, "ADC0_CH5"), MA35_MUX(0x9, "EBI_ADR17"), MA35_MUX(0xe, "ECAP2_IC1")), @@ -239,6 +244,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x1, "EPWM2_CH2"), MA35_MUX(0x2, "UART4_RXD"), MA35_MUX(0x3, "CAN1_RXD"), + MA35_MUX(0x4, "USBHL3_DM"), MA35_MUX(0x5, "I2C4_SDA"), MA35_MUX(0x6, "I2S1_DI"), MA35_MUX(0x8, "ADC0_CH6"), @@ -249,6 +255,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x1, "EPWM2_CH3"), MA35_MUX(0x2, "UART4_TXD"), MA35_MUX(0x3, "CAN1_TXD"), + MA35_MUX(0x4, "USBHL3_DP"), MA35_MUX(0x5, "I2C4_SCL"), MA35_MUX(0x6, "I2S1_DO"), MA35_MUX(0x8, "ADC0_CH7"), @@ -264,10 +271,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_PIN(34, PC2, 0x90, 0x8, MA35_MUX(0x0, "GPC2"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL4_DM"), MA35_MUX(0x6, "SD0_DAT0/eMMC0_DAT0")), MA35_PIN(35, PC3, 0x90, 0xc, MA35_MUX(0x0, "GPC3"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL4_DP"), MA35_MUX(0x6, "SD0_DAT1/eMMC0_DAT1")), MA35_PIN(36, PC4, 0x90, 0x10, MA35_MUX(0x0, "GPC4"), @@ -280,65 +289,100 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_PIN(38, PC6, 0x90, 0x18, MA35_MUX(0x0, "GPC6"), MA35_MUX(0x3, "CAN1_RXD"), + MA35_MUX(0x4, "USBHL5_DM"), MA35_MUX(0x6, "SD0_nCD")), MA35_PIN(39, PC7, 0x90, 0x1c, MA35_MUX(0x0, "GPC7"), MA35_MUX(0x3, "CAN1_TXD"), + MA35_MUX(0x4, "USBHL5_DP"), MA35_MUX(0x6, "SD0_WP")), - MA35_PIN(40, PC12, 0x94, 0x10, + MA35_PIN(40, PC8, 0x94, 0x0, + MA35_MUX(0x0, "GPC8"), + MA35_MUX(0x1, "EPWM2_CH0"), + MA35_MUX(0x2, "UART10_nCTS"), + MA35_MUX(0x3, "UART9_RXD"), + MA35_MUX(0x4, "I2C0_SDA"), + MA35_MUX(0x5, "SPI1_SS0"), + MA35_MUX(0x6, "SD0_DAT4/eMMC0_DAT4")), + MA35_PIN(41, PC9, 0x94, 0x4, + MA35_MUX(0x0, "GPC9"), + MA35_MUX(0x1, "EPWM2_CH1"), + MA35_MUX(0x2, "UART10_nRTS"), + MA35_MUX(0x3, "UART9_TXD"), + MA35_MUX(0x4, "I2C0_SCL"), + MA35_MUX(0x5, "SPI1_CLK"), + MA35_MUX(0x6, "SD0_DAT5/eMMC0_DAT5")), + MA35_PIN(42, PC10, 0x94, 0x8, + MA35_MUX(0x0, "GPC10"), + MA35_MUX(0x1, "EPWM2_CH2"), + MA35_MUX(0x2, "UART10_RXD"), + MA35_MUX(0x3, "CAN2_RXD"), + MA35_MUX(0x4, "USBHL0_DM"), + MA35_MUX(0x5, "SPI1_MOSI"), + MA35_MUX(0x6, "SD0_DAT6/eMMC0_DAT6")), + MA35_PIN(43, PC11, 0x94, 0xc, + MA35_MUX(0x0, "GPC11"), + MA35_MUX(0x1, "EPWM2_CH3"), + MA35_MUX(0x2, "UART10_TXD"), + MA35_MUX(0x3, "CAN2_TXD"), + MA35_MUX(0x4, "USBHL0_DP"), + MA35_MUX(0x5, "SPI1_MISO"), + MA35_MUX(0x6, "SD0_DAT7/eMMC0_DAT7")), + MA35_PIN(44, PC12, 0x94, 0x10, MA35_MUX(0x0, "GPC12"), MA35_MUX(0x2, "UART12_nCTS"), MA35_MUX(0x3, "UART11_RXD"), MA35_MUX(0x6, "LCM_DATA16")), - MA35_PIN(41, PC13, 0x94, 0x14, + MA35_PIN(45, PC13, 0x94, 0x14, MA35_MUX(0x0, "GPC13"), MA35_MUX(0x2, "UART12_nRTS"), MA35_MUX(0x3, "UART11_TXD"), MA35_MUX(0x6, "LCM_DATA17")), - MA35_PIN(42, PC14, 0x94, 0x18, + MA35_PIN(46, PC14, 0x94, 0x18, MA35_MUX(0x0, "GPC14"), MA35_MUX(0x2, "UART12_RXD"), MA35_MUX(0x6, "LCM_DATA18")), - MA35_PIN(43, PC15, 0x94, 0x1c, + MA35_PIN(47, PC15, 0x94, 0x1c, MA35_MUX(0x0, "GPC15"), MA35_MUX(0x2, "UART12_TXD"), MA35_MUX(0x6, "LCM_DATA19"), MA35_MUX(0x7, "LCM_MPU_TE"), MA35_MUX(0x8, "LCM_MPU_VSYNC")), - MA35_PIN(44, PD0, 0x98, 0x0, + MA35_PIN(48, PD0, 0x98, 0x0, MA35_MUX(0x0, "GPD0"), MA35_MUX(0x2, "UART3_nCTS"), MA35_MUX(0x3, "UART4_RXD"), MA35_MUX(0x5, "QSPI0_SS0")), - MA35_PIN(45, PD1, 0x98, 0x4, + MA35_PIN(49, PD1, 0x98, 0x4, MA35_MUX(0x0, "GPD1"), MA35_MUX(0x2, "UART3_nRTS"), MA35_MUX(0x3, "UART4_TXD"), MA35_MUX(0x5, "QSPI0_CLK")), - MA35_PIN(46, PD2, 0x98, 0x8, + MA35_PIN(50, PD2, 0x98, 0x8, MA35_MUX(0x0, "GPD2"), MA35_MUX(0x2, "UART3_RXD"), MA35_MUX(0x5, "QSPI0_MOSI0")), - MA35_PIN(47, PD3, 0x98, 0xc, + MA35_PIN(51, PD3, 0x98, 0xc, MA35_MUX(0x0, "GPD3"), MA35_MUX(0x2, "UART3_TXD"), MA35_MUX(0x5, "QSPI0_MISO0")), - MA35_PIN(48, PD4, 0x98, 0x10, + MA35_PIN(52, PD4, 0x98, 0x10, MA35_MUX(0x0, "GPD4"), MA35_MUX(0x2, "UART1_nCTS"), MA35_MUX(0x3, "UART2_RXD"), MA35_MUX(0x4, "I2C2_SDA"), MA35_MUX(0x5, "QSPI0_MOSI1")), - MA35_PIN(49, PD5, 0x98, 0x14, + MA35_PIN(53, PD5, 0x98, 0x14, MA35_MUX(0x0, "GPD5"), MA35_MUX(0x2, "UART1_nRTS"), MA35_MUX(0x3, "UART2_TXD"), MA35_MUX(0x4, "I2C2_SCL"), MA35_MUX(0x5, "QSPI0_MISO1")), - MA35_PIN(50, PD6, 0x98, 0x18, + MA35_PIN(54, PD6, 0x98, 0x18, MA35_MUX(0x0, "GPD6"), MA35_MUX(0x1, "EPWM0_SYNC_IN"), MA35_MUX(0x2, "UART1_RXD"), + MA35_MUX(0x4, "USBHL3_DM"), MA35_MUX(0x5, "QSPI1_MOSI1"), MA35_MUX(0x6, "I2C0_SDA"), MA35_MUX(0x7, "I2S0_MCLK"), @@ -346,10 +390,11 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "EBI_AD5"), MA35_MUX(0xa, "SPI3_SS1"), MA35_MUX(0xb, "TRACE_CLK")), - MA35_PIN(51, PD7, 0x98, 0x1c, + MA35_PIN(55, PD7, 0x98, 0x1c, MA35_MUX(0x0, "GPD7"), MA35_MUX(0x1, "EPWM0_SYNC_OUT"), MA35_MUX(0x2, "UART1_TXD"), + MA35_MUX(0x4, "USBHL3_DP"), MA35_MUX(0x5, "QSPI1_MISO1"), MA35_MUX(0x6, "I2C0_SCL"), MA35_MUX(0x7, "I2S1_MCLK"), @@ -357,7 +402,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "EBI_AD6"), MA35_MUX(0xa, "SC1_nCD"), MA35_MUX(0xb, "EADC0_ST")), - MA35_PIN(52, PD8, 0x9c, 0x0, + MA35_PIN(56, PD8, 0x9c, 0x0, MA35_MUX(0x0, "GPD8"), MA35_MUX(0x1, "EPWM0_BRAKE0"), MA35_MUX(0x2, "UART16_nCTS"), @@ -368,7 +413,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "EBI_AD7"), MA35_MUX(0xa, "SC1_CLK"), MA35_MUX(0xb, "TM0")), - MA35_PIN(53, PD9, 0x9c, 0x4, + MA35_PIN(57, PD9, 0x9c, 0x4, MA35_MUX(0x0, "GPD9"), MA35_MUX(0x1, "EPWM0_BRAKE1"), MA35_MUX(0x2, "UART16_nRTS"), @@ -379,7 +424,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "EBI_AD8"), MA35_MUX(0xa, "SC1_DAT"), MA35_MUX(0xb, "TM0_EXT")), - MA35_PIN(54, PD10, 0x9c, 0x8, + MA35_PIN(58, PD10, 0x9c, 0x8, MA35_MUX(0x0, "GPD10"), MA35_MUX(0x1, "EPWM1_BRAKE0"), MA35_MUX(0x2, "UART16_RXD"), @@ -389,7 +434,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "EBI_AD9"), MA35_MUX(0xa, "SC1_RST"), MA35_MUX(0xb, "TM2")), - MA35_PIN(55, PD11, 0x9c, 0xc, + MA35_PIN(59, PD11, 0x9c, 0xc, MA35_MUX(0x0, "GPD11"), MA35_MUX(0x1, "EPWM1_BRAKE1"), MA35_MUX(0x2, "UART16_TXD"), @@ -399,7 +444,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "EBI_AD10"), MA35_MUX(0xa, "SC1_PWR"), MA35_MUX(0xb, "TM2_EXT")), - MA35_PIN(56, PD12, 0x9c, 0x10, + MA35_PIN(60, PD12, 0x9c, 0x10, MA35_MUX(0x0, "GPD12"), MA35_MUX(0x1, "EPWM0_BRAKE0"), MA35_MUX(0x2, "UART11_TXD"), @@ -412,7 +457,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xb, "TM5"), MA35_MUX(0xc, "I2S1_LRCK"), MA35_MUX(0xd, "INT1")), - MA35_PIN(57, PD13, 0x9c, 0x14, + MA35_PIN(61, PD13, 0x9c, 0x14, MA35_MUX(0x0, "GPD13"), MA35_MUX(0x1, "EPWM0_BRAKE1"), MA35_MUX(0x2, "UART11_RXD"), @@ -424,11 +469,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "ECAP0_IC0"), MA35_MUX(0xb, "TM5_EXT"), MA35_MUX(0xc, "I2S1_BCLK")), - MA35_PIN(58, PD14, 0x9c, 0x18, + MA35_PIN(62, PD14, 0x9c, 0x18, MA35_MUX(0x0, "GPD14"), MA35_MUX(0x1, "EPWM0_SYNC_IN"), MA35_MUX(0x2, "UART11_nCTS"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL5_DM"), MA35_MUX(0x6, "TRACE_DATA2"), MA35_MUX(0x7, "EBI_MCLK"), MA35_MUX(0x8, "EBI_AD6"), @@ -436,116 +482,117 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xb, "TM6"), MA35_MUX(0xc, "I2S1_DI"), MA35_MUX(0xd, "INT3")), - MA35_PIN(59, PD15, 0x9c, 0x1c, + MA35_PIN(63, PD15, 0x9c, 0x1c, MA35_MUX(0x0, "GPD15"), MA35_MUX(0x1, "EPWM0_SYNC_OUT"), MA35_MUX(0x2, "UART11_nRTS"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL5_DP"), MA35_MUX(0x6, "TRACE_DATA3"), MA35_MUX(0x7, "EBI_ALE"), MA35_MUX(0x8, "EBI_AD7"), MA35_MUX(0x9, "ECAP0_IC2"), MA35_MUX(0xb, "TM6_EXT"), MA35_MUX(0xc, "I2S1_DO")), - MA35_PIN(60, PE0, 0xa0, 0x0, + MA35_PIN(64, PE0, 0xa0, 0x0, MA35_MUX(0x0, "GPE0"), MA35_MUX(0x2, "UART9_nCTS"), MA35_MUX(0x3, "UART8_RXD"), MA35_MUX(0x7, "CCAP1_DATA0"), MA35_MUX(0x8, "RGMII0_MDC"), MA35_MUX(0x9, "RMII0_MDC")), - MA35_PIN(61, PE1, 0xa0, 0x4, + MA35_PIN(65, PE1, 0xa0, 0x4, MA35_MUX(0x0, "GPE1"), MA35_MUX(0x2, "UART9_nRTS"), MA35_MUX(0x3, "UART8_TXD"), MA35_MUX(0x7, "CCAP1_DATA1"), MA35_MUX(0x8, "RGMII0_MDIO"), MA35_MUX(0x9, "RMII0_MDIO")), - MA35_PIN(62, PE2, 0xa0, 0x8, + MA35_PIN(66, PE2, 0xa0, 0x8, MA35_MUX(0x0, "GPE2"), MA35_MUX(0x2, "UART9_RXD"), MA35_MUX(0x7, "CCAP1_DATA2"), MA35_MUX(0x8, "RGMII0_TXCTL"), MA35_MUX(0x9, "RMII0_TXEN")), - MA35_PIN(63, PE3, 0xa0, 0xc, + MA35_PIN(67, PE3, 0xa0, 0xc, MA35_MUX(0x0, "GPE3"), MA35_MUX(0x2, "UART9_TXD"), MA35_MUX(0x7, "CCAP1_DATA3"), MA35_MUX(0x8, "RGMII0_TXD0"), MA35_MUX(0x9, "RMII0_TXD0")), - MA35_PIN(64, PE4, 0xa0, 0x10, + MA35_PIN(68, PE4, 0xa0, 0x10, MA35_MUX(0x0, "GPE4"), MA35_MUX(0x2, "UART4_nCTS"), MA35_MUX(0x3, "UART3_RXD"), MA35_MUX(0x7, "CCAP1_DATA4"), MA35_MUX(0x8, "RGMII0_TXD1"), MA35_MUX(0x9, "RMII0_TXD1")), - MA35_PIN(65, PE5, 0xa0, 0x14, + MA35_PIN(69, PE5, 0xa0, 0x14, MA35_MUX(0x0, "GPE5"), MA35_MUX(0x2, "UART4_nRTS"), MA35_MUX(0x3, "UART3_TXD"), MA35_MUX(0x7, "CCAP1_DATA5"), MA35_MUX(0x8, "RGMII0_RXCLK"), MA35_MUX(0x9, "RMII0_REFCLK")), - MA35_PIN(66, PE6, 0xa0, 0x18, + MA35_PIN(70, PE6, 0xa0, 0x18, MA35_MUX(0x0, "GPE6"), MA35_MUX(0x2, "UART4_RXD"), MA35_MUX(0x7, "CCAP1_DATA6"), MA35_MUX(0x8, "RGMII0_RXCTL"), MA35_MUX(0x9, "RMII0_CRSDV")), - MA35_PIN(67, PE7, 0xa0, 0x1c, + MA35_PIN(71, PE7, 0xa0, 0x1c, MA35_MUX(0x0, "GPE7"), MA35_MUX(0x2, "UART4_TXD"), MA35_MUX(0x7, "CCAP1_DATA7"), MA35_MUX(0x8, "RGMII0_RXD0"), MA35_MUX(0x9, "RMII0_RXD0")), - MA35_PIN(68, PE8, 0xa4, 0x0, + MA35_PIN(72, PE8, 0xa4, 0x0, MA35_MUX(0x0, "GPE8"), MA35_MUX(0x2, "UART13_nCTS"), MA35_MUX(0x3, "UART12_RXD"), MA35_MUX(0x7, "CCAP1_SCLK"), MA35_MUX(0x8, "RGMII0_RXD1"), MA35_MUX(0x9, "RMII0_RXD1")), - MA35_PIN(69, PE9, 0xa4, 0x4, + MA35_PIN(73, PE9, 0xa4, 0x4, MA35_MUX(0x0, "GPE9"), MA35_MUX(0x2, "UART13_nRTS"), MA35_MUX(0x3, "UART12_TXD"), MA35_MUX(0x7, "CCAP1_PIXCLK"), MA35_MUX(0x8, "RGMII0_RXD2"), MA35_MUX(0x9, "RMII0_RXERR")), - MA35_PIN(70, PE10, 0xa4, 0x8, + MA35_PIN(74, PE10, 0xa4, 0x8, MA35_MUX(0x0, "GPE10"), MA35_MUX(0x2, "UART15_nCTS"), MA35_MUX(0x3, "UART14_RXD"), MA35_MUX(0x5, "SPI1_SS0"), MA35_MUX(0x7, "CCAP1_HSYNC"), MA35_MUX(0x8, "RGMII0_RXD3")), - MA35_PIN(71, PE11, 0xa4, 0xc, + MA35_PIN(75, PE11, 0xa4, 0xc, MA35_MUX(0x0, "GPE11"), MA35_MUX(0x2, "UART15_nRTS"), MA35_MUX(0x3, "UART14_TXD"), MA35_MUX(0x5, "SPI1_CLK"), MA35_MUX(0x7, "CCAP1_VSYNC"), MA35_MUX(0x8, "RGMII0_TXCLK")), - MA35_PIN(72, PE12, 0xa4, 0x10, + MA35_PIN(76, PE12, 0xa4, 0x10, MA35_MUX(0x0, "GPE12"), MA35_MUX(0x2, "UART15_RXD"), MA35_MUX(0x5, "SPI1_MOSI"), MA35_MUX(0x7, "CCAP1_DATA8"), MA35_MUX(0x8, "RGMII0_TXD2")), - MA35_PIN(73, PE13, 0xa4, 0x14, + MA35_PIN(77, PE13, 0xa4, 0x14, MA35_MUX(0x0, "GPE13"), MA35_MUX(0x2, "UART15_TXD"), MA35_MUX(0x5, "SPI1_MISO"), MA35_MUX(0x7, "CCAP1_DATA9"), MA35_MUX(0x8, "RGMII0_TXD3")), - MA35_PIN(74, PE14, 0xa4, 0x18, + MA35_PIN(78, PE14, 0xa4, 0x18, MA35_MUX(0x0, "GPE14"), MA35_MUX(0x1, "UART0_TXD")), - MA35_PIN(75, PE15, 0xa4, 0x1c, + MA35_PIN(79, PE15, 0xa4, 0x1c, MA35_MUX(0x0, "GPE15"), MA35_MUX(0x1, "UART0_RXD")), - MA35_PIN(76, PF0, 0xa8, 0x0, + MA35_PIN(80, PF0, 0xa8, 0x0, MA35_MUX(0x0, "GPF0"), MA35_MUX(0x2, "UART2_nCTS"), MA35_MUX(0x3, "UART1_RXD"), @@ -553,7 +600,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "RGMII1_MDC"), MA35_MUX(0x9, "RMII1_MDC"), MA35_MUX(0xe, "KPI_COL0")), - MA35_PIN(77, PF1, 0xa8, 0x4, + MA35_PIN(81, PF1, 0xa8, 0x4, MA35_MUX(0x0, "GPF1"), MA35_MUX(0x2, "UART2_nRTS"), MA35_MUX(0x3, "UART1_TXD"), @@ -561,21 +608,21 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "RGMII1_MDIO"), MA35_MUX(0x9, "RMII1_MDIO"), MA35_MUX(0xe, "KPI_COL1")), - MA35_PIN(78, PF2, 0xa8, 0x8, + MA35_PIN(82, PF2, 0xa8, 0x8, MA35_MUX(0x0, "GPF2"), MA35_MUX(0x2, "UART2_RXD"), MA35_MUX(0x6, "RGMII0_TXD2"), MA35_MUX(0x8, "RGMII1_TXCTL"), MA35_MUX(0x9, "RMII1_TXEN"), MA35_MUX(0xe, "KPI_COL2")), - MA35_PIN(79, PF3, 0xa8, 0xc, + MA35_PIN(83, PF3, 0xa8, 0xc, MA35_MUX(0x0, "GPF3"), MA35_MUX(0x2, "UART2_TXD"), MA35_MUX(0x6, "RGMII0_TXD3"), MA35_MUX(0x8, "RGMII1_TXD0"), MA35_MUX(0x9, "RMII1_TXD0"), MA35_MUX(0xe, "KPI_COL3")), - MA35_PIN(80, PF4, 0xa8, 0x10, + MA35_PIN(84, PF4, 0xa8, 0x10, MA35_MUX(0x0, "GPF4"), MA35_MUX(0x2, "UART11_nCTS"), MA35_MUX(0x3, "UART10_RXD"), @@ -583,9 +630,10 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x5, "SPI1_SS0"), MA35_MUX(0x8, "RGMII1_TXD1"), MA35_MUX(0x9, "RMII1_TXD1"), + MA35_MUX(0xc, "USBHL0_DM"), MA35_MUX(0xd, "CAN2_RXD"), MA35_MUX(0xe, "KPI_ROW0")), - MA35_PIN(81, PF5, 0xa8, 0x14, + MA35_PIN(85, PF5, 0xa8, 0x14, MA35_MUX(0x0, "GPF5"), MA35_MUX(0x2, "UART11_nRTS"), MA35_MUX(0x3, "UART10_TXD"), @@ -593,9 +641,10 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x5, "SPI1_CLK"), MA35_MUX(0x8, "RGMII1_RXCLK"), MA35_MUX(0x9, "RMII1_REFCLK"), + MA35_MUX(0xc, "USBHL0_DP"), MA35_MUX(0xd, "CAN2_TXD"), MA35_MUX(0xe, "KPI_ROW1")), - MA35_PIN(82, PF6, 0xa8, 0x18, + MA35_PIN(86, PF6, 0xa8, 0x18, MA35_MUX(0x0, "GPF6"), MA35_MUX(0x2, "UART11_RXD"), MA35_MUX(0x4, "I2S0_DI"), @@ -605,7 +654,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "I2C4_SDA"), MA35_MUX(0xd, "SC0_CLK"), MA35_MUX(0xe, "KPI_ROW2")), - MA35_PIN(83, PF7, 0xa8, 0x1c, + MA35_PIN(87, PF7, 0xa8, 0x1c, MA35_MUX(0x0, "GPF7"), MA35_MUX(0x2, "UART11_TXD"), MA35_MUX(0x4, "I2S0_DO"), @@ -615,7 +664,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "I2C4_SCL"), MA35_MUX(0xd, "SC0_DAT"), MA35_MUX(0xe, "KPI_ROW3")), - MA35_PIN(84, PF8, 0xac, 0x0, + MA35_PIN(88, PF8, 0xac, 0x0, MA35_MUX(0x0, "GPF8"), MA35_MUX(0x2, "UART13_RXD"), MA35_MUX(0x4, "I2C5_SDA"), @@ -624,7 +673,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "RMII1_RXD1"), MA35_MUX(0xd, "SC0_RST"), MA35_MUX(0xe, "KPI_COL4")), - MA35_PIN(85, PF9, 0xac, 0x4, + MA35_PIN(89, PF9, 0xac, 0x4, MA35_MUX(0x0, "GPF9"), MA35_MUX(0x2, "UART13_TXD"), MA35_MUX(0x4, "I2C5_SCL"), @@ -633,7 +682,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "RMII1_RXERR"), MA35_MUX(0xd, "SC0_PWR"), MA35_MUX(0xe, "KPI_COL5")), - MA35_PIN(86, PF10, 0xac, 0x8, + MA35_PIN(90, PF10, 0xac, 0x8, MA35_MUX(0x0, "GPF10"), MA35_MUX(0x2, "UART13_nCTS"), MA35_MUX(0x5, "I2S0_LRCK"), @@ -641,7 +690,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "RGMII1_RXD3"), MA35_MUX(0x9, "SC0_CLK"), MA35_MUX(0xe, "KPI_COL6")), - MA35_PIN(87, PF11, 0xac, 0xc, + MA35_PIN(91, PF11, 0xac, 0xc, MA35_MUX(0x0, "GPF11"), MA35_MUX(0x2, "UART13_nRTS"), MA35_MUX(0x5, "I2S0_BCLK"), @@ -649,21 +698,21 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "RGMII1_TXCLK"), MA35_MUX(0x9, "SC0_DAT"), MA35_MUX(0xe, "KPI_COL7")), - MA35_PIN(88, PF12, 0xac, 0x10, + MA35_PIN(92, PF12, 0xac, 0x10, MA35_MUX(0x0, "GPF12"), MA35_MUX(0x5, "I2S0_DI"), MA35_MUX(0x6, "SPI1_MOSI"), MA35_MUX(0x8, "RGMII1_TXD2"), MA35_MUX(0x9, "SC0_RST"), MA35_MUX(0xe, "KPI_ROW4")), - MA35_PIN(89, PF13, 0xac, 0x14, + MA35_PIN(93, PF13, 0xac, 0x14, MA35_MUX(0x0, "GPF13"), MA35_MUX(0x5, "I2S0_DO"), MA35_MUX(0x6, "SPI1_MISO"), MA35_MUX(0x8, "RGMII1_TXD3"), MA35_MUX(0x9, "SC0_PWR"), MA35_MUX(0xe, "KPI_ROW5")), - MA35_PIN(90, PF14, 0xac, 0x18, + MA35_PIN(94, PF14, 0xac, 0x18, MA35_MUX(0x0, "GPF14"), MA35_MUX(0x1, "EPWM2_BRAKE0"), MA35_MUX(0x2, "EADC0_ST"), @@ -679,10 +728,10 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xd, "SPI1_SS1"), MA35_MUX(0xe, "QEI2_INDEX"), MA35_MUX(0xf, "I2S0_MCLK")), - MA35_PIN(91, PF15, 0xac, 0x1c, + MA35_PIN(95, PF15, 0xac, 0x1c, MA35_MUX(0x0, "GPF15"), MA35_MUX(0x1, "HSUSB0_VBUSVLD")), - MA35_PIN(92, PG0, 0xb0, 0x0, + MA35_PIN(96, PG0, 0xb0, 0x0, MA35_MUX(0x0, "GPG0"), MA35_MUX(0x1, "EPWM0_CH0"), MA35_MUX(0x2, "UART7_TXD"), @@ -696,19 +745,20 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xc, "CLKO"), MA35_MUX(0xd, "INT0"), MA35_MUX(0xf, "EBI_ADR15")), - MA35_PIN(93, PG1, 0xb0, 0x4, + MA35_PIN(97, PG1, 0xb0, 0x4, MA35_MUX(0x0, "GPG1"), MA35_MUX(0x1, "EPWM0_CH3"), MA35_MUX(0x2, "UART9_nRTS"), MA35_MUX(0x3, "UART6_TXD"), MA35_MUX(0x4, "I2C4_SCL"), MA35_MUX(0x5, "CAN2_TXD"), + MA35_MUX(0x6, "USBHL0_DP"), MA35_MUX(0x7, "EBI_nCS0"), MA35_MUX(0x9, "QEI0_B"), MA35_MUX(0xb, "TM1_EXT"), MA35_MUX(0xe, "RGMII1_PPS"), MA35_MUX(0xf, "RMII1_PPS")), - MA35_PIN(94, PG2, 0xb0, 0x8, + MA35_PIN(98, PG2, 0xb0, 0x8, MA35_MUX(0x0, "GPG2"), MA35_MUX(0x1, "EPWM0_CH4"), MA35_MUX(0x2, "UART9_RXD"), @@ -719,7 +769,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "QEI0_A"), MA35_MUX(0xb, "TM3"), MA35_MUX(0xd, "INT1")), - MA35_PIN(95, PG3, 0xb0, 0xc, + MA35_PIN(99, PG3, 0xb0, 0xc, MA35_MUX(0x0, "GPG3"), MA35_MUX(0x1, "EPWM0_CH5"), MA35_MUX(0x2, "UART9_TXD"), @@ -731,7 +781,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "QEI0_B"), MA35_MUX(0xb, "TM3_EXT"), MA35_MUX(0xc, "I2S1_MCLK")), - MA35_PIN(96, PG4, 0xb0, 0x10, + MA35_PIN(100, PG4, 0xb0, 0x10, MA35_MUX(0x0, "GPG4"), MA35_MUX(0x1, "EPWM1_CH0"), MA35_MUX(0x2, "UART5_nCTS"), @@ -745,7 +795,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xb, "TM4"), MA35_MUX(0xd, "INT2"), MA35_MUX(0xe, "ECAP1_IC2")), - MA35_PIN(97, PG5, 0xb0, 0x14, + MA35_PIN(101, PG5, 0xb0, 0x14, MA35_MUX(0x0, "GPG5"), MA35_MUX(0x1, "EPWM1_CH1"), MA35_MUX(0x2, "UART5_nRTS"), @@ -757,7 +807,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "I2S1_DI"), MA35_MUX(0xa, "SC1_DAT"), MA35_MUX(0xb, "TM4_EXT")), - MA35_PIN(98, PG6, 0xb0, 0x18, + MA35_PIN(102, PG6, 0xb0, 0x18, MA35_MUX(0x0, "GPG6"), MA35_MUX(0x1, "EPWM1_CH2"), MA35_MUX(0x2, "UART5_RXD"), @@ -769,7 +819,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "SC1_RST"), MA35_MUX(0xb, "TM7"), MA35_MUX(0xd, "INT3")), - MA35_PIN(99, PG7, 0xb0, 0x1c, + MA35_PIN(103, PG7, 0xb0, 0x1c, MA35_MUX(0x0, "GPG7"), MA35_MUX(0x1, "EPWM1_CH3"), MA35_MUX(0x2, "UART5_TXD"), @@ -780,27 +830,29 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "I2S1_LRCK"), MA35_MUX(0xa, "SC1_PWR"), MA35_MUX(0xb, "TM7_EXT")), - MA35_PIN(100, PG8, 0xb4, 0x0, + MA35_PIN(104, PG8, 0xb4, 0x0, MA35_MUX(0x0, "GPG8"), MA35_MUX(0x1, "EPWM1_CH4"), MA35_MUX(0x2, "UART12_RXD"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL4_DM"), MA35_MUX(0x5, "SPI2_SS0"), MA35_MUX(0x6, "LCM_VSYNC"), MA35_MUX(0x7, "I2C3_SDA"), MA35_MUX(0xc, "EBI_AD7"), MA35_MUX(0xd, "EBI_nCS0")), - MA35_PIN(101, PG9, 0xb4, 0x4, + MA35_PIN(105, PG9, 0xb4, 0x4, MA35_MUX(0x0, "GPG9"), MA35_MUX(0x1, "EPWM1_CH5"), MA35_MUX(0x2, "UART12_TXD"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL4_DP"), MA35_MUX(0x5, "SPI2_CLK"), MA35_MUX(0x6, "LCM_HSYNC"), MA35_MUX(0x7, "I2C3_SCL"), MA35_MUX(0xc, "EBI_AD8"), MA35_MUX(0xd, "EBI_nCS1")), - MA35_PIN(102, PG10, 0xb4, 0x8, + MA35_PIN(106, PG10, 0xb4, 0x8, MA35_MUX(0x0, "GPG10"), MA35_MUX(0x2, "UART12_nRTS"), MA35_MUX(0x3, "UART13_TXD"), @@ -808,7 +860,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x6, "LCM_CLK"), MA35_MUX(0xc, "EBI_AD9"), MA35_MUX(0xd, "EBI_nWRH")), - MA35_PIN(103, PG11, 0xb4, 0xc, + MA35_PIN(107, PG11, 0xb4, 0xc, MA35_MUX(0x0, "GPG11"), MA35_MUX(0x3, "JTAG_TDO"), MA35_MUX(0x5, "I2S0_MCLK"), @@ -816,93 +868,93 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x7, "EBI_nWRH"), MA35_MUX(0x8, "EBI_nCS1"), MA35_MUX(0xa, "EBI_AD0")), - MA35_PIN(104, PG12, 0xb4, 0x10, + MA35_PIN(108, PG12, 0xb4, 0x10, MA35_MUX(0x0, "GPG12"), MA35_MUX(0x3, "JTAG_TCK/SW_CLK"), MA35_MUX(0x5, "I2S0_LRCK"), MA35_MUX(0x7, "EBI_nWRL"), MA35_MUX(0xa, "EBI_AD1")), - MA35_PIN(105, PG13, 0xb4, 0x14, + MA35_PIN(109, PG13, 0xb4, 0x14, MA35_MUX(0x0, "GPG13"), MA35_MUX(0x3, "JTAG_TMS/SW_DIO"), MA35_MUX(0x5, "I2S0_BCLK"), MA35_MUX(0x7, "EBI_MCLK"), MA35_MUX(0xa, "EBI_AD2")), - MA35_PIN(106, PG14, 0xb4, 0x18, + MA35_PIN(110, PG14, 0xb4, 0x18, MA35_MUX(0x0, "GPG14"), MA35_MUX(0x3, "JTAG_TDI"), MA35_MUX(0x5, "I2S0_DI"), MA35_MUX(0x6, "NAND_nCS1"), MA35_MUX(0x7, "EBI_ALE"), MA35_MUX(0xa, "EBI_AD3")), - MA35_PIN(107, PG15, 0xb4, 0x1c, + MA35_PIN(111, PG15, 0xb4, 0x1c, MA35_MUX(0x0, "GPG15"), MA35_MUX(0x3, "JTAG_nTRST"), MA35_MUX(0x5, "I2S0_DO"), MA35_MUX(0x7, "EBI_nCS0"), MA35_MUX(0xa, "EBI_AD4")), - MA35_PIN(108, PH0, 0xb8, 0x0, + MA35_PIN(112, PH0, 0xb8, 0x0, MA35_MUX(0x0, "GPH0"), MA35_MUX(0x2, "UART8_nCTS"), MA35_MUX(0x3, "UART7_RXD"), MA35_MUX(0x6, "LCM_DATA8")), - MA35_PIN(109, PH1, 0xb8, 0x4, + MA35_PIN(113, PH1, 0xb8, 0x4, MA35_MUX(0x0, "GPH1"), MA35_MUX(0x2, "UART8_nRTS"), MA35_MUX(0x3, "UART7_TXD"), MA35_MUX(0x6, "LCM_DATA9")), - MA35_PIN(110, PH2, 0xb8, 0x8, + MA35_PIN(114, PH2, 0xb8, 0x8, MA35_MUX(0x0, "GPH2"), MA35_MUX(0x2, "UART8_RXD"), MA35_MUX(0x6, "LCM_DATA10")), - MA35_PIN(111, PH3, 0xb8, 0xc, + MA35_PIN(115, PH3, 0xb8, 0xc, MA35_MUX(0x0, "GPH3"), MA35_MUX(0x2, "UART8_TXD"), MA35_MUX(0x6, "LCM_DATA11")), - MA35_PIN(112, PH4, 0xb8, 0x10, + MA35_PIN(116, PH4, 0xb8, 0x10, MA35_MUX(0x0, "GPH4"), MA35_MUX(0x2, "UART10_nCTS"), MA35_MUX(0x3, "UART9_RXD"), MA35_MUX(0x6, "LCM_DATA12")), - MA35_PIN(113, PH5, 0xb8, 0x14, + MA35_PIN(117, PH5, 0xb8, 0x14, MA35_MUX(0x0, "GPH5"), MA35_MUX(0x2, "UART10_nRTS"), MA35_MUX(0x3, "UART9_TXD"), MA35_MUX(0x6, "LCM_DATA13")), - MA35_PIN(114, PH6, 0xb8, 0x18, + MA35_PIN(118, PH6, 0xb8, 0x18, MA35_MUX(0x0, "GPH6"), MA35_MUX(0x2, "UART10_RXD"), MA35_MUX(0x6, "LCM_DATA14")), - MA35_PIN(115, PH7, 0xb8, 0x1c, + MA35_PIN(119, PH7, 0xb8, 0x1c, MA35_MUX(0x0, "GPH7"), MA35_MUX(0x2, "UART10_TXD"), MA35_MUX(0x6, "LCM_DATA15")), - MA35_PIN(116, PH8, 0xbc, 0x0, + MA35_PIN(120, PH8, 0xbc, 0x0, MA35_MUX(0x0, "GPH8"), MA35_MUX(0x6, "TAMPER0")), - MA35_PIN(117, PH9, 0xbc, 0x4, + MA35_PIN(121, PH9, 0xbc, 0x4, MA35_MUX(0x0, "GPH9"), MA35_MUX(0x4, "CLK_32KOUT"), MA35_MUX(0x6, "TAMPER1")), - MA35_PIN(118, PH12, 0xbc, 0x10, + MA35_PIN(124, PH12, 0xbc, 0x10, MA35_MUX(0x0, "GPH12"), MA35_MUX(0x2, "UART14_nCTS"), MA35_MUX(0x3, "UART13_RXD"), MA35_MUX(0x6, "LCM_DATA20")), - MA35_PIN(119, PH13, 0xbc, 0x14, + MA35_PIN(125, PH13, 0xbc, 0x14, MA35_MUX(0x0, "GPH13"), MA35_MUX(0x2, "UART14_nRTS"), MA35_MUX(0x3, "UART13_TXD"), MA35_MUX(0x6, "LCM_DATA21")), - MA35_PIN(120, PH14, 0xbc, 0x18, + MA35_PIN(126, PH14, 0xbc, 0x18, MA35_MUX(0x0, "GPH14"), MA35_MUX(0x2, "UART14_RXD"), MA35_MUX(0x6, "LCM_DATA22")), - MA35_PIN(121, PH15, 0xbc, 0x1c, + MA35_PIN(127, PH15, 0xbc, 0x1c, MA35_MUX(0x0, "GPH15"), MA35_MUX(0x2, "UART14_TXD"), MA35_MUX(0x6, "LCM_DATA23")), - MA35_PIN(122, PI0, 0xc0, 0x0, + MA35_PIN(128, PI0, 0xc0, 0x0, MA35_MUX(0x0, "GPI0"), MA35_MUX(0x1, "EPWM0_CH0"), MA35_MUX(0x2, "UART12_nCTS"), @@ -913,7 +965,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "EBI_ADR0"), MA35_MUX(0xb, "TM0"), MA35_MUX(0xc, "ECAP1_IC0")), - MA35_PIN(123, PI1, 0xc0, 0x4, + MA35_PIN(129, PI1, 0xc0, 0x4, MA35_MUX(0x0, "GPI1"), MA35_MUX(0x1, "EPWM0_CH1"), MA35_MUX(0x2, "UART12_nRTS"), @@ -924,26 +976,28 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "EBI_ADR1"), MA35_MUX(0xb, "TM0_EXT"), MA35_MUX(0xc, "ECAP1_IC1")), - MA35_PIN(124, PI2, 0xc0, 0x8, + MA35_PIN(130, PI2, 0xc0, 0x8, MA35_MUX(0x0, "GPI2"), MA35_MUX(0x1, "EPWM0_CH2"), MA35_MUX(0x2, "UART12_RXD"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL2_DM"), MA35_MUX(0x5, "SPI3_MOSI"), MA35_MUX(0x7, "SC0_DAT"), MA35_MUX(0x8, "EBI_ADR2"), MA35_MUX(0xb, "TM1"), MA35_MUX(0xc, "ECAP1_IC2")), - MA35_PIN(125, PI3, 0xc0, 0xc, + MA35_PIN(131, PI3, 0xc0, 0xc, MA35_MUX(0x0, "GPI3"), MA35_MUX(0x1, "EPWM0_CH3"), MA35_MUX(0x2, "UART12_TXD"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL2_DP"), MA35_MUX(0x5, "SPI3_MISO"), MA35_MUX(0x7, "SC0_RST"), MA35_MUX(0x8, "EBI_ADR3"), MA35_MUX(0xb, "TM1_EXT")), - MA35_PIN(126, PI4, 0xc0, 0x10, + MA35_PIN(132, PI4, 0xc0, 0x10, MA35_MUX(0x0, "GPI4"), MA35_MUX(0x1, "EPWM0_CH4"), MA35_MUX(0x2, "UART14_nCTS"), @@ -953,7 +1007,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x6, "I2S1_LRCK"), MA35_MUX(0x8, "EBI_ADR4"), MA35_MUX(0xd, "INT0")), - MA35_PIN(127, PI5, 0xc0, 0x14, + MA35_PIN(133, PI5, 0xc0, 0x14, MA35_MUX(0x0, "GPI5"), MA35_MUX(0x1, "EPWM0_CH5"), MA35_MUX(0x2, "UART14_nRTS"), @@ -962,65 +1016,67 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x6, "I2S1_BCLK"), MA35_MUX(0x8, "EBI_ADR5"), MA35_MUX(0xd, "INT1")), - MA35_PIN(128, PI6, 0xc0, 0x18, + MA35_PIN(134, PI6, 0xc0, 0x18, MA35_MUX(0x0, "GPI6"), MA35_MUX(0x1, "EPWM0_BRAKE0"), MA35_MUX(0x2, "UART14_RXD"), MA35_MUX(0x3, "CAN1_RXD"), + MA35_MUX(0x4, "USBHL3_DM"), MA35_MUX(0x6, "I2S1_DI"), MA35_MUX(0x8, "EBI_ADR6"), MA35_MUX(0xc, "QEI1_INDEX"), MA35_MUX(0xd, "INT2")), - MA35_PIN(129, PI7, 0xc0, 0x1c, + MA35_PIN(135, PI7, 0xc0, 0x1c, MA35_MUX(0x0, "GPI7"), MA35_MUX(0x1, "EPWM0_BRAKE1"), MA35_MUX(0x2, "UART14_TXD"), MA35_MUX(0x3, "CAN1_TXD"), + MA35_MUX(0x4, "USBHL3_DP"), MA35_MUX(0x6, "I2S1_DO"), MA35_MUX(0x8, "EBI_ADR7"), MA35_MUX(0xc, "ECAP0_IC0"), MA35_MUX(0xd, "INT3")), - MA35_PIN(130, PI8, 0xc4, 0x0, + MA35_PIN(136, PI8, 0xc4, 0x0, MA35_MUX(0x0, "GPI8"), MA35_MUX(0x2, "UART4_nCTS"), MA35_MUX(0x3, "UART3_RXD"), MA35_MUX(0x6, "LCM_DATA0"), MA35_MUX(0xc, "EBI_AD11")), - MA35_PIN(131, PI9, 0xc4, 0x4, + MA35_PIN(137, PI9, 0xc4, 0x4, MA35_MUX(0x0, "GPI9"), MA35_MUX(0x2, "UART4_nRTS"), MA35_MUX(0x3, "UART3_TXD"), MA35_MUX(0x6, "LCM_DATA1"), MA35_MUX(0xc, "EBI_AD12")), - MA35_PIN(132, PI10, 0xc4, 0x8, + MA35_PIN(138, PI10, 0xc4, 0x8, MA35_MUX(0x0, "GPI10"), MA35_MUX(0x2, "UART4_RXD"), MA35_MUX(0x6, "LCM_DATA2"), MA35_MUX(0xc, "EBI_AD13")), - MA35_PIN(133, PI11, 0xC4, 0xc, + MA35_PIN(139, PI11, 0xC4, 0xc, MA35_MUX(0x0, "GPI11"), MA35_MUX(0x2, "UART4_TXD"), MA35_MUX(0x6, "LCM_DATA3"), MA35_MUX(0xc, "EBI_AD14")), - MA35_PIN(134, PI12, 0xc4, 0x10, + MA35_PIN(140, PI12, 0xc4, 0x10, MA35_MUX(0x0, "GPI12"), MA35_MUX(0x2, "UART6_nCTS"), MA35_MUX(0x3, "UART5_RXD"), MA35_MUX(0x6, "LCM_DATA4")), - MA35_PIN(135, PI13, 0xc4, 0x14, + MA35_PIN(141, PI13, 0xc4, 0x14, MA35_MUX(0x0, "GPI13"), MA35_MUX(0x2, "UART6_nRTS"), MA35_MUX(0x3, "UART5_TXD"), MA35_MUX(0x6, "LCM_DATA5")), - MA35_PIN(136, PI14, 0xc4, 0x18, + MA35_PIN(142, PI14, 0xc4, 0x18, MA35_MUX(0x0, "GPI14"), MA35_MUX(0x2, "UART6_RXD"), MA35_MUX(0x6, "LCM_DATA6")), - MA35_PIN(137, PI15, 0xc4, 0x1c, + MA35_PIN(143, PI15, 0xc4, 0x1c, MA35_MUX(0x0, "GPI15"), MA35_MUX(0x2, "UART6_TXD"), MA35_MUX(0x6, "LCM_DATA7")), - MA35_PIN(138, PJ0, 0xc8, 0x0, + MA35_PIN(144, PJ0, 0xc8, 0x0, MA35_MUX(0x0, "GPJ0"), MA35_MUX(0x1, "EPWM1_BRAKE0"), MA35_MUX(0x2, "UART8_nCTS"), @@ -1034,7 +1090,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "EBI_ADR16"), MA35_MUX(0xb, "EBI_nCS0"), MA35_MUX(0xc, "EBI_AD7")), - MA35_PIN(139, PJ1, 0xc8, 0x4, + MA35_PIN(145, PJ1, 0xc8, 0x4, MA35_MUX(0x0, "GPJ1"), MA35_MUX(0x1, "EPWM1_BRAKE1"), MA35_MUX(0x2, "UART8_nRTS"), @@ -1048,11 +1104,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "EBI_ADR17"), MA35_MUX(0xb, "EBI_nCS1"), MA35_MUX(0xc, "EBI_AD8")), - MA35_PIN(140, PJ2, 0xc8, 0x8, + MA35_PIN(146, PJ2, 0xc8, 0x8, MA35_MUX(0x0, "GPJ2"), MA35_MUX(0x1, "EPWM1_CH4"), MA35_MUX(0x2, "UART8_RXD"), MA35_MUX(0x3, "CAN1_RXD"), + MA35_MUX(0x4, "USBHL5_DM"), MA35_MUX(0x5, "SPI2_MOSI"), MA35_MUX(0x6, "eMMC1_DAT6"), MA35_MUX(0x7, "I2S0_DI"), @@ -1061,11 +1118,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "EBI_ADR18"), MA35_MUX(0xb, "EBI_nWRH"), MA35_MUX(0xc, "EBI_AD9")), - MA35_PIN(141, PJ3, 0xc8, 0xc, + MA35_PIN(147, PJ3, 0xc8, 0xc, MA35_MUX(0x0, "GPJ3"), MA35_MUX(0x1, "EPWM1_CH5"), MA35_MUX(0x2, "UART8_TXD"), MA35_MUX(0x3, "CAN1_TXD"), + MA35_MUX(0x4, "USBHL5_DP"), MA35_MUX(0x5, "SPI2_MISO"), MA35_MUX(0x6, "eMMC1_DAT7"), MA35_MUX(0x7, "I2S0_DO"), @@ -1074,39 +1132,43 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "EBI_ADR19"), MA35_MUX(0xb, "EBI_nWRL"), MA35_MUX(0xc, "EBI_AD10")), - MA35_PIN(142, PJ4, 0xc8, 0x10, + MA35_PIN(148, PJ4, 0xc8, 0x10, MA35_MUX(0x0, "GPJ4"), MA35_MUX(0x4, "I2C3_SDA"), MA35_MUX(0x6, "SD1_WP")), - MA35_PIN(143, PJ5, 0xc8, 0x14, + MA35_PIN(149, PJ5, 0xc8, 0x14, MA35_MUX(0x0, "GPJ5"), MA35_MUX(0x4, "I2C3_SCL"), MA35_MUX(0x6, "SD1_nCD")), - MA35_PIN(144, PJ6, 0xc8, 0x18, + MA35_PIN(150, PJ6, 0xc8, 0x18, MA35_MUX(0x0, "GPJ6"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL0_DM"), MA35_MUX(0x6, "SD1_CMD/eMMC1_CMD")), - MA35_PIN(145, PJ7, 0xc8, 0x1c, + MA35_PIN(151, PJ7, 0xc8, 0x1c, MA35_MUX(0x0, "GPJ7"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL0_DP"), MA35_MUX(0x6, "SD1_CLK/eMMC1_CLK")), - MA35_PIN(146, PJ8, 0xcc, 0x0, + MA35_PIN(152, PJ8, 0xcc, 0x0, MA35_MUX(0x0, "GPJ8"), MA35_MUX(0x4, "I2C4_SDA"), MA35_MUX(0x6, "SD1_DAT0/eMMC1_DAT0")), - MA35_PIN(147, PJ9, 0xcc, 0x4, + MA35_PIN(153, PJ9, 0xcc, 0x4, MA35_MUX(0x0, "GPJ9"), MA35_MUX(0x4, "I2C4_SCL"), MA35_MUX(0x6, "SD1_DAT1/eMMC1_DAT1")), - MA35_PIN(148, PJ10, 0xcc, 0x8, + MA35_PIN(154, PJ10, 0xcc, 0x8, MA35_MUX(0x0, "GPJ10"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL1_DM"), MA35_MUX(0x6, "SD1_DAT2/eMMC1_DAT2")), - MA35_PIN(149, PJ11, 0xcc, 0xc, + MA35_PIN(155, PJ11, 0xcc, 0xc, MA35_MUX(0x0, "GPJ11"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL1_DP"), MA35_MUX(0x6, "SD1_DAT3/eMMC1_DAT3")), - MA35_PIN(150, PJ12, 0xcc, 0x10, + MA35_PIN(156, PJ12, 0xcc, 0x10, MA35_MUX(0x0, "GPJ12"), MA35_MUX(0x1, "EPWM1_CH2"), MA35_MUX(0x2, "UART2_nCTS"), @@ -1117,7 +1179,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "EBI_ADR12"), MA35_MUX(0xb, "TM2"), MA35_MUX(0xc, "QEI0_INDEX")), - MA35_PIN(151, PJ13, 0xcc, 0x14, + MA35_PIN(157, PJ13, 0xcc, 0x14, MA35_MUX(0x0, "GPJ13"), MA35_MUX(0x1, "EPWM1_CH3"), MA35_MUX(0x2, "UART2_nRTS"), @@ -1127,27 +1189,29 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x7, "SC1_DAT"), MA35_MUX(0x8, "EBI_ADR13"), MA35_MUX(0xb, "TM2_EXT")), - MA35_PIN(152, PJ14, 0xcc, 0x18, + MA35_PIN(158, PJ14, 0xcc, 0x18, MA35_MUX(0x0, "GPJ14"), MA35_MUX(0x1, "EPWM1_CH4"), MA35_MUX(0x2, "UART2_RXD"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL5_DM"), MA35_MUX(0x5, "SPI3_MISO"), MA35_MUX(0x7, "SC1_RST"), MA35_MUX(0x8, "EBI_ADR14"), MA35_MUX(0xb, "TM3")), - MA35_PIN(153, PJ15, 0xcc, 0x1c, + MA35_PIN(159, PJ15, 0xcc, 0x1c, MA35_MUX(0x0, "GPJ15"), MA35_MUX(0x1, "EPWM1_CH5"), MA35_MUX(0x2, "UART2_TXD"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL5_DP"), MA35_MUX(0x5, "SPI3_CLK"), MA35_MUX(0x6, "EADC0_ST"), MA35_MUX(0x7, "SC1_PWR"), MA35_MUX(0x8, "EBI_ADR15"), MA35_MUX(0xb, "TM3_EXT"), MA35_MUX(0xd, "INT1")), - MA35_PIN(154, PK0, 0xd0, 0x0, + MA35_PIN(160, PK0, 0xd0, 0x0, MA35_MUX(0x0, "GPK0"), MA35_MUX(0x1, "EPWM0_SYNC_IN"), MA35_MUX(0x2, "UART16_nCTS"), @@ -1157,7 +1221,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "EBI_ADR8"), MA35_MUX(0xb, "TM7"), MA35_MUX(0xc, "ECAP0_IC1")), - MA35_PIN(155, PK1, 0xd0, 0x4, + MA35_PIN(161, PK1, 0xd0, 0x4, MA35_MUX(0x0, "GPK1"), MA35_MUX(0x1, "EPWM0_SYNC_OUT"), MA35_MUX(0x2, "UART16_nRTS"), @@ -1167,25 +1231,27 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "EBI_ADR9"), MA35_MUX(0xb, "TM7_EXT"), MA35_MUX(0xc, "ECAP0_IC2")), - MA35_PIN(156, PK2, 0xd0, 0x8, + MA35_PIN(162, PK2, 0xd0, 0x8, MA35_MUX(0x0, "GPK2"), MA35_MUX(0x1, "EPWM1_CH0"), MA35_MUX(0x2, "UART16_RXD"), MA35_MUX(0x3, "CAN2_RXD"), + MA35_MUX(0x4, "USBHL4_DM"), MA35_MUX(0x5, "SPI3_I2SMCLK"), MA35_MUX(0x7, "SC0_PWR"), MA35_MUX(0x8, "EBI_ADR10"), MA35_MUX(0xc, "QEI0_A")), - MA35_PIN(157, PK3, 0xd0, 0xc, + MA35_PIN(163, PK3, 0xd0, 0xc, MA35_MUX(0x0, "GPK3"), MA35_MUX(0x1, "EPWM1_CH1"), MA35_MUX(0x2, "UART16_TXD"), MA35_MUX(0x3, "CAN2_TXD"), + MA35_MUX(0x4, "USBHL4_DP"), MA35_MUX(0x5, "SPI3_SS1"), MA35_MUX(0x7, "SC1_nCD"), MA35_MUX(0x8, "EBI_ADR11"), MA35_MUX(0xc, "QEI0_B")), - MA35_PIN(158, PK4, 0xd0, 0x10, + MA35_PIN(164, PK4, 0xd0, 0x10, MA35_MUX(0x0, "GPK4"), MA35_MUX(0x2, "UART12_nCTS"), MA35_MUX(0x3, "UART13_RXD"), @@ -1193,7 +1259,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x6, "LCM_DEN"), MA35_MUX(0xc, "EBI_AD10"), MA35_MUX(0xd, "EBI_nWRL")), - MA35_PIN(159, PK5, 0xd0, 0x14, + MA35_PIN(165, PK5, 0xd0, 0x14, MA35_MUX(0x0, "GPK5"), MA35_MUX(0x1, "EPWM1_CH1"), MA35_MUX(0x2, "UART12_nRTS"), @@ -1205,28 +1271,30 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "EADC0_ST"), MA35_MUX(0xb, "TM8_EXT"), MA35_MUX(0xd, "INT1")), - MA35_PIN(160, PK6, 0xd0, 0x18, + MA35_PIN(166, PK6, 0xd0, 0x18, MA35_MUX(0x0, "GPK6"), MA35_MUX(0x1, "EPWM1_CH2"), MA35_MUX(0x2, "UART12_RXD"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL4_DM"), MA35_MUX(0x5, "SPI2_MOSI"), MA35_MUX(0x7, "I2S1_BCLK"), MA35_MUX(0x8, "SC0_RST"), MA35_MUX(0xb, "TM6"), MA35_MUX(0xd, "INT2")), - MA35_PIN(161, PK7, 0xd0, 0x1c, + MA35_PIN(167, PK7, 0xd0, 0x1c, MA35_MUX(0x0, "GPK7"), MA35_MUX(0x1, "EPWM1_CH3"), MA35_MUX(0x2, "UART12_TXD"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL4_DP"), MA35_MUX(0x5, "SPI2_MISO"), MA35_MUX(0x7, "I2S1_LRCK"), MA35_MUX(0x8, "SC0_PWR"), MA35_MUX(0x9, "CLKO"), MA35_MUX(0xb, "TM6_EXT"), MA35_MUX(0xd, "INT3")), - MA35_PIN(162, PK8, 0xd4, 0x0, + MA35_PIN(168, PK8, 0xd4, 0x0, MA35_MUX(0x0, "GPK8"), MA35_MUX(0x1, "EPWM1_CH0"), MA35_MUX(0x4, "I2C3_SDA"), @@ -1237,25 +1305,27 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xa, "EBI_ADR15"), MA35_MUX(0xb, "TM8"), MA35_MUX(0xc, "QEI1_INDEX")), - MA35_PIN(163, PK9, 0xd4, 0x4, + MA35_PIN(169, PK9, 0xd4, 0x4, MA35_MUX(0x0, "GPK9"), MA35_MUX(0x4, "I2C3_SCL"), MA35_MUX(0x6, "CCAP0_SCLK"), MA35_MUX(0x8, "EBI_AD0"), MA35_MUX(0xa, "EBI_ADR0")), - MA35_PIN(164, PK10, 0xd4, 0x8, + MA35_PIN(170, PK10, 0xd4, 0x8, MA35_MUX(0x0, "GPK10"), MA35_MUX(0x3, "CAN1_RXD"), + MA35_MUX(0x4, "USBHL3_DM"), MA35_MUX(0x6, "CCAP0_PIXCLK"), MA35_MUX(0x8, "EBI_AD1"), MA35_MUX(0xa, "EBI_ADR1")), - MA35_PIN(165, PK11, 0xd4, 0xc, + MA35_PIN(171, PK11, 0xd4, 0xc, MA35_MUX(0x0, "GPK11"), MA35_MUX(0x3, "CAN1_TXD"), + MA35_MUX(0x4, "USBHL3_DP"), MA35_MUX(0x6, "CCAP0_HSYNC"), MA35_MUX(0x8, "EBI_AD2"), MA35_MUX(0xa, "EBI_ADR2")), - MA35_PIN(166, PK12, 0xd4, 0x10, + MA35_PIN(172, PK12, 0xd4, 0x10, MA35_MUX(0x0, "GPK12"), MA35_MUX(0x1, "EPWM2_CH0"), MA35_MUX(0x2, "UART1_nCTS"), @@ -1266,7 +1336,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "SC0_CLK"), MA35_MUX(0xb, "TM10"), MA35_MUX(0xd, "INT2")), - MA35_PIN(167, PK13, 0xd4, 0x14, + MA35_PIN(173, PK13, 0xd4, 0x14, MA35_MUX(0x0, "GPK13"), MA35_MUX(0x1, "EPWM2_CH1"), MA35_MUX(0x2, "UART1_nRTS"), @@ -1276,28 +1346,30 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x6, "SPI1_CLK"), MA35_MUX(0x8, "SC0_DAT"), MA35_MUX(0xb, "TM10_EXT")), - MA35_PIN(168, PK14, 0xd4, 0x18, + MA35_PIN(174, PK14, 0xd4, 0x18, MA35_MUX(0x0, "GPK14"), MA35_MUX(0x1, "EPWM2_CH2"), MA35_MUX(0x2, "UART1_RXD"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL4_DM"), MA35_MUX(0x5, "I2S0_DI"), MA35_MUX(0x6, "SPI1_MOSI"), MA35_MUX(0x8, "SC0_RST"), MA35_MUX(0xa, "I2C5_SDA"), MA35_MUX(0xb, "TM11"), MA35_MUX(0xd, "INT3")), - MA35_PIN(169, PK15, 0xd4, 0x1c, + MA35_PIN(175, PK15, 0xd4, 0x1c, MA35_MUX(0x0, "GPK15"), MA35_MUX(0x1, "EPWM2_CH3"), MA35_MUX(0x2, "UART1_TXD"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL4_DP"), MA35_MUX(0x5, "I2S0_DO"), MA35_MUX(0x6, "SPI1_MISO"), MA35_MUX(0x8, "SC0_PWR"), MA35_MUX(0xa, "I2C5_SCL"), MA35_MUX(0xb, "TM11_EXT")), - MA35_PIN(170, PL0, 0xd8, 0x0, + MA35_PIN(176, PL0, 0xd8, 0x0, MA35_MUX(0x0, "GPL0"), MA35_MUX(0x1, "EPWM1_CH0"), MA35_MUX(0x2, "UART11_nCTS"), @@ -1310,7 +1382,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC1_CLK"), MA35_MUX(0xb, "TM5"), MA35_MUX(0xc, "QEI1_A")), - MA35_PIN(171, PL1, 0xd8, 0x4, + MA35_PIN(177, PL1, 0xd8, 0x4, MA35_MUX(0x0, "GPL1"), MA35_MUX(0x1, "EPWM1_CH1"), MA35_MUX(0x2, "UART11_nRTS"), @@ -1323,11 +1395,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC1_DAT"), MA35_MUX(0xb, "TM5_EXT"), MA35_MUX(0xc, "QEI1_B")), - MA35_PIN(172, PL2, 0xd8, 0x8, + MA35_PIN(178, PL2, 0xd8, 0x8, MA35_MUX(0x0, "GPL2"), MA35_MUX(0x1, "EPWM1_CH2"), MA35_MUX(0x2, "UART11_RXD"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL4_DM"), MA35_MUX(0x5, "SPI2_SS0"), MA35_MUX(0x6, "QSPI1_SS1"), MA35_MUX(0x7, "I2S0_DI"), @@ -1335,11 +1408,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC1_RST"), MA35_MUX(0xb, "TM7"), MA35_MUX(0xc, "QEI1_INDEX")), - MA35_PIN(173, PL3, 0xd8, 0xc, + MA35_PIN(179, PL3, 0xd8, 0xc, MA35_MUX(0x0, "GPL3"), MA35_MUX(0x1, "EPWM1_CH3"), MA35_MUX(0x2, "UART11_TXD"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL4_DP"), MA35_MUX(0x5, "SPI2_CLK"), MA35_MUX(0x6, "QSPI1_CLK"), MA35_MUX(0x7, "I2S0_DO"), @@ -1347,7 +1421,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC1_PWR"), MA35_MUX(0xb, "TM7_EXT"), MA35_MUX(0xc, "ECAP0_IC0")), - MA35_PIN(174, PL4, 0xd8, 0x10, + MA35_PIN(180, PL4, 0xd8, 0x10, MA35_MUX(0x0, "GPL4"), MA35_MUX(0x1, "EPWM1_CH4"), MA35_MUX(0x2, "UART2_nCTS"), @@ -1360,7 +1434,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC1_nCD"), MA35_MUX(0xb, "TM9"), MA35_MUX(0xc, "ECAP0_IC1")), - MA35_PIN(175, PL5, 0xd8, 0x14, + MA35_PIN(181, PL5, 0xd8, 0x14, MA35_MUX(0x0, "GPL5"), MA35_MUX(0x1, "EPWM1_CH5"), MA35_MUX(0x2, "UART2_nRTS"), @@ -1373,28 +1447,30 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC0_nCD"), MA35_MUX(0xb, "TM9_EXT"), MA35_MUX(0xc, "ECAP0_IC2")), - MA35_PIN(176, PL6, 0xd8, 0x18, + MA35_PIN(182, PL6, 0xd8, 0x18, MA35_MUX(0x0, "GPL6"), MA35_MUX(0x1, "EPWM0_CH0"), MA35_MUX(0x2, "UART2_RXD"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL5_DM"), MA35_MUX(0x6, "QSPI1_MOSI1"), MA35_MUX(0x7, "TRACE_CLK"), MA35_MUX(0x8, "EBI_AD5"), MA35_MUX(0xb, "TM3"), MA35_MUX(0xc, "ECAP1_IC0"), MA35_MUX(0xd, "INT0")), - MA35_PIN(177, PL7, 0xd8, 0x1c, + MA35_PIN(183, PL7, 0xd8, 0x1c, MA35_MUX(0x0, "GPL7"), MA35_MUX(0x1, "EPWM0_CH1"), MA35_MUX(0x2, "UART2_TXD"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL5_DP"), MA35_MUX(0x6, "QSPI1_MISO1"), MA35_MUX(0x8, "EBI_AD6"), MA35_MUX(0xb, "TM3_EXT"), MA35_MUX(0xc, "ECAP1_IC1"), MA35_MUX(0xd, "INT1")), - MA35_PIN(178, PL8, 0xdc, 0x0, + MA35_PIN(184, PL8, 0xdc, 0x0, MA35_MUX(0x0, "GPL8"), MA35_MUX(0x1, "EPWM0_CH2"), MA35_MUX(0x2, "UART14_nCTS"), @@ -1408,7 +1484,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xb, "TM4"), MA35_MUX(0xc, "ECAP1_IC2"), MA35_MUX(0xd, "INT2")), - MA35_PIN(179, PL9, 0xdc, 0x4, + MA35_PIN(185, PL9, 0xdc, 0x4, MA35_MUX(0x0, "GPL9"), MA35_MUX(0x1, "EPWM0_CH3"), MA35_MUX(0x2, "UART14_nRTS"), @@ -1422,11 +1498,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xb, "TM4_EXT"), MA35_MUX(0xc, "QEI0_A"), MA35_MUX(0xd, "INT3")), - MA35_PIN(180, PL10, 0xdc, 0x8, + MA35_PIN(186, PL10, 0xdc, 0x8, MA35_MUX(0x0, "GPL10"), MA35_MUX(0x1, "EPWM0_CH4"), MA35_MUX(0x2, "UART14_RXD"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL2_DM"), MA35_MUX(0x5, "SPI3_MOSI"), MA35_MUX(0x6, "EPWM0_CH5"), MA35_MUX(0x7, "I2S1_DI"), @@ -1434,11 +1511,12 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC0_RST"), MA35_MUX(0xb, "EBI_nWRH"), MA35_MUX(0xc, "QEI0_B")), - MA35_PIN(181, PL11, 0xdc, 0xc, + MA35_PIN(187, PL11, 0xdc, 0xc, MA35_MUX(0x0, "GPL11"), MA35_MUX(0x1, "EPWM0_CH5"), MA35_MUX(0x2, "UART14_TXD"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL2_DP"), MA35_MUX(0x5, "SPI3_MISO"), MA35_MUX(0x6, "EPWM1_CH5"), MA35_MUX(0x7, "I2S1_DO"), @@ -1446,7 +1524,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x9, "SC0_PWR"), MA35_MUX(0xb, "EBI_nWRL"), MA35_MUX(0xc, "QEI0_INDEX")), - MA35_PIN(182, PL12, 0xdc, 0x10, + MA35_PIN(188, PL12, 0xdc, 0x10, MA35_MUX(0x0, "GPL12"), MA35_MUX(0x1, "EPWM0_SYNC_IN"), MA35_MUX(0x2, "UART7_nCTS"), @@ -1463,7 +1541,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xd, "EBI_AD11"), MA35_MUX(0xe, "RGMII0_PPS"), MA35_MUX(0xf, "RMII0_PPS")), - MA35_PIN(183, PL13, 0xdc, 0x14, + MA35_PIN(189, PL13, 0xdc, 0x14, MA35_MUX(0x0, "GPL13"), MA35_MUX(0x1, "EPWM0_SYNC_OUT"), MA35_MUX(0x2, "UART7_nRTS"), @@ -1480,7 +1558,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xd, "EBI_AD12"), MA35_MUX(0xe, "RGMII1_PPS"), MA35_MUX(0xf, "RMII1_PPS")), - MA35_PIN(184, PL14, 0xdc, 0x18, + MA35_PIN(190, PL14, 0xdc, 0x18, MA35_MUX(0x0, "GPL14"), MA35_MUX(0x1, "EPWM0_CH2"), MA35_MUX(0x2, "UART7_RXD"), @@ -1492,7 +1570,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xb, "TM2"), MA35_MUX(0xc, "INT0"), MA35_MUX(0xd, "EBI_AD13")), - MA35_PIN(185, PL15, 0xdc, 0x1c, + MA35_PIN(191, PL15, 0xdc, 0x1c, MA35_MUX(0x0, "GPL15"), MA35_MUX(0x1, "EPWM0_CH1"), MA35_MUX(0x2, "UART7_TXD"), @@ -1505,86 +1583,92 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0xb, "TM2_EXT"), MA35_MUX(0xc, "INT2"), MA35_MUX(0xd, "EBI_AD14")), - MA35_PIN(186, PM0, 0xe0, 0x0, + MA35_PIN(192, PM0, 0xe0, 0x0, MA35_MUX(0x0, "GPM0"), MA35_MUX(0x4, "I2C4_SDA"), MA35_MUX(0x6, "CCAP0_VSYNC"), MA35_MUX(0x8, "EBI_AD3"), MA35_MUX(0xa, "EBI_ADR3")), - MA35_PIN(187, PM1, 0xe0, 0x4, + MA35_PIN(193, PM1, 0xe0, 0x4, MA35_MUX(0x0, "GPM1"), MA35_MUX(0x4, "I2C4_SCL"), MA35_MUX(0x5, "SPI3_I2SMCLK"), MA35_MUX(0x6, "CCAP0_SFIELD"), MA35_MUX(0x8, "EBI_AD4"), MA35_MUX(0xa, "EBI_ADR4")), - MA35_PIN(188, PM2, 0xe0, 0x8, + MA35_PIN(194, PM2, 0xe0, 0x8, MA35_MUX(0x0, "GPM2"), MA35_MUX(0x3, "CAN3_RXD"), + MA35_MUX(0x4, "USBHL0_DM"), MA35_MUX(0x6, "CCAP0_DATA0"), MA35_MUX(0x8, "EBI_AD5"), MA35_MUX(0xa, "EBI_ADR5")), - MA35_PIN(189, PM3, 0xe0, 0xc, + MA35_PIN(195, PM3, 0xe0, 0xc, MA35_MUX(0x0, "GPM3"), MA35_MUX(0x3, "CAN3_TXD"), + MA35_MUX(0x4, "USBHL0_DP"), MA35_MUX(0x6, "CCAP0_DATA1"), MA35_MUX(0x8, "EBI_AD6"), MA35_MUX(0xa, "EBI_ADR6")), - MA35_PIN(190, PM4, 0xe0, 0x10, + MA35_PIN(196, PM4, 0xe0, 0x10, MA35_MUX(0x0, "GPM4"), MA35_MUX(0x4, "I2C5_SDA"), MA35_MUX(0x6, "CCAP0_DATA2"), MA35_MUX(0x8, "EBI_AD7"), MA35_MUX(0xa, "EBI_ADR7")), - MA35_PIN(191, PM5, 0xe0, 0x14, + MA35_PIN(197, PM5, 0xe0, 0x14, MA35_MUX(0x0, "GPM5"), MA35_MUX(0x4, "I2C5_SCL"), MA35_MUX(0x6, "CCAP0_DATA3"), MA35_MUX(0x8, "EBI_AD8"), MA35_MUX(0xa, "EBI_ADR8")), - MA35_PIN(192, PM6, 0xe0, 0x18, + MA35_PIN(198, PM6, 0xe0, 0x18, MA35_MUX(0x0, "GPM6"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL1_DM"), MA35_MUX(0x6, "CCAP0_DATA4"), MA35_MUX(0x8, "EBI_AD9"), MA35_MUX(0xa, "EBI_ADR9")), - MA35_PIN(193, PM7, 0xe0, 0x1c, + MA35_PIN(199, PM7, 0xe0, 0x1c, MA35_MUX(0x0, "GPM7"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL1_DP"), MA35_MUX(0x6, "CCAP0_DATA5"), MA35_MUX(0x8, "EBI_AD10"), MA35_MUX(0xa, "EBI_ADR10")), - MA35_PIN(194, PM8, 0xe4, 0x0, + MA35_PIN(200, PM8, 0xe4, 0x0, MA35_MUX(0x0, "GPM8"), MA35_MUX(0x4, "I2C0_SDA"), MA35_MUX(0x6, "CCAP0_DATA6"), MA35_MUX(0x8, "EBI_AD11"), MA35_MUX(0xa, "EBI_ADR11")), - MA35_PIN(195, PM9, 0xe4, 0x4, + MA35_PIN(201, PM9, 0xe4, 0x4, MA35_MUX(0x0, "GPM9"), MA35_MUX(0x4, "I2C0_SCL"), MA35_MUX(0x6, "CCAP0_DATA7"), MA35_MUX(0x8, "EBI_AD12"), MA35_MUX(0xa, "EBI_ADR12")), - MA35_PIN(196, PM10, 0xe4, 0x8, + MA35_PIN(202, PM10, 0xe4, 0x8, MA35_MUX(0x0, "GPM10"), MA35_MUX(0x1, "EPWM1_CH2"), MA35_MUX(0x3, "CAN2_RXD"), + MA35_MUX(0x4, "USBHL4_DM"), MA35_MUX(0x5, "SPI3_SS0"), MA35_MUX(0x6, "CCAP0_DATA8"), MA35_MUX(0x7, "SPI2_I2SMCLK"), MA35_MUX(0x8, "EBI_AD13"), MA35_MUX(0xa, "EBI_ADR13")), - MA35_PIN(197, PM11, 0xe4, 0xc, + MA35_PIN(203, PM11, 0xe4, 0xc, MA35_MUX(0x0, "GPM11"), MA35_MUX(0x1, "EPWM1_CH3"), MA35_MUX(0x3, "CAN2_TXD"), + MA35_MUX(0x4, "USBHL4_DP"), MA35_MUX(0x5, "SPI3_SS1"), MA35_MUX(0x6, "CCAP0_DATA9"), MA35_MUX(0x7, "SPI2_SS1"), MA35_MUX(0x8, "EBI_AD14"), MA35_MUX(0xa, "EBI_ADR14")), - MA35_PIN(198, PM12, 0xe4, 0x10, + MA35_PIN(204, PM12, 0xe4, 0x10, MA35_MUX(0x0, "GPM12"), MA35_MUX(0x1, "EPWM1_CH4"), MA35_MUX(0x2, "UART10_nCTS"), @@ -1595,7 +1679,7 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "EBI_AD8"), MA35_MUX(0x9, "I2S1_MCLK"), MA35_MUX(0xb, "TM8")), - MA35_PIN(199, PM13, 0xe4, 0x14, + MA35_PIN(205, PM13, 0xe4, 0x14, MA35_MUX(0x0, "GPM13"), MA35_MUX(0x1, "EPWM1_CH5"), MA35_MUX(0x2, "UART10_nRTS"), @@ -1605,99 +1689,66 @@ static const struct pinctrl_pin_desc ma35d1_pins[] = { MA35_MUX(0x8, "EBI_AD9"), MA35_MUX(0x9, "ECAP1_IC0"), MA35_MUX(0xb, "TM8_EXT")), - MA35_PIN(200, PM14, 0xe4, 0x18, + MA35_PIN(206, PM14, 0xe4, 0x18, MA35_MUX(0x0, "GPM14"), MA35_MUX(0x1, "EPWM1_BRAKE0"), MA35_MUX(0x2, "UART10_RXD"), MA35_MUX(0x3, "TRACE_DATA2"), MA35_MUX(0x4, "CAN2_RXD"), + MA35_MUX(0x5, "USBHL3_DM"), MA35_MUX(0x6, "I2C3_SDA"), MA35_MUX(0x8, "EBI_AD10"), MA35_MUX(0x9, "ECAP1_IC1"), MA35_MUX(0xb, "TM10"), MA35_MUX(0xd, "INT1")), - MA35_PIN(201, PM15, 0xe4, 0x1c, + MA35_PIN(207, PM15, 0xe4, 0x1c, MA35_MUX(0x0, "GPM15"), MA35_MUX(0x1, "EPWM1_BRAKE1"), MA35_MUX(0x2, "UART10_TXD"), MA35_MUX(0x3, "TRACE_DATA3"), MA35_MUX(0x4, "CAN2_TXD"), + MA35_MUX(0x5, "USBHL3_DP"), MA35_MUX(0x6, "I2C3_SCL"), MA35_MUX(0x8, "EBI_AD11"), MA35_MUX(0x9, "ECAP1_IC2"), MA35_MUX(0xb, "TM10_EXT"), MA35_MUX(0xd, "INT2")), - MA35_PIN(202, PN0, 0xe8, 0x0, + MA35_PIN(208, PN0, 0xe8, 0x0, MA35_MUX(0x0, "GPN0"), MA35_MUX(0x4, "I2C2_SDA"), MA35_MUX(0x6, "CCAP1_DATA0")), - MA35_PIN(203, PN1, 0xe8, 0x4, + MA35_PIN(209, PN1, 0xe8, 0x4, MA35_MUX(0x0, "GPN1"), MA35_MUX(0x4, "I2C2_SCL"), MA35_MUX(0x6, "CCAP1_DATA1")), - MA35_PIN(204, PN2, 0xe8, 0x8, + MA35_PIN(210, PN2, 0xe8, 0x8, MA35_MUX(0x0, "GPN2"), MA35_MUX(0x3, "CAN0_RXD"), + MA35_MUX(0x4, "USBHL0_DM"), MA35_MUX(0x6, "CCAP1_DATA2")), - MA35_PIN(205, PN3, 0xe8, 0xc, + MA35_PIN(211, PN3, 0xe8, 0xc, MA35_MUX(0x0, "GPN3"), MA35_MUX(0x3, "CAN0_TXD"), + MA35_MUX(0x4, "USBHL0_DP"), MA35_MUX(0x6, "CCAP1_DATA3")), - MA35_PIN(206, PN4, 0xe8, 0x10, + MA35_PIN(212, PN4, 0xe8, 0x10, MA35_MUX(0x0, "GPN4"), MA35_MUX(0x4, "I2C1_SDA"), MA35_MUX(0x6, "CCAP1_DATA4")), - MA35_PIN(207, PN5, 0xe8, 0x14, + MA35_PIN(213, PN5, 0xe8, 0x14, MA35_MUX(0x0, "GPN5"), MA35_MUX(0x4, "I2C1_SCL"), MA35_MUX(0x6, "CCAP1_DATA5")), - MA35_PIN(208, PN6, 0xe8, 0x18, + MA35_PIN(214, PN6, 0xe8, 0x18, MA35_MUX(0x0, "GPN6"), MA35_MUX(0x3, "CAN1_RXD"), + MA35_MUX(0x4, "USBHL1_DM"), MA35_MUX(0x6, "CCAP1_DATA6")), - MA35_PIN(209, PN7, 0xe8, 0x1c, + MA35_PIN(215, PN7, 0xe8, 0x1c, MA35_MUX(0x0, "GPN7"), MA35_MUX(0x3, "CAN1_TXD"), + MA35_MUX(0x4, "USBHL1_DP"), MA35_MUX(0x6, "CCAP1_DATA7")), - MA35_PIN(210, PN10, 0xec, 0x8, - MA35_MUX(0x0, "GPN10"), - MA35_MUX(0x3, "CAN2_RXD"), - MA35_MUX(0x6, "CCAP1_SCLK")), - MA35_PIN(211, PN11, 0xec, 0xc, - MA35_MUX(0x0, "GPN11"), - MA35_MUX(0x3, "CAN2_TXD"), - MA35_MUX(0x6, "CCAP1_PIXCLK")), - MA35_PIN(212, PN12, 0xec, 0x10, - MA35_MUX(0x0, "GPN12"), - MA35_MUX(0x2, "UART6_nCTS"), - MA35_MUX(0x3, "UART12_RXD"), - MA35_MUX(0x4, "I2C5_SDA"), - MA35_MUX(0x6, "CCAP1_HSYNC")), - MA35_PIN(213, PN13, 0xec, 0x14, - MA35_MUX(0x0, "GPN13"), - MA35_MUX(0x2, "UART6_nRTS"), - MA35_MUX(0x3, "UART12_TXD"), - MA35_MUX(0x4, "I2C5_SCL"), - MA35_MUX(0x6, "CCAP1_VSYNC")), - MA35_PIN(214, PN14, 0xec, 0x18, - MA35_MUX(0x0, "GPN14"), - MA35_MUX(0x2, "UART6_RXD"), - MA35_MUX(0x3, "CAN3_RXD"), - MA35_MUX(0x5, "SPI1_SS1"), - MA35_MUX(0x6, "CCAP1_SFIELD"), - MA35_MUX(0x7, "SPI1_I2SMCLK")), - MA35_PIN(215, PN15, 0xec, 0x1c, - MA35_MUX(0x0, "GPN15"), - MA35_MUX(0x1, "EPWM2_CH4"), - MA35_MUX(0x2, "UART6_TXD"), - MA35_MUX(0x3, "CAN3_TXD"), - MA35_MUX(0x5, "I2S0_MCLK"), - MA35_MUX(0x6, "SPI1_SS1"), - MA35_MUX(0x7, "SPI1_I2SMCLK"), - MA35_MUX(0x8, "SC0_nCD"), - MA35_MUX(0x9, "EADC0_ST"), - MA35_MUX(0xa, "CLKO"), - MA35_MUX(0xb, "TM6")), MA35_PIN(216, PN8, 0xec, 0x0, MA35_MUX(0x0, "GPN8"), MA35_MUX(0x1, "EPWM2_CH4"), diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 13ed87d5d30c..e051ff141d6c 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -8,7 +8,6 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/mfd/syscon.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> @@ -260,11 +259,10 @@ static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type) return -EINVAL; } - if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (type & IRQ_TYPE_LEVEL_MASK) { npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_level_irq); - } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING - | IRQ_TYPE_EDGE_FALLING)) { + } else if (type & IRQ_TYPE_EDGE_BOTH) { npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_edge_irq); } diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 0aae1a253459..6150cde7e824 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -11,7 +11,6 @@ #include <linux/module.h> #include <linux/debugfs.h> #include <linux/seq_file.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> @@ -26,6 +25,7 @@ #define NPCM8XX_GCR_SRCNT 0x068 #define NPCM8XX_GCR_FLOCKR1 0x074 #define NPCM8XX_GCR_DSCNT 0x078 +#define NPCM8XX_GCR_INTCR4 0x0c0 #define NPCM8XX_GCR_I2CSEGSEL 0x0e0 #define NPCM8XX_GCR_MFSEL1 0x260 #define NPCM8XX_GCR_MFSEL2 0x264 @@ -78,6 +78,11 @@ #define NPCM8XX_GPIO_PER_BANK 32 #define NPCM8XX_GPIO_BANK_NUM 8 #define NPCM8XX_GCR_NONE 0 +#define NPCM8XX_INTCR4_R1_RMII_EN BIT(12) +#define NPCM8XX_INTCR4_R2_RMII_EN BIT(13) +#define NPCM8XX_INTCR4_RMII3_EN BIT(14) +#define NPCM8XX_GCR_DSCNT_RG2DS_SHIFT 6 +#define NPCM8XX_GCR_DSCNT_RG2DS_MASK GENMASK(7, 6) #define NPCM8XX_DEBOUNCE_MAX 4 #define NPCM8XX_DEBOUNCE_NSEC 40 @@ -291,17 +296,33 @@ static void npcmgpio_irq_unmask(struct irq_data *d) static unsigned int npcmgpio_irq_startup(struct irq_data *d) { - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - unsigned int gpio = irqd_to_hwirq(d); - - /* active-high, input, clear interrupt, enable interrupt */ - npcmgpio_direction_input(gc, gpio); npcmgpio_irq_ack(d); npcmgpio_irq_unmask(d); return 0; } +static int npcmgpio_irq_request_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int gpio = irqd_to_hwirq(d); + int ret; + + ret = npcmgpio_direction_input(gc, gpio); + if (ret) + return ret; + + return gpiochip_reqres_irq(gc, gpio); +} + +static void npcmgpio_irq_release_resources(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int gpio = irqd_to_hwirq(d); + + gpiochip_relres_irq(gc, gpio); +} + static struct irq_chip npcmgpio_irqchip = { .name = "NPCM8XX-GPIO-IRQ", .irq_ack = npcmgpio_irq_ack, @@ -309,8 +330,9 @@ static struct irq_chip npcmgpio_irqchip = { .irq_mask = npcmgpio_irq_mask, .irq_set_type = npcmgpio_set_irq_type, .irq_startup = npcmgpio_irq_startup, + .irq_request_resources = npcmgpio_irq_request_resources, + .irq_release_resources = npcmgpio_irq_release_resources, .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static const int gpi36_pins[] = { 36 }; @@ -538,7 +560,7 @@ static const int wdog2_pins[] = { 219 }; static const int bmcuart0a_pins[] = { 41, 42 }; static const int bmcuart0b_pins[] = { 48, 49 }; -static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; +static const int bmcuart1_pins[] = { 43, 63 }; static const int scipme_pins[] = { 169 }; static const int smi_pins[] = { 170 }; @@ -1283,6 +1305,7 @@ static struct pinfunction npcm8xx_funcs[] = { #define DRIVE_STRENGTH_LO_SHIFT 8 #define DRIVE_STRENGTH_HI_SHIFT 12 #define DRIVE_STRENGTH_MASK GENMASK(15, 8) +#define DSTR_RG2 BIT(16) #define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ ((hi) << DRIVE_STRENGTH_HI_SHIFT)) @@ -1415,10 +1438,10 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), - NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), @@ -1441,14 +1464,14 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), - NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), - NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), @@ -1509,8 +1532,8 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), - NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ - NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ + NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), + NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR_RG2 | SLEW), NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), @@ -1560,7 +1583,7 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = { PINCTRL_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"), PINCTRL_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"), PINCTRL_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"), - PINCTRL_PIN(7, "GPIO7/IOX2_D0/SMB2D_SCL"), + PINCTRL_PIN(7, "GPIO7/IOX2_DO/SMB2D_SCL"), PINCTRL_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"), PINCTRL_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"), PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"), @@ -1796,6 +1819,61 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = { PINCTRL_PIN(251, "JM2/CP1_GPIO"), }; +static u32 npcm8xx_rmii_output_enable_mask(unsigned int pin) +{ + switch (pin) { + case 178: + case 179: + case 180: + case 181: + case 182: + case 193: + case 201: + return NPCM8XX_INTCR4_R1_RMII_EN; + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 200: + return NPCM8XX_INTCR4_R2_RMII_EN; + case 110: + case 111: + case 209: + case 210: + case 211: + case 214: + case 215: + return NPCM8XX_INTCR4_RMII3_EN; + default: + return 0; + } +} + +static void npcm8xx_set_rmii_output_enable(struct regmap *gcr_regmap, + const unsigned int *pin, + int pin_number, int mode) +{ + u32 mask = 0; + u32 val = 0; + u32 bit; + int i; + + for (i = 0; i < pin_number; i++) { + bit = npcm8xx_rmii_output_enable_mask(pin[i]); + mask |= bit; + + if ((mode == fn_r1 && bit == NPCM8XX_INTCR4_R1_RMII_EN) || + (mode == fn_r2 && bit == NPCM8XX_INTCR4_R2_RMII_EN) || + (mode == fn_rmii3 && bit == NPCM8XX_INTCR4_RMII3_EN)) + val |= bit; + } + + if (mask) + regmap_update_bits(gcr_regmap, NPCM8XX_GCR_INTCR4, mask, val); +} + /* Enable mode in pin group */ static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, int pin_number, int mode) @@ -1834,6 +1912,8 @@ static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, BIT(cfg->bit4) : 0); } } + + npcm8xx_set_rmii_output_enable(gcr_regmap, pin, pin_number, mode); } static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, @@ -1893,6 +1973,56 @@ static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank, return 0; } +static int npcm8xx_get_rg2_drive_strength(struct npcm8xx_pinctrl *npcm) +{ + u32 val; + int ret; + + ret = regmap_read(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT, &val); + if (ret) + return ret; + + switch ((val & NPCM8XX_GCR_DSCNT_RG2DS_MASK) >> + NPCM8XX_GCR_DSCNT_RG2DS_SHIFT) { + case 0: + return 8; + case 1: + return 12; + case 2: + return 16; + case 3: + return 24; + default: + return -EINVAL; + } +} + +static int npcm8xx_set_rg2_drive_strength(struct npcm8xx_pinctrl *npcm, int nval) +{ + u32 val; + + switch (nval) { + case 8: + val = 0; + break; + case 12: + val = 1; + break; + case 16: + val = 2; + break; + case 24: + val = 3; + break; + default: + return -EOPNOTSUPP; + } + + return regmap_update_bits(npcm->gcr_regmap, NPCM8XX_GCR_DSCNT, + NPCM8XX_GCR_DSCNT_RG2DS_MASK, + val << NPCM8XX_GCR_DSCNT_RG2DS_SHIFT); +} + static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, unsigned int pin) { @@ -1901,10 +2031,13 @@ static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; int gpio = pin % bank->chip.gc.ngpio; unsigned long pinmask = BIT(gpio); - int flg, val; - u32 ds = 0; + int flg, ds; + u32 val; flg = pincfg[pin].flag; + if (flg & DSTR_RG2) + return npcm8xx_get_rg2_drive_strength(npcm); + if (!(flg & DRIVE_STRENGTH_MASK)) return -EINVAL; @@ -1923,6 +2056,9 @@ static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm, int gpio = BIT(pin % bank->chip.gc.ngpio); int v; + if (pincfg[pin].flag & DSTR_RG2) + return npcm8xx_set_rg2_drive_strength(npcm, nval); + v = pincfg[pin].flag & DRIVE_STRENGTH_MASK; if (DSLO(v) == nval) @@ -2074,7 +2210,8 @@ static const struct pinmux_ops npcm8xx_pinmux_ops = { static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio, u32 nanosecs) { - void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4); + void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + + (gpio / 16) * 4; int gpio_debounce = (gpio % 16) * 2, debounce_select, i; u32 dbncp_val, dbncp_val_mod; @@ -2351,6 +2488,9 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) if (ret < 0) return dev_err_probe(dev, ret, "Failed to retrieve IRQ for bank %u\n", id); + iowrite32(0, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVEN); + iowrite32(0xffffffff, pctrl->gpio_bank[id].base + NPCM8XX_GP_N_EVST); + pctrl->gpio_bank[id].irq = ret; pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index d624a4d302a8..bc030abdadca 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -16,7 +16,6 @@ #include <linux/irq.h> #include <linux/mfd/syscon.h> #include <linux/module.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c index fe7cd641fddd..4b40770a38b7 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32cc.c +++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c @@ -2,7 +2,7 @@ /* * Core driver for the S32 CC (Common Chassis) pin controller * - * Copyright 2017-2022,2024 NXP + * Copyright 2017-2022,2024-2025 NXP * Copyright (C) 2022 SUSE LLC * Copyright 2015-2016 Freescale Semiconductor, Inc. */ @@ -60,6 +60,12 @@ static u32 get_pin_func(u32 pinmux) return pinmux & GENMASK(3, 0); } +/* + * struct s32_pinctrl_mem_region - memory region for a set of SIUL2 registers + * @map: regmap used for this range + * @pin_range: the pins controlled by these registers + * @name: name of the current range + */ struct s32_pinctrl_mem_region { struct regmap *map; const struct s32_pin_range *pin_range; @@ -67,7 +73,7 @@ struct s32_pinctrl_mem_region { }; /* - * Holds pin configuration for GPIO's. + * struct gpio_pin_config - holds pin configuration for GPIO's * @pin_id: Pin ID for this GPIO * @config: Pin settings * @list: Linked list entry for each gpio pin @@ -79,20 +85,22 @@ struct gpio_pin_config { }; /* - * Pad config save/restore for power suspend/resume. + * struct s32_pinctrl_context - pad config save/restore for suspend/resume + * @pads: saved values for the pads */ struct s32_pinctrl_context { unsigned int *pads; }; /* + * struct s32_pinctrl - private driver data * @dev: a pointer back to containing device * @pctl: a pointer to the pinctrl device structure * @regions: reserved memory regions with start/end pin * @info: structure containing information about the pin - * @gpio_configs: Saved configurations for GPIO pins - * @gpiop_configs_lock: lock for the `gpio_configs` list - * @s32_pinctrl_context: Configuration saved over system sleep + * @gpio_configs: saved configurations for GPIO pins + * @gpio_configs_lock: lock for the `gpio_configs` list + * @saved_context: configuration saved over system sleep */ struct s32_pinctrl { struct device *dev; @@ -123,13 +131,13 @@ s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin) return NULL; } -static inline int s32_check_pin(struct pinctrl_dev *pctldev, - unsigned int pin) +static int s32_check_pin(struct pinctrl_dev *pctldev, + unsigned int pin) { return s32_get_region(pctldev, pin) ? 0 : -EINVAL; } -static inline int s32_regmap_read(struct pinctrl_dev *pctldev, +static int s32_regmap_read(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int *val) { struct s32_pinctrl_mem_region *region; @@ -145,7 +153,7 @@ static inline int s32_regmap_read(struct pinctrl_dev *pctldev, return regmap_read(region->map, offset, val); } -static inline int s32_regmap_write(struct pinctrl_dev *pctldev, +static int s32_regmap_write(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int val) { @@ -163,7 +171,7 @@ static inline int s32_regmap_write(struct pinctrl_dev *pctldev, } -static inline int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, +static int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin, unsigned int mask, unsigned int val) { struct s32_pinctrl_mem_region *region; @@ -236,10 +244,10 @@ static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev, } ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs); - if (ret) { - dev_err(dev, "%pOF: could not parse node property\n", np); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, + "%pOF: could not parse node property\n", + np); if (n_cfgs) reserve++; @@ -476,8 +484,8 @@ static int s32_get_slew_regval(int arg) return -EINVAL; } -static inline void s32_pin_set_pull(enum pin_config_param param, - unsigned int *mask, unsigned int *config) +static void s32_pin_set_pull(enum pin_config_param param, + unsigned int *mask, unsigned int *config) { switch (param) { case PIN_CONFIG_BIAS_DISABLE: @@ -763,15 +771,15 @@ static int s32_pinctrl_parse_groups(struct device_node *np, grp->data.name = np->name; npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32)); - if (npins < 0) { - dev_err(dev, "Failed to read 'pinmux' property in node %s.\n", - grp->data.name); - return -EINVAL; - } - if (!npins) { - dev_err(dev, "The group %s has no pins.\n", grp->data.name); - return -EINVAL; - } + if (npins < 0) + return dev_err_probe(dev, -EINVAL, + "Failed to read 'pinmux' in node %s\n", + grp->data.name); + + if (!npins) + return dev_err_probe(dev, -EINVAL, + "The group %s has no pins\n", + grp->data.name); grp->data.npins = npins; @@ -812,10 +820,9 @@ static int s32_pinctrl_parse_functions(struct device_node *np, /* Initialise function */ func->name = np->name; func->ngroups = of_get_child_count(np); - if (func->ngroups == 0) { - dev_err(info->dev, "no groups defined in %pOF\n", np); - return -EINVAL; - } + if (func->ngroups == 0) + return dev_err_probe(info->dev, -EINVAL, + "No groups defined in %pOF\n", np); groups = devm_kcalloc(info->dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); @@ -886,10 +893,9 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev, } nfuncs = of_get_child_count(np); - if (nfuncs <= 0) { - dev_err(&pdev->dev, "no functions defined\n"); - return -EINVAL; - } + if (nfuncs <= 0) + return dev_err_probe(&pdev->dev, -EINVAL, + "No functions defined\n"); info->nfunctions = nfuncs; info->functions = devm_kcalloc(&pdev->dev, nfuncs, @@ -919,18 +925,17 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev, int s32_pinctrl_probe(struct platform_device *pdev, const struct s32_pinctrl_soc_data *soc_data) { - struct s32_pinctrl *ipctl; - int ret; - struct pinctrl_desc *s32_pinctrl_desc; - struct s32_pinctrl_soc_info *info; #ifdef CONFIG_PM_SLEEP struct s32_pinctrl_context *saved_context; #endif + struct pinctrl_desc *s32_pinctrl_desc; + struct s32_pinctrl_soc_info *info; + struct s32_pinctrl *ipctl; + int ret; - if (!soc_data || !soc_data->pins || !soc_data->npins) { - dev_err(&pdev->dev, "wrong pinctrl info\n"); - return -EINVAL; - } + if (!soc_data || !soc_data->pins || !soc_data->npins) + return dev_err_probe(&pdev->dev, -EINVAL, + "Wrong pinctrl info\n"); info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -965,16 +970,15 @@ int s32_pinctrl_probe(struct platform_device *pdev, s32_pinctrl_desc->owner = THIS_MODULE; ret = s32_pinctrl_probe_dt(pdev, ipctl); - if (ret) { - dev_err(&pdev->dev, "fail to probe dt properties\n"); - return ret; - } + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Fail to probe dt properties\n"); - ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc, - ipctl); - if (IS_ERR(ipctl->pctl)) - return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl), - "could not register s32 pinctrl driver\n"); + ret = devm_pinctrl_register_and_init(&pdev->dev, s32_pinctrl_desc, + ipctl, &ipctl->pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Could not register s32 pinctrl driver\n"); #ifdef CONFIG_PM_SLEEP saved_context = &ipctl->saved_context; @@ -986,7 +990,12 @@ int s32_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; #endif - dev_info(&pdev->dev, "initialized s32 pinctrl driver\n"); + ret = pinctrl_enable(ipctl->pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to enable pinctrl\n"); + + dev_info(&pdev->dev, "Initialized S32 pinctrl driver\n"); return 0; } diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 64ed28309788..95c803c40a7d 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -225,10 +225,9 @@ static int parse_fw_cfg(struct fwnode_handle *fwnode, unsigned int count, unsigned long *cfg, unsigned int *ncfg) { - unsigned long *properties; int i, test; - properties = bitmap_zalloc(count, GFP_KERNEL); + unsigned long *properties __free(bitmap) = bitmap_zalloc(count, GFP_KERNEL); for (i = 0; i < count; i++) { u32 val; @@ -263,7 +262,6 @@ static int parse_fw_cfg(struct fwnode_handle *fwnode, if (ret) { pr_err("%pfw: conflicting setting detected for %s\n", fwnode, par->property); - bitmap_free(properties); return -EINVAL; } } @@ -295,7 +293,6 @@ static int parse_fw_cfg(struct fwnode_handle *fwnode, pr_err("%pfw: cannot have multiple drive configurations\n", fwnode); - bitmap_free(properties); return 0; } @@ -419,7 +416,7 @@ int pinconf_generic_parse_dt_config(struct device_node *np, * Now limit the number of configs to the real number of * found properties. */ - *configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL); + *configs = kmemdup_array(cfg, ncfg, sizeof(unsigned long), GFP_KERNEL); if (!*configs) { ret = -ENOMEM; goto out; diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index dca963633b5d..81686844dfa5 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -275,7 +275,7 @@ void pinconf_show_setting(struct seq_file *s, case PIN_MAP_TYPE_CONFIGS_GROUP: seq_printf(s, "group %s (%d)", pctlops->get_group_name(pctldev, - setting->data.configs.group_or_pin), + setting->data.configs.group_or_pin), setting->data.configs.group_or_pin); break; default: @@ -348,8 +348,13 @@ static int pinconf_groups_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - unsigned int ngroups = pctlops->get_groups_count(pctldev); unsigned int selector = 0; + unsigned int ngroups; + + if (!pctlops->get_groups_count || !pctlops->get_group_name) + return 0; + + ngroups = pctlops->get_groups_count(pctldev); seq_puts(s, "Pin config settings per pin group\n"); seq_puts(s, "Format: group (name): configs\n"); diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index 659a781e2091..fc2d6cce9afb 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -167,11 +167,22 @@ pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, } #endif -#if defined(CONFIG_GENERIC_PINCTRL) && defined (CONFIG_OF) +#if defined(CONFIG_GENERIC_PINCTRL) int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **maps, unsigned int *num_maps); + +int pinctrl_generic_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps); + +int pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent, + struct device_node *np, struct pinctrl_map **maps, + unsigned int *num_maps, unsigned int *num_reserved_maps, + const char **group_name, unsigned int ngroups, + void *data, unsigned int *pins, unsigned int npins); #else static inline int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, @@ -181,4 +192,23 @@ pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, { return -ENOTSUPP; } + +static inline int +pinctrl_generic_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + return -ENOTSUPP; +} + +static inline int +pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent, + struct device_node *np, struct pinctrl_map **maps, + unsigned int *num_maps, unsigned int *num_reserved_maps, + const char **group_name, unsigned int ngroups, + void *data, unsigned int *pins, unsigned int npins) +{ + return -ENOTSUPP; +} #endif diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index e3128b0045d2..15a398bb3be2 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -884,8 +884,7 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) u32 pin_reg, mask; int i; - mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | - BIT(WAKE_CNTRL_OFF_S4); + mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); for (i = 0; i < desc->npins; i++) { int pin = desc->pins[i].number; diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c index e713dea98aa8..3d2f477aac9e 100644 --- a/drivers/pinctrl/pinctrl-as3722.c +++ b/drivers/pinctrl/pinctrl-as3722.c @@ -10,7 +10,6 @@ #include <linux/delay.h> #include <linux/gpio/driver.h> #include <linux/kernel.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mfd/as3722.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/pinctrl-aw9523.c b/drivers/pinctrl/pinctrl-aw9523.c index 02a24ac87ea4..a13b1cdb78ea 100644 --- a/drivers/pinctrl/pinctrl-aw9523.c +++ b/drivers/pinctrl/pinctrl-aw9523.c @@ -817,7 +817,7 @@ static int aw9523_init_irq(struct aw9523 *awi, int irq) ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func, IRQF_ONESHOT, dev_name(dev), awi); if (ret) - return dev_err_probe(dev, ret, "Failed to request irq %d\n", irq); + return ret; girq = &awi->gpio.irq; gpio_irq_chip_set_chip(girq, &aw9523_irq_chip); @@ -1033,7 +1033,7 @@ static void aw9523_remove(struct i2c_client *client) } static const struct i2c_device_id aw9523_i2c_id_table[] = { - { "aw9523_i2c" }, + { .name = "aw9523_i2c" }, { } }; MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table); diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index ace0be5ec679..9a54b259ef4b 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -16,7 +16,6 @@ #include <linux/i2c.h> #include <linux/init.h> #include <linux/interrupt.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/property.h> #include <linux/regmap.h> @@ -1461,9 +1460,9 @@ static int cy8c95x0_probe(struct i2c_client *client) } static const struct i2c_device_id cy8c95x0_id[] = { - { "cy8c9520", 20 }, - { "cy8c9540", 40 }, - { "cy8c9560", 60 }, + { .name = "cy8c9520", .driver_data = 20 }, + { .name = "cy8c9540", .driver_data = 40 }, + { .name = "cy8c9560", .driver_data = 60 }, { } }; MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); diff --git a/drivers/pinctrl/pinctrl-da850-pupd.c b/drivers/pinctrl/pinctrl-da850-pupd.c index 5eb248663e17..c5f243d1311f 100644 --- a/drivers/pinctrl/pinctrl-da850-pupd.c +++ b/drivers/pinctrl/pinctrl-da850-pupd.c @@ -9,7 +9,6 @@ #include <linux/device.h> #include <linux/io.h> #include <linux/ioport.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c index 2e16f09aeb47..58f22b4a5a6f 100644 --- a/drivers/pinctrl/pinctrl-digicolor.c +++ b/drivers/pinctrl/pinctrl-digicolor.c @@ -14,7 +14,6 @@ #include <linux/gpio/driver.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/spinlock.h> diff --git a/drivers/pinctrl/pinctrl-eic7700.c b/drivers/pinctrl/pinctrl-eic7700.c index ffcd0ec5c2dc..09a3b097383c 100644 --- a/drivers/pinctrl/pinctrl-eic7700.c +++ b/drivers/pinctrl/pinctrl-eic7700.c @@ -11,7 +11,6 @@ #include <linux/bitfield.h> #include <linux/device.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -423,6 +422,9 @@ static int eic7700_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, else value &= ~EIC7700_ST; break; + /* All pins are persistent over suspend */ + case PIN_CONFIG_PERSIST_STATE: + return 0; default: return -EOPNOTSUPP; } diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c index ba1c867b7b89..349eb944b4ac 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -532,8 +532,9 @@ static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { - unsigned int i, npins, old = 0; const unsigned int *pins; + unsigned int i, npins; + unsigned long old = 0; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c index dcdf80f07a90..19d845b47939 100644 --- a/drivers/pinctrl/pinctrl-eyeq5.c +++ b/drivers/pinctrl/pinctrl-eyeq5.c @@ -25,7 +25,6 @@ #include <linux/err.h> #include <linux/errno.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/seq_file.h> #include <linux/slab.h> diff --git a/drivers/pinctrl/pinctrl-generic-mux.c b/drivers/pinctrl/pinctrl-generic-mux.c new file mode 100644 index 000000000000..202b72351efb --- /dev/null +++ b/drivers/pinctrl/pinctrl-generic-mux.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Generic Pin Control Driver for Board-Level Mux Chips + * Copyright 2026 NXP + */ + +#include <linux/cleanup.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/mutex.h> +#include <linux/mux/consumer.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> + +#include "core.h" +#include "pinconf.h" +#include "pinmux.h" +#include "pinctrl-utils.h" + +struct mux_pin_function { + struct mux_state *mux_state; +}; + +struct mux_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + + /* mutex protect [pinctrl|pinmux]_generic functions */ + struct mutex lock; +}; + +static int +mux_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **maps, unsigned int *num_maps) +{ + unsigned int num_reserved_maps = 0; + struct mux_pin_function *function; + const char **group_names; + int ret; + + function = devm_kzalloc(pctldev->dev, sizeof(*function), GFP_KERNEL); + if (!function) + return -ENOMEM; + + group_names = devm_kcalloc(pctldev->dev, 1, sizeof(*group_names), GFP_KERNEL); + if (!group_names) + return -ENOMEM; + + function->mux_state = devm_mux_state_get_from_np(pctldev->dev, NULL, np_config); + if (IS_ERR(function->mux_state)) + return PTR_ERR(function->mux_state); + + ret = pinctrl_generic_to_map(pctldev, np_config, np_config, maps, + num_maps, &num_reserved_maps, group_names, + 0, &np_config->name, NULL, 0); + + if (ret) + return ret; + + ret = pinmux_generic_add_function(pctldev, np_config->name, group_names, + 1, function); + if (ret < 0) { + pinctrl_utils_free_map(pctldev, *maps, *num_maps); + return ret; + } + + return 0; +} + +static const struct pinctrl_ops mux_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = mux_pinmux_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int mux_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct mux_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev); + const struct function_desc *function; + struct mux_pin_function *func; + int ret; + + guard(mutex)(&mpctl->lock); + + function = pinmux_generic_get_function(pctldev, func_selector); + func = function->data; + + ret = mux_state_try_select(func->mux_state); + if (ret) + return ret; + + return 0; +} + +static void mux_pinmux_release_mux(struct pinctrl_dev *pctldev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct mux_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev); + const struct function_desc *function; + struct mux_pin_function *func; + + guard(mutex)(&mpctl->lock); + + function = pinmux_generic_get_function(pctldev, func_selector); + func = function->data; + + mux_state_deselect(func->mux_state); +} + +static const struct pinmux_ops mux_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = mux_pinmux_set_mux, + .release_mux = mux_pinmux_release_mux, +}; + +static int mux_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mux_pinctrl *mpctl; + struct pinctrl_desc *pctl_desc; + int ret; + + mpctl = devm_kzalloc(dev, sizeof(*mpctl), GFP_KERNEL); + if (!mpctl) + return -ENOMEM; + + mpctl->dev = dev; + + platform_set_drvdata(pdev, mpctl); + + pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); + if (!pctl_desc) + return -ENOMEM; + + ret = devm_mutex_init(dev, &mpctl->lock); + if (ret) + return ret; + + pctl_desc->name = dev_name(dev); + pctl_desc->owner = THIS_MODULE; + pctl_desc->pctlops = &mux_pinctrl_ops; + pctl_desc->pmxops = &mux_pinmux_ops; + + ret = devm_pinctrl_register_and_init(dev, pctl_desc, mpctl, + &mpctl->pctl); + if (ret) + return dev_err_probe(dev, ret, "Failed to register pinctrl.\n"); + + ret = pinctrl_enable(mpctl->pctl); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable pinctrl.\n"); + + return 0; +} + +static const struct of_device_id mux_pinctrl_of_match[] = { + { .compatible = "pinctrl-multiplexer" }, + { } +}; +MODULE_DEVICE_TABLE(of, mux_pinctrl_of_match); + +static struct platform_driver mux_pinctrl_driver = { + .driver = { + .name = "generic-pinctrl-mux", + .of_match_table = mux_pinctrl_of_match, + }, + .probe = mux_pinctrl_probe, +}; +module_platform_driver(mux_pinctrl_driver); + +MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>"); +MODULE_DESCRIPTION("Generic Pin Control Driver for Board-Level Mux Chips"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c index efb39c6a6703..4277c8748513 100644 --- a/drivers/pinctrl/pinctrl-generic.c +++ b/drivers/pinctrl/pinctrl-generic.c @@ -3,8 +3,10 @@ #define pr_fmt(fmt) "generic pinconfig core: " fmt #include <linux/array_size.h> +#include <linux/cleanup.h> #include <linux/device.h> #include <linux/module.h> +#include <linux/mutex.h> #include <linux/of.h> #include <linux/slab.h> @@ -17,6 +19,72 @@ #include "pinctrl-utils.h" #include "pinmux.h" +int pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent, + struct device_node *np, struct pinctrl_map **maps, + unsigned int *num_maps, unsigned int *num_reserved_maps, + const char **group_names, unsigned int ngroups, + void *data, unsigned int *pins, unsigned int npins) +{ + struct device *dev = pctldev->dev; + unsigned int num_configs; + const char *group_name; + unsigned long *configs; + int ret, reserve = 1; + + group_name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", parent, np); + if (!group_name) + return -ENOMEM; + + group_names[ngroups] = group_name; + + ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve); + if (ret) + return ret; + + ret = pinctrl_utils_add_map_mux(pctldev, maps, num_reserved_maps, num_maps, group_name, + parent->name); + if (ret < 0) + goto err_free_map; + + ret = pinctrl_generic_add_group(pctldev, group_name, pins, npins, data); + if (ret < 0) { + dev_err_probe(dev, ret, "failed to add group %s: %d\n", + group_name, ret); + goto err_free_map; + } + + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); + if (ret) { + dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", + group_name); + goto err_free_map; + } + + if (num_configs == 0) + return 0; + + ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve); + if (ret) + goto err_free_map; + + ret = pinctrl_utils_add_map_configs(pctldev, maps, num_reserved_maps, num_maps, group_name, + configs, + num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); + kfree(configs); + if (ret) + goto err_free_map; + + return 0; + +err_free_map: + pinctrl_utils_free_map(pctldev, *maps, *num_maps); + *maps = NULL; + *num_maps = 0; + *num_reserved_maps = 0; + return ret; +}; +EXPORT_SYMBOL_GPL(pinctrl_generic_to_map); + static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *parent, struct device_node *np, @@ -27,11 +95,9 @@ static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *p unsigned int ngroups) { struct device *dev = pctldev->dev; + unsigned int pin, *pins; const char **functions; - const char *group_name; - unsigned long *configs; - unsigned int num_configs, pin, *pins; - int npins, ret, reserve = 1; + int npins, ret; npins = of_property_count_u32_elems(np, "pins"); @@ -41,12 +107,6 @@ static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *p return npins; } - group_name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", parent, np); - if (!group_name) - return -ENOMEM; - - group_names[ngroups] = group_name; - pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); if (!pins) return -ENOMEM; @@ -67,53 +127,69 @@ static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *p return ret; } - ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve); - if (ret) - return ret; + return pinctrl_generic_to_map(pctldev, parent, np, maps, num_maps, + num_reserved_maps, group_names, ngroups, + functions, pins, npins); +} - ret = pinctrl_utils_add_map_mux(pctldev, maps, num_reserved_maps, num_maps, group_name, - parent->name); - if (ret < 0) - return ret; +static int pinctrl_generic_pinmux_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *parent, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps, + unsigned int *num_reserved_maps, + const char **group_names, + unsigned int ngroups) +{ + struct device *dev = pctldev->dev; + unsigned int *pins, *muxes; + int npins, ret; - ret = pinctrl_generic_add_group(pctldev, group_name, pins, npins, functions); - if (ret < 0) - return dev_err_probe(dev, ret, "failed to add group %s: %d\n", - group_name, ret); + npins = of_property_count_u32_elems(np, "pinmux"); - ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); - if (ret) - return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", - group_name); + if (npins < 1) { + dev_err(dev, "invalid pinctrl group %pOFn.%pOFn %d\n", + parent, np, npins); + return npins; + } - if (num_configs == 0) - return 0; + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; - ret = pinctrl_utils_reserve_map(pctldev, maps, num_reserved_maps, num_maps, reserve); - if (ret) - return ret; + muxes = devm_kcalloc(dev, npins, sizeof(*muxes), GFP_KERNEL); + if (!muxes) + return -ENOMEM; - ret = pinctrl_utils_add_map_configs(pctldev, maps, num_reserved_maps, num_maps, group_name, - configs, - num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); - kfree(configs); - if (ret) - return ret; + for (int i = 0; i < npins; i++) { + unsigned int pinmux; - return 0; -}; + ret = of_property_read_u32_index(np, "pinmux", i, &pinmux); + if (ret) + return ret; -/* - * For platforms that do not define groups or functions in the driver, but - * instead use the devicetree to describe them. This function will, unlike - * pinconf_generic_dt_node_to_map() etc which rely on driver defined groups - * and functions, create them in addition to parsing pinconf properties and - * adding mappings. - */ -int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **maps, - unsigned int *num_maps) + pins[i] = pinmux >> 16; + muxes[i] = pinmux & GENMASK(15, 0); + } + + return pinctrl_generic_to_map(pctldev, parent, np, maps, num_maps, + num_reserved_maps, group_names, ngroups, + muxes, pins, npins); +} + +static int pinctrl_generic_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps, + int (dt_subnode_to_map)( + struct pinctrl_dev *, + struct device_node *, + struct device_node *, + struct pinctrl_map **, + unsigned int *, + unsigned int *, + const char **, + unsigned int)) { struct device *dev = pctldev->dev; struct device_node *child_np; @@ -122,6 +198,8 @@ int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, int ngroups = 0; int ret; + guard(mutex)(&pctldev->mutex); + *maps = NULL; *num_maps = 0; @@ -136,11 +214,8 @@ int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, if (!group_names) return -ENOMEM; - ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, np, - maps, num_maps, - &num_reserved_maps, - group_names, - ngroups); + ret = dt_subnode_to_map(pctldev, np, np, maps, num_maps, + &num_reserved_maps, group_names, ngroups); if (ret) { pinctrl_utils_free_map(pctldev, *maps, *num_maps); return dev_err_probe(dev, ret, "error figuring out mappings for %s\n", np->name); @@ -164,11 +239,8 @@ parent: ngroups = 0; for_each_available_child_of_node_scoped(np, child_np) { - ret = pinctrl_generic_pins_function_dt_subnode_to_map(pctldev, np, child_np, - maps, num_maps, - &num_reserved_maps, - group_names, - ngroups); + ret = dt_subnode_to_map(pctldev, np, child_np, maps, num_maps, + &num_reserved_maps, group_names, ngroups); if (ret) { pinctrl_utils_free_map(pctldev, *maps, *num_maps); return dev_err_probe(dev, ret, "error figuring out mappings for %s\n", @@ -186,4 +258,40 @@ parent: return 0; } + +/* + * For platforms that do not define groups or functions in the driver, but + * instead use the devicetree to describe them. This function will, unlike + * pinconf_generic_dt_node_to_map() etc which rely on driver defined groups + * and functions, create them in addition to parsing pinconf properties and + * adding mappings. + */ +int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + return pinctrl_generic_dt_node_to_map(pctldev, np, maps, num_maps, + &pinctrl_generic_pins_function_dt_subnode_to_map); +} EXPORT_SYMBOL_GPL(pinctrl_generic_pins_function_dt_node_to_map); + +/* + * For platforms that do not define groups or functions in the driver, but + * instead use the devicetree to describe them. This function will, unlike + * pinconf_generic_dt_node_to_map() etc which rely on driver defined groups + * and functions, create them in addition to parsing pinconf properties and + * adding mappings. + * + * It assumes that the upper 16 bits of the pinmux items contain the pin + * and the lower 16 the mux setting. + */ +int pinctrl_generic_pinmux_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + return pinctrl_generic_dt_node_to_map(pctldev, np, maps, num_maps, + &pinctrl_generic_pinmux_dt_subnode_to_map); +}; +EXPORT_SYMBOL_GPL(pinctrl_generic_pinmux_dt_node_to_map); diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index c7f14546de05..1aa6a6dc1209 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -12,7 +12,6 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/property.h> @@ -4334,7 +4333,8 @@ static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { const unsigned int *pins; - unsigned int i, npins, old = 0; + unsigned int i, npins; + unsigned long old = 0; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); diff --git a/drivers/pinctrl/pinctrl-loongson2.c b/drivers/pinctrl/pinctrl-loongson2.c index 4d4fbeadafb7..7d04fa81d2e5 100644 --- a/drivers/pinctrl/pinctrl-loongson2.c +++ b/drivers/pinctrl/pinctrl-loongson2.c @@ -8,7 +8,6 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/platform_device.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index 5e0201768323..9431810ffaff 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -12,7 +12,6 @@ #include <linux/clk.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinconf-generic.h> diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c index acb945a25743..0fa28d697e8c 100644 --- a/drivers/pinctrl/pinctrl-max77620.c +++ b/drivers/pinctrl/pinctrl-max77620.c @@ -10,7 +10,6 @@ */ #include <linux/mfd/max77620.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> @@ -645,9 +644,9 @@ static const struct dev_pm_ops max77620_pinctrl_pm_ops = { }; static const struct platform_device_id max77620_pinctrl_devtype[] = { - { .name = "max77620-pinctrl", }, - { .name = "max20024-pinctrl", }, - {}, + { .name = "max77620-pinctrl" }, + { .name = "max20024-pinctrl" }, + { } }; MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype); diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index b89b3169e8be..cc668f84bf8b 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/device.h> #include <linux/mutex.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/export.h> #include <linux/gpio/driver.h> @@ -560,11 +559,8 @@ static int mcp23s08_irq_setup(struct mcp23s08 *mcp) err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, mcp23s08_irq, irqflags, dev_name(chip->parent), mcp); - if (err != 0) { - dev_err(chip->parent, "unable to request IRQ#%d: %d\n", - mcp->irq, err); + if (err) return err; - } return 0; } diff --git a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c index 94e1add6ddd7..928b66531858 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c +++ b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c @@ -2,7 +2,6 @@ /* MCP23S08 I2C GPIO driver */ #include <linux/i2c.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/regmap.h> @@ -67,9 +66,9 @@ static const struct mcp23s08_info mcp23018_i2c = { }; static const struct i2c_device_id mcp230xx_id[] = { - { "mcp23008", (kernel_ulong_t)&mcp23008_i2c }, - { "mcp23017", (kernel_ulong_t)&mcp23017_i2c }, - { "mcp23018", (kernel_ulong_t)&mcp23018_i2c }, + { .name = "mcp23008", .driver_data = (kernel_ulong_t)&mcp23008_i2c }, + { .name = "mcp23017", .driver_data = (kernel_ulong_t)&mcp23017_i2c }, + { .name = "mcp23018", .driver_data = (kernel_ulong_t)&mcp23018_i2c }, { } }; MODULE_DEVICE_TABLE(i2c, mcp230xx_id); diff --git a/drivers/pinctrl/pinctrl-mcp23s08_spi.c b/drivers/pinctrl/pinctrl-mcp23s08_spi.c index 54f61c8cb1c0..bacebcff67ef 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08_spi.c +++ b/drivers/pinctrl/pinctrl-mcp23s08_spi.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* MCP23S08 SPI GPIO driver */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/property.h> #include <linux/regmap.h> @@ -10,6 +9,7 @@ #include "pinctrl-mcp23s08.h" #define MCP_MAX_DEV_PER_CS 8 +#define MCP23S08_SPI_BASE 0x40 /* * A given spi_device can represent up to eight mcp23sxx chips @@ -143,13 +143,13 @@ static int mcp23s08_probe(struct spi_device *spi) unsigned int addr; int chips; int ret; - u32 v; + u8 v; info = spi_get_device_match_data(spi); - ret = device_property_read_u32(dev, "microchip,spi-present-mask", &v); + ret = device_property_read_u8(dev, "microchip,spi-present-mask", &v); if (ret) { - ret = device_property_read_u32(dev, "mcp,spi-present-mask", &v); + ret = device_property_read_u8(dev, "mcp,spi-present-mask", &v); if (ret) { dev_err(dev, "missing spi-present-mask"); return ret; @@ -173,6 +173,8 @@ static int mcp23s08_probe(struct spi_device *spi) for_each_set_bit(addr, &spi_present_mask, MCP_MAX_DEV_PER_CS) { data->mcp[addr] = &data->chip[--chips]; data->mcp[addr]->irq = spi->irq; + data->mcp[addr]->dev = dev; + data->mcp[addr]->addr = MCP23S08_SPI_BASE | (addr << 1); ret = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, info); if (ret) @@ -184,7 +186,7 @@ static int mcp23s08_probe(struct spi_device *spi) if (!data->mcp[addr]->pinctrl_desc.name) return -ENOMEM; - ret = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), + ret = mcp23s08_probe_one(data->mcp[addr], dev, MCP23S08_SPI_BASE | (addr << 1), info->type, -1); if (ret < 0) return ret; diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 7a6cb5f502b0..aa0f7c809978 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -13,7 +13,6 @@ #include <linux/gpio/driver.h> #include <linux/io.h> #include <linux/mfd/ocelot.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c index fcd9d46de89f..1b285c9ee05a 100644 --- a/drivers/pinctrl/pinctrl-mlxbf3.c +++ b/drivers/pinctrl/pinctrl-mlxbf3.c @@ -6,7 +6,6 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/types.h> diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 0fe0527863b8..58d3cde9f964 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -2317,7 +2317,7 @@ static const struct irq_chip ocelot_irqchip = { static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) { - if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip, handle_level_irq, NULL); if (type & IRQ_TYPE_EDGE_BOTH) diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 0b33b01dbaad..cc5cd2a538c5 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -10,7 +10,6 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/irq.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 2f14c7f9c95a..ba47b6f323cc 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -483,7 +483,7 @@ static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { { .num = 1, .pin = 0, @@ -547,7 +547,7 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { { .num = 0, .pin = 20, @@ -578,7 +578,7 @@ static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { { .num = 2, .pin = 20, @@ -612,7 +612,7 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { { /* gpio1b6_sel */ .num = 1, @@ -721,7 +721,116 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { }, }; -static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { +static const struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { + { + /* gpio1b6_sel */ + .num = 1, + .pin = 14, + .reg = 0x28, + .bit = 12, + .mask = 0xf + }, { + /* gpio1b7_sel */ + .num = 1, + .pin = 15, + .reg = 0x2c, + .bit = 0, + .mask = 0x3 + }, { + /* gpio1c2_sel */ + .num = 1, + .pin = 18, + .reg = 0x30, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c3_sel */ + .num = 1, + .pin = 19, + .reg = 0x30, + .bit = 8, + .mask = 0xf + }, { + /* gpio1c4_sel */ + .num = 1, + .pin = 20, + .reg = 0x30, + .bit = 12, + .mask = 0xf + }, { + /* gpio1c5_sel */ + .num = 1, + .pin = 21, + .reg = 0x34, + .bit = 0, + .mask = 0xf + }, { + /* gpio1c6_sel */ + .num = 1, + .pin = 22, + .reg = 0x34, + .bit = 4, + .mask = 0xf + }, { + /* gpio1c7_sel */ + .num = 1, + .pin = 23, + .reg = 0x34, + .bit = 8, + .mask = 0xf + }, { + /* gpio2a2_sel_plus */ + .num = 2, + .pin = 2, + .reg = 0x608, + .bit = 0, + .mask = 0x7 + }, { + /* gpio2a3_sel_plus */ + .num = 2, + .pin = 3, + .reg = 0x608, + .bit = 4, + .mask = 0x7 + }, { + /* gpio2c0_sel_plus */ + .num = 2, + .pin = 16, + .reg = 0x610, + .bit = 8, + .mask = 0x7 + }, { + /* gpio3b2_sel_plus */ + .num = 3, + .pin = 10, + .reg = 0x610, + .bit = 0, + .mask = 0x7 + }, { + /* gpio3b3_sel_plus */ + .num = 3, + .pin = 11, + .reg = 0x610, + .bit = 4, + .mask = 0x7 + }, { + /* gpio3b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x68, + .bit = 8, + .mask = 0xf + }, { + /* gpio3b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x68, + .bit = 12, + .mask = 0xf + }, +}; + +static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { /* gpio2_b7_sel */ .num = 2, @@ -793,7 +902,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_mux_recalced_data *data; + const struct rockchip_mux_recalced_data *data; int i; for (i = 0; i < ctrl->niomux_recalced; i++) { @@ -811,7 +920,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, *bit = data->bit; } -static struct rockchip_mux_route_data px30_mux_route_data[] = { +static const struct rockchip_mux_route_data px30_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */ RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */ RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */ @@ -862,7 +971,7 @@ static struct rockchip_mux_route_data px30_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */ }; -static struct rockchip_mux_route_data rv1126_mux_route_data[] = { +static const struct rockchip_mux_route_data rv1126_mux_route_data[] = { RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ @@ -959,7 +1068,7 @@ static struct rockchip_mux_route_data rv1126_mux_route_data[] = { RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ }; -static struct rockchip_mux_route_data rk3128_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3128_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ @@ -969,12 +1078,12 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ }; -static struct rockchip_mux_route_data rk3188_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3188_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ }; -static struct rockchip_mux_route_data rk3228_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3228_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ @@ -995,12 +1104,12 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = { RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ }; -static struct rockchip_mux_route_data rk3288_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3288_mux_route_data[] = { RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ }; -static struct rockchip_mux_route_data rk3308_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ @@ -1016,7 +1125,36 @@ static struct rockchip_mux_route_data rk3308_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ }; -static struct rockchip_mux_route_data rk3328_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3308b_mux_route_data[] = { + RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ + RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ + RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ + RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ + RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ + RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ + RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ + RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ + RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ + RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ + RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ + RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ + RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ + RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ + RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ + RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ + RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ + RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ + RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ +}; + +static const struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ @@ -1031,7 +1169,7 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ }; -static struct rockchip_mux_route_data rk3399_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3399_mux_route_data[] = { RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ @@ -1039,7 +1177,7 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = { RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ }; -static struct rockchip_mux_route_data rk3568_mux_route_data[] = { +static const struct rockchip_mux_route_data rk3568_mux_route_data[] = { RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ @@ -1140,7 +1278,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; - struct rockchip_mux_route_data *data; + const struct rockchip_mux_route_data *data; int i; for (i = 0; i < ctrl->niomux_routes; i++) { @@ -1188,6 +1326,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) else regmap = info->regmap_base; + /* Banks with their own IOC block use its regmap for the iomux */ + if (bank->regmap_ioc) + regmap = bank->regmap_ioc; + else if (ctrl->type == RV1106) + return -EINVAL; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12) return 0; @@ -1317,6 +1461,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) else regmap = info->regmap_base; + /* Banks with their own IOC block use its regmap for the iomux */ + if (bank->regmap_ioc) + regmap = bank->regmap_ioc; + else if (ctrl->type == RV1106) + return -EINVAL; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12) return 0; @@ -1725,6 +1875,78 @@ static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RV1106_DRV_BITS_PER_PIN 8 +#define RV1106_DRV_PINS_PER_REG 2 +#define RV1106_PULL_BITS_PER_PIN 2 +#define RV1106_PULL_PINS_PER_REG 8 +#define RV1106_SMT_BITS_PER_PIN 1 +#define RV1106_SMT_PINS_PER_REG 8 + +/* + * Each bank has its own IOC block, referenced by the rockchip,grf + * phandle of the bank node. The offsets below are relative to the + * bank's own block. + */ +static const int rv1106_drv_offsets[] = { 0x10, 0x80, 0xc0, 0x100, 0x20 }; +static const int rv1106_pull_offsets[] = { 0x38, 0x1c0, 0x1d0, 0x1e0, 0x70 }; +static const int rv1106_smt_offsets[] = { 0x40, 0x280, 0x290, 0x2a0, 0xa0 }; + +static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >= ARRAY_SIZE(rv1106_drv_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + /* Only pins 0-6 of GPIO0 have drive-strength registers */ + if (bank->bank_num == 0 && pin_num > 6) + return -ENOTSUPP; + + *regmap = bank->regmap_ioc; + *reg = rv1106_drv_offsets[bank->bank_num]; + *reg += ((pin_num / RV1106_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_DRV_PINS_PER_REG; + *bit *= RV1106_DRV_BITS_PER_PIN; + + return 0; +} + +static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >= ARRAY_SIZE(rv1106_pull_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + *regmap = bank->regmap_ioc; + *reg = rv1106_pull_offsets[bank->bank_num]; + *reg += ((pin_num / RV1106_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_PULL_PINS_PER_REG; + *bit *= RV1106_PULL_BITS_PER_PIN; + + return 0; +} + +static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >= ARRAY_SIZE(rv1106_smt_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + *regmap = bank->regmap_ioc; + *reg = rv1106_smt_offsets[bank->bank_num]; + *reg += ((pin_num / RV1106_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RV1106_SMT_PINS_PER_REG; + *bit *= RV1106_SMT_BITS_PER_PIN; + + return 0; +} + #define RV1108_PULL_PMU_OFFSET 0x10 #define RV1108_PULL_OFFSET 0x110 #define RV1108_PULL_PINS_PER_REG 8 @@ -3212,7 +3434,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, u8 bit; int drv_type = bank->drv[pin_num / 8].drv_type; - if (ctrl->type == RV1103B && pin_num >= 12) + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) drv_type = DRV_TYPE_IO_LEVEL_2_BIT; ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); @@ -3267,6 +3489,25 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_1V8_ONLY: rmask_bits = RK3288_DRV_BITS_PER_PIN; break; + case DRV_TYPE_IO_LEVEL_2_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + + return data & 0x3; + case DRV_TYPE_IO_LEVEL_8_BIT: + ret = regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>= bit; + data &= (1 << 8) - 1; + + ret = hweight8(data); + if (ret > 0) + return ret - 1; + else + return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; @@ -3310,6 +3551,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, ret = strength; goto config; } else if (ctrl->type == RV1103B || + ctrl->type == RV1106 || ctrl->type == RK3506 || ctrl->type == RK3528 || ctrl->type == RK3562 || @@ -3390,25 +3632,6 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_1V8_ONLY: rmask_bits = RK3288_DRV_BITS_PER_PIN; break; - case DRV_TYPE_IO_LEVEL_2_BIT: - ret = regmap_read(regmap, reg, &data); - if (ret) - return ret; - data >>= bit; - - return data & 0x3; - case DRV_TYPE_IO_LEVEL_8_BIT: - ret = regmap_read(regmap, reg, &data); - if (ret) - return ret; - data >>= bit; - data &= (1 << 8) - 1; - - ret = hweight8(data); - if (ret > 0) - return ret - 1; - else - return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; @@ -3482,10 +3705,12 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) : PIN_CONFIG_BIAS_DISABLE; case PX30: case RV1103B: + case RV1106: case RV1108: case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -3547,11 +3772,13 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, break; case PX30: case RV1103B: + case RV1106: case RV1108: case RV1126: case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -3843,11 +4070,13 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, return pull ? false : true; case PX30: case RV1103B: + case RV1106: case RV1108: case RV1126: case RK3188: case RK3288: case RK3308: + case RK3308B: case RK3328: case RK3368: case RK3399: @@ -4296,6 +4525,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( pmu_offs = ctrl->pmu_mux_offset; drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; + + /* + * This function mutates the static per-SoC data. Most of it is + * idempotent: recalculated iomux and drv offsets anchor at the + * values calculated by a previous run. The pin count is not, so + * reset it here; otherwise it accumulates when the probe runs + * again after a probe deferral, shifting every bank's pin_base. + */ + ctrl->nr_pins = 0; + bank = ctrl->pin_banks; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0; @@ -4370,7 +4609,18 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( bank_pins += 8; } + } + + return ctrl; +} +static void iomux_recalced_routes_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int i, j; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { /* calculate the per-bank recalced_mask */ for (j = 0; j < ctrl->niomux_recalced; j++) { int pin = 0; @@ -4391,8 +4641,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( } } } - - return ctrl; } #define RK3288_GRF_GPIO6C_IOMUX 0x64 @@ -4443,6 +4691,76 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, rockchip_pinctrl_resume); +#define RK3308B_GRF_SOC_CON13 0x608 +#define RK3308B_GRF_SOC_CON15 0x610 + +/* RK3308B_GRF_SOC_CON13 */ +#define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) +#define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* RK3308B_GRF_SOC_CON15 */ +#define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) +#define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* + * RK3308B has 3-bit gpio##_sel_plus iomuxes over some 2-bit old ones. + * Enable them by setting the gpio##_sel_src_ctrl registers. + */ +static int rk3308b_soc_sel_src_init(struct rockchip_pinctrl *info) +{ + int ret; + + ret = regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON13, + RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | + RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); + if (ret) + return ret; + + return regmap_write(info->regmap_base, RK3308B_GRF_SOC_CON15, + RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | + RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); +} + +#define RK3308_GRF_CHIP_ID 0x800 + +static int rk3308_soc_data_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + unsigned int chip_id; + int ret; + + ret = regmap_read(info->regmap_base, RK3308_GRF_CHIP_ID, &chip_id); + if (ret) + return ret; + + switch (chip_id) { + case 0xcea: + /* Original RK3308, no changes needed */ + break; + case 0x3308: + case 0x3308c: + ctrl->type = RK3308B; + ctrl->iomux_recalced = rk3308b_mux_recalced_data; + ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); + ctrl->iomux_routes = rk3308b_mux_route_data; + ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); + + ret = rk3308b_soc_sel_src_init(info); + if (ret) + return ret; + break; + default: + return dev_err_probe(info->dev, -EINVAL, + "Unknown RK3308 chip_id: 0x%x\n", chip_id); + } + + return 0; +} + static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; @@ -4452,6 +4770,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) struct resource *res; void __iomem *base; int ret; + int i; if (!dev->of_node) return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); @@ -4505,6 +4824,52 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) /* try to find the optional reference to the ioc1 syscon */ info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); + if (ctrl->type == RK3308) { + ret = rk3308_soc_data_init(info); + if (ret) + return ret; + } + + iomux_recalced_routes_init(info); + + /* + * On SoCs where each GPIO bank has its own IOC block, the bank nodes + * carry a rockchip,grf phandle pointing at it. The bank number comes + * from the gpio alias, as used by the gpio driver, falling back to + * the node position for devicetrees without aliases. The fallback is + * wrong when an SoC variant omits a bank, so aliases are needed + * there. + */ + i = 0; + for_each_child_of_node_scoped(np, child) { + struct rockchip_pin_bank *bank = NULL; + int id, j; + + if (!of_match_node(rockchip_bank_match, child)) + continue; + + id = of_alias_get_id(child, "gpio"); + if (id < 0) + id = i; + i++; + + for (j = 0; j < ctrl->nr_banks; j++) { + if (ctrl->pin_banks[j].bank_num == id) { + bank = &ctrl->pin_banks[j]; + break; + } + } + if (!bank) + continue; + + bank->regmap_ioc = syscon_regmap_lookup_by_phandle_optional( + child, "rockchip,grf"); + if (IS_ERR(bank->regmap_ioc)) + return dev_err_probe(dev, PTR_ERR(bank->regmap_ioc), + "%pOFn: failed to look up bank ioc\n", + child); + } + ret = rockchip_pinctrl_register(pdev, info); if (ret) return ret; @@ -4623,6 +4988,69 @@ static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = { .schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit, }; +static struct rockchip_pin_bank rv1106_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(4, 24, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0, -1, -1, -1, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), +}; + +static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = { + .pin_banks = rv1106_pin_banks, + .nr_banks = ARRAY_SIZE(rv1106_pin_banks), + .label = "RV1106-GPIO", + .type = RV1106, + .pull_calc_reg = rv1106_calc_pull_reg_and_bit, + .drv_calc_reg = rv1106_calc_drv_reg_and_bit, + .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -5261,6 +5689,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &px30_pin_ctrl }, { .compatible = "rockchip,rv1103b-pinctrl", .data = &rv1103b_pin_ctrl }, + { .compatible = "rockchip,rv1106-pinctrl", + .data = &rv1106_pin_ctrl }, { .compatible = "rockchip,rv1108-pinctrl", .data = &rv1108_pin_ctrl }, { .compatible = "rockchip,rv1126-pinctrl", @@ -5303,6 +5733,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &rk3588_pin_ctrl }, {}, }; +MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); static struct platform_driver rockchip_pinctrl_driver = { .probe = rockchip_pinctrl_probe, @@ -5329,4 +5760,3 @@ module_exit(rockchip_pinctrl_drv_unregister); MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:pinctrl-rockchip"); -MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index bb0e803e3b8a..950097699643 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -186,6 +186,7 @@ enum rockchip_pinctrl_type { PX30, RV1103B, + RV1106, RV1108, RV1126, RK2928, @@ -194,6 +195,7 @@ enum rockchip_pinctrl_type { RK3188, RK3288, RK3308, + RK3308B, RK3328, RK3368, RK3399, @@ -295,6 +297,8 @@ struct rockchip_drv { * @dev: the pinctrl device bind to the bank * @reg_base: register base of the gpio bank * @regmap_pull: optional separate register for additional pull settings + * @regmap_ioc: optional per-bank IO control regmap, for SoCs where each + * bank has its own IOC block * @clk: clock of the gpio bank * @db_clk: clock of the gpio debounce * @irq: interrupt of the gpio bank @@ -323,6 +327,7 @@ struct rockchip_pin_bank { struct device *dev; void __iomem *reg_base; struct regmap *regmap_pull; + struct regmap *regmap_ioc; struct clk *clk; struct clk *db_clk; int irq; @@ -400,9 +405,9 @@ struct rockchip_pin_ctrl { int pmu_mux_offset; int grf_drv_offset; int pmu_drv_offset; - struct rockchip_mux_recalced_data *iomux_recalced; + const struct rockchip_mux_recalced_data *iomux_recalced; u32 niomux_recalced; - struct rockchip_mux_route_data *iomux_routes; + const struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; int (*pull_calc_reg)(struct rockchip_pin_bank *bank, diff --git a/drivers/pinctrl/pinctrl-rp1.c b/drivers/pinctrl/pinctrl-rp1.c index fc4ed68ea5ac..dd0e85c2ca33 100644 --- a/drivers/pinctrl/pinctrl-rp1.c +++ b/drivers/pinctrl/pinctrl-rp1.c @@ -1085,7 +1085,7 @@ static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "function %s (%s) in %s; irq %d (%s)", rp1_func_names[fsel].name, rp1_func_names[func].name, - value ? "hi" : "lo", + str_hi_lo(value), irq, irq_type_names[pin->irq_type]); } diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index f22be6b7b82a..1bb36ca477b7 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -10,7 +10,6 @@ #include <linux/err.h> #include <linux/errno.h> #include <linux/module.h> -#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/scmi_protocol.h> #include <linux/slab.h> diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 7e022a46ee42..e0eb7240a985 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -619,8 +619,9 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned group, unsigned long *config) { + unsigned long old = 0; const unsigned *pins; - unsigned npins, old = 0; + unsigned npins; int i, ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); @@ -1627,7 +1628,8 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs, &pcs_irqdomain_ops, pcs_soc); if (!pcs->domain) { - irq_set_chained_handler(pcs_soc->irq, NULL); + pcs_irq_free(pcs); + pcs_soc->irq = -1; return -EINVAL; } diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 03ee13844b50..935cace7f645 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -727,10 +727,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) stmfx_pinctrl_irq_thread_fn, IRQF_ONESHOT, dev_name(pctl->dev), pctl); - if (ret) { - dev_err(pctl->dev, "cannot request irq%d\n", irq); + if (ret) return ret; - } dev_info(pctl->dev, "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 1d6760ffe809..04a0e6269e5b 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -525,7 +525,7 @@ static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) struct sx150x_pinctrl *pctl = gpiochip_get_data(gc); unsigned int n, val = 0; - if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) + if (flow_type & IRQ_TYPE_LEVEL_MASK) return -EINVAL; n = irqd_to_hwirq(d); @@ -550,6 +550,9 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) if (err < 0) return IRQ_NONE; + if (!val) + return IRQ_NONE; + err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); if (err < 0) return IRQ_NONE; @@ -839,17 +842,18 @@ static const struct pinconf_ops sx150x_pinconf_ops = { }; static const struct i2c_device_id sx150x_id[] = { - {"sx1501q", (kernel_ulong_t) &sx1501q_device_data }, - {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, - {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, - {"sx1504q", (kernel_ulong_t) &sx1504q_device_data }, - {"sx1505q", (kernel_ulong_t) &sx1505q_device_data }, - {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, - {"sx1507q", (kernel_ulong_t) &sx1507q_device_data }, - {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, - {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, - {} + { .name = "sx1501q", .driver_data = (kernel_ulong_t)&sx1501q_device_data }, + { .name = "sx1502q", .driver_data = (kernel_ulong_t)&sx1502q_device_data }, + { .name = "sx1503q", .driver_data = (kernel_ulong_t)&sx1503q_device_data }, + { .name = "sx1504q", .driver_data = (kernel_ulong_t)&sx1504q_device_data }, + { .name = "sx1505q", .driver_data = (kernel_ulong_t)&sx1505q_device_data }, + { .name = "sx1506q", .driver_data = (kernel_ulong_t)&sx1506q_device_data }, + { .name = "sx1507q", .driver_data = (kernel_ulong_t)&sx1507q_device_data }, + { .name = "sx1508q", .driver_data = (kernel_ulong_t)&sx1508q_device_data }, + { .name = "sx1509q", .driver_data = (kernel_ulong_t)&sx1509q_device_data }, + { } }; +MODULE_DEVICE_TABLE(i2c, sx150x_id); static const struct of_device_id sx150x_of_match[] = { { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data }, @@ -1122,6 +1126,7 @@ static int sx150x_probe(struct i2c_client *client) I2C_FUNC_SMBUS_WRITE_WORD_DATA; struct device *dev = &client->dev; struct sx150x_pinctrl *pctl; + u32 irq_type; int ret; if (!i2c_check_functionality(client->adapter, i2c_funcs)) @@ -1221,10 +1226,24 @@ static int sx150x_probe(struct i2c_client *client) girq->handler = handle_bad_irq; girq->threaded = true; + irq_type = irq_get_trigger_type(client->irq); + switch (irq_type) { + case IRQF_TRIGGER_FALLING: + case IRQF_TRIGGER_LOW: + break; + case IRQF_TRIGGER_NONE: + irq_type = IRQF_TRIGGER_FALLING; + break; + default: + return dev_err_probe(dev, -EINVAL, + "unsupported irq trigger type %x\n", + irq_type); + } + ret = devm_request_threaded_irq(dev, client->irq, NULL, sx150x_irq_thread_fn, IRQF_ONESHOT | IRQF_SHARED | - IRQF_TRIGGER_FALLING, + irq_type, client->name, pctl); if (ret < 0) return ret; diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 3f581404a9b9..b7cbd69dd877 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -479,7 +479,7 @@ struct tb10x_port { */ struct tb10x_pinctrl { struct pinctrl_dev *pctl; - void *base; + void __iomem *base; const struct tb10x_pinfuncgrp *pingroups; unsigned int pinfuncgrpcnt; unsigned int pinfuncnt; diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c index 4d5a99483dee..50a5889df7c4 100644 --- a/drivers/pinctrl/pinctrl-th1520.c +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -11,7 +11,6 @@ #include <linux/clk.h> #include <linux/device.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-tps6594.c index 6726853110d1..937fc9cb54b7 100644 --- a/drivers/pinctrl/pinctrl-tps6594.c +++ b/drivers/pinctrl/pinctrl-tps6594.c @@ -10,7 +10,6 @@ #include <linux/module.h> #include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> -#include <linux/mod_devicetable.h> #include <linux/mfd/tps6594.h> @@ -347,6 +346,7 @@ static struct tps6594_pinctrl tps6594_template_pinctrl = { }; static int tps6594_gpio_regmap_xlate(struct gpio_regmap *gpio, + enum gpio_regmap_operation op, unsigned int base, unsigned int offset, unsigned int *reg, unsigned int *mask) { @@ -562,8 +562,8 @@ static int tps6594_pinctrl_probe(struct platform_device *pdev) } static const struct platform_device_id tps6594_pinctrl_id_table[] = { - { "tps6594-pinctrl", }, - {} + { .name = "tps6594-pinctrl" }, + { } }; MODULE_DEVICE_TABLE(platform, tps6594_pinctrl_id_table); diff --git a/drivers/pinctrl/pinctrl-upboard.c b/drivers/pinctrl/pinctrl-upboard.c index f8c8b9d84990..de1920a3387d 100644 --- a/drivers/pinctrl/pinctrl-upboard.c +++ b/drivers/pinctrl/pinctrl-upboard.c @@ -912,6 +912,19 @@ static const struct upboard_pinctrl_map upboard_pinctrl_map_apl01 = { .nmaps = ARRAY_SIZE(pinctrl_map_apl01), }; +static const struct pinctrl_map pinctrl_map_adl[] = { + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c0_grp", "i2c0"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "i2c1_grp", "i2c1"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "pwm0_grp", "pwm0"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "uart1_grp", "uart1"), + PIN_MAP_MUX_GROUP_DEFAULT("upboard-pinctrl", "INTC1055:00", "ssp2_grp", "ssp2"), +}; + +static const struct upboard_pinctrl_map upboard_pinctrl_map_adl = { + .maps = &pinctrl_map_adl[0], + .nmaps = ARRAY_SIZE(pinctrl_map_adl), +}; + static const struct dmi_system_id dmi_platform_info[] = { { /* UP Squared */ @@ -921,6 +934,14 @@ static const struct dmi_system_id dmi_platform_info[] = { }, .driver_data = (void *)&upboard_pinctrl_map_apl01, }, + { + /* UP Xtreme i12 */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPX-ADLP01"), + }, + .driver_data = (void *)&upboard_pinctrl_map_adl, + }, { } }; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 3a8dd184ba3d..c705bc182266 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -517,6 +517,7 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; + const struct pinmux_ops *ops = pctldev->desc->pmxops; int ret = 0; const unsigned int *pins = NULL; unsigned int num_pins = 0; @@ -563,6 +564,10 @@ void pinmux_disable_setting(const struct pinctrl_setting *setting) pins[i], desc->name, gname); } } + + if (ops->release_mux) + ops->release_mux(pctldev, setting->data.mux.func, + setting->data.mux.group); } #ifdef CONFIG_DEBUG_FS diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 80af372a1147..18db350222b9 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -6,6 +6,7 @@ config PINCTRL_MSM depends on GPIOLIB # OF for pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF depends on OF + default ARCH_QCOM select QCOM_SCM select PINMUX select GENERIC_PINMUX_FUNCTIONS @@ -49,11 +50,12 @@ config PINCTRL_QCOM_SSBI_PMIC devices are pm8058 and pm8921. config PINCTRL_LPASS_LPI - tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver" + tristate "Qualcomm LPASS LPI pin controller driver" select PINMUX select PINCONF select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS + depends on PM_CLK depends on GPIOLIB help This is the pinctrl, pinmux, pinconf and gpiolib driver for the @@ -61,7 +63,7 @@ config PINCTRL_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. config PINCTRL_MILOS_LPASS_LPI - tristate "Qualcomm Technologies Inc Milos LPASS LPI pin controller driver" + tristate "Qualcomm Milos LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -71,7 +73,7 @@ config PINCTRL_MILOS_LPASS_LPI platform. config PINCTRL_SC7280_LPASS_LPI - tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin controller driver" + tristate "Qualcomm SC7280 and SM8350 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -81,7 +83,7 @@ config PINCTRL_SC7280_LPASS_LPI and SM8350 platforms. config PINCTRL_SDM660_LPASS_LPI - tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver" + tristate "Qualcomm SDM660 LPASS LPI pin controller driver" depends on GPIOLIB depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI @@ -91,7 +93,7 @@ config PINCTRL_SDM660_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform. config PINCTRL_SM4250_LPASS_LPI - tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver" + tristate "Qualcomm SM4250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -100,7 +102,7 @@ config PINCTRL_SM4250_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform. config PINCTRL_SDM670_LPASS_LPI - tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver" + tristate "Qualcomm SDM670 LPASS LPI pin controller driver" depends on GPIOLIB depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI @@ -110,7 +112,7 @@ config PINCTRL_SDM670_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform. config PINCTRL_SM6115_LPASS_LPI - tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" + tristate "Qualcomm SM6115 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -118,8 +120,17 @@ config PINCTRL_SM6115_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform. +config PINCTRL_SM6350_LPASS_LPI + tristate "Qualcomm SM6350 LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6350 platform. + config PINCTRL_SM8250_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver" + tristate "Qualcomm SM8250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -128,7 +139,7 @@ config PINCTRL_SM8250_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform. config PINCTRL_SM8450_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver" + tristate "Qualcomm SM8450 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -137,7 +148,7 @@ config PINCTRL_SM8450_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform. config PINCTRL_SC8280XP_LPASS_LPI - tristate "Qualcomm Technologies Inc SC8280XP LPASS LPI pin controller driver" + tristate "Qualcomm SC8280XP LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -146,7 +157,7 @@ config PINCTRL_SC8280XP_LPASS_LPI (Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform. config PINCTRL_SM8550_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver" + tristate "Qualcomm SM8550 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help @@ -156,7 +167,7 @@ config PINCTRL_SM8550_LPASS_LPI platform. config PINCTRL_SM8650_LPASS_LPI - tristate "Qualcomm Technologies Inc SM8650 LPASS LPI pin controller driver" + tristate "Qualcomm SM8650 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST depends on PINCTRL_LPASS_LPI help diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 836cdeca1006..42875457b5fc 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -4,6 +4,7 @@ if PINCTRL_MSM config PINCTRL_APQ8064 tristate "Qualcomm APQ8064 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8064 platform. @@ -11,13 +12,15 @@ config PINCTRL_APQ8064 config PINCTRL_APQ8084 tristate "Qualcomm APQ8084 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8084 platform. config PINCTRL_ELIZA - tristate "Qualcomm Technologies Inc Eliza pin controller driver" + tristate "Qualcomm Eliza pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) @@ -26,8 +29,9 @@ config PINCTRL_ELIZA If unsure, say N. config PINCTRL_GLYMUR - tristate "Qualcomm Technologies Inc Glymur pin controller driver" + tristate "Qualcomm Glymur pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) @@ -36,8 +40,9 @@ config PINCTRL_GLYMUR If unsure, say N. config PINCTRL_HAWI - tristate "Qualcomm Technologies Inc Hawi pin controller driver" + tristate "Qualcomm Hawi pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) @@ -48,13 +53,15 @@ config PINCTRL_HAWI config PINCTRL_IPQ4019 tristate "Qualcomm IPQ4019 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ4019 platform. config PINCTRL_IPQ5018 - tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver" + tristate "Qualcomm IPQ5018 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -64,29 +71,33 @@ config PINCTRL_IPQ5018 config PINCTRL_IPQ8064 tristate "Qualcomm IPQ8064 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. config PINCTRL_IPQ5210 - tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver" + tristate "Qualcomm IPQ5210 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc IPQ5210 platform. config PINCTRL_IPQ5332 - tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" + tristate "Qualcomm IPQ5332 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc IPQ5332 platform. config PINCTRL_IPQ5424 - tristate "Qualcomm Technologies, Inc. IPQ5424 pin controller driver" + tristate "Qualcomm IPQ5424 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -94,8 +105,9 @@ config PINCTRL_IPQ5424 IPQ5424. config PINCTRL_IPQ8074 - tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" + tristate "Qualcomm IPQ8074 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -103,8 +115,9 @@ config PINCTRL_IPQ8074 IPQ8074. config PINCTRL_IPQ6018 - tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver" + tristate "Qualcomm IPQ6018 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the @@ -112,25 +125,48 @@ config PINCTRL_IPQ6018 IPQ6018. config PINCTRL_IPQ9574 - tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver" + tristate "Qualcomm IPQ9574 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc. TLMM block found on the Qualcomm Technologies Inc. IPQ9574 platform. Select this for IPQ9574. +config PINCTRL_IPQ9650 + tristate "Qualcomm IPQ9650 pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ9650 platform. Select this for + IPQ9650. + config PINCTRL_KAANAPALI - tristate "Qualcomm Technologies Inc Kaanapali pin controller driver" + tristate "Qualcomm Kaanapali pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc Kaanapali platform. +config PINCTRL_MAILI + tristate "Qualcomm Technologies Inc Maili pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Maili platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_MSM8226 tristate "Qualcomm 8226 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm @@ -139,6 +175,7 @@ config PINCTRL_MSM8226 config PINCTRL_MSM8660 tristate "Qualcomm 8660 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8660 platform. @@ -146,12 +183,14 @@ config PINCTRL_MSM8660 config PINCTRL_MSM8960 tristate "Qualcomm 8960 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8960 platform. config PINCTRL_MDM9607 tristate "Qualcomm 9607 pin controller driver" + default ARCH_QCOM if ARM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 9607 platform. @@ -159,6 +198,7 @@ config PINCTRL_MDM9607 config PINCTRL_MDM9615 tristate "Qualcomm 9615 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 9615 platform. @@ -166,6 +206,7 @@ config PINCTRL_MDM9615 config PINCTRL_MSM8X74 tristate "Qualcomm 8x74 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8974 platform. @@ -173,12 +214,14 @@ config PINCTRL_MSM8X74 config PINCTRL_MSM8909 tristate "Qualcomm 8909 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8909 platform. config PINCTRL_MSM8916 tristate "Qualcomm 8916 pin controller driver" + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. @@ -192,6 +235,7 @@ config PINCTRL_MSM8917 config PINCTRL_MSM8953 tristate "Qualcomm 8953 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8953 platform. @@ -201,6 +245,7 @@ config PINCTRL_MSM8953 config PINCTRL_MSM8976 tristate "Qualcomm 8976 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm MSM8976 platform. @@ -210,6 +255,7 @@ config PINCTRL_MSM8976 config PINCTRL_MSM8994 tristate "Qualcomm 8994 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm 8994 platform. The @@ -218,6 +264,7 @@ config PINCTRL_MSM8994 config PINCTRL_MSM8996 tristate "Qualcomm MSM8996 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8996 platform. @@ -225,13 +272,23 @@ config PINCTRL_MSM8996 config PINCTRL_MSM8998 tristate "Qualcomm MSM8998 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8998 platform. +config PINCTRL_NORD + tristate "Qualcomm Nord pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux and pinconf driver for the Qualcomm + TLMM block found on the Qualcomm NORD platforms. + config PINCTRL_QCM2290 tristate "Qualcomm QCM2290 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found in the Qualcomm QCM2290 platform. @@ -239,48 +296,54 @@ config PINCTRL_QCM2290 config PINCTRL_QCS404 tristate "Qualcomm QCS404 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found in the Qualcomm QCS404 platform. config PINCTRL_QCS615 - tristate "Qualcomm Technologies QCS615 pin controller driver" + tristate "Qualcomm QCS615 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the TLMM block found on the Qualcomm QCS615 platform. config PINCTRL_QCS8300 - tristate "Qualcomm Technologies QCS8300 pin controller driver" + tristate "Qualcomm QCS8300 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux and pinconf driver for the Qualcomm TLMM block found on the Qualcomm QCS8300 platform. config PINCTRL_QDF2XXX - tristate "Qualcomm Technologies QDF2xxx pin controller driver" + tristate "Qualcomm QDF2xxx pin controller driver" depends on ACPI + default ARCH_QCOM if ARM64 help This is the GPIO driver for the TLMM block found on the Qualcomm Technologies QDF2xxx SOCs. config PINCTRL_QDU1000 - tristate "Qualcomm Technologies Inc QDU1000/QRU1000 pin controller driver" + tristate "Qualcomm QDU1000/QRU1000 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf, and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc QDU1000 and QRU1000 platforms. config PINCTRL_SA8775P - tristate "Qualcomm Technologies Inc SA8775P pin controller driver" + tristate "Qualcomm SA8775P pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux and pinconf driver for the Qualcomm TLMM block found on the Qualcomm SA8775P platforms. config PINCTRL_SAR2130P - tristate "Qualcomm Technologies Inc SAR2130P pin controller driver" + tristate "Qualcomm SAR2130P pin controller driver" depends on ARM64 || COMPILE_TEST help This is the pinctrl, pinmux, pinconf and gpiolib driver for the @@ -288,202 +351,238 @@ config PINCTRL_SAR2130P Technologies Inc SAR2130P platform. config PINCTRL_SC7180 - tristate "Qualcomm Technologies Inc SC7180 pin controller driver" + tristate "Qualcomm SC7180 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC7180 platform. config PINCTRL_SC7280 - tristate "Qualcomm Technologies Inc SC7280 pin controller driver" + tristate "Qualcomm SC7280 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC7280 platform. config PINCTRL_SC8180X - tristate "Qualcomm Technologies Inc SC8180x pin controller driver" + tristate "Qualcomm SC8180x pin controller driver" depends on (OF || ACPI) depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC8180x platform. config PINCTRL_SC8280XP - tristate "Qualcomm Technologies Inc SC8280xp pin controller driver" + tristate "Qualcomm SC8280xp pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC8280xp platform. config PINCTRL_SDM660 - tristate "Qualcomm Technologies Inc SDM660 pin controller driver" + tristate "Qualcomm SDM660 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM660 platform. config PINCTRL_SDM670 - tristate "Qualcomm Technologies Inc SDM670 pin controller driver" + tristate "Qualcomm SDM670 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM670 platform. config PINCTRL_SDM845 - tristate "Qualcomm Technologies Inc SDM845 pin controller driver" + tristate "Qualcomm SDM845 pin controller driver" depends on (OF || ACPI) depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM845 platform. config PINCTRL_SDX55 - tristate "Qualcomm Technologies Inc SDX55 pin controller driver" + tristate "Qualcomm SDX55 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX55 platform. config PINCTRL_SDX65 - tristate "Qualcomm Technologies Inc SDX65 pin controller driver" + tristate "Qualcomm SDX65 pin controller driver" depends on ARM || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX65 platform. config PINCTRL_SDX75 - tristate "Qualcomm Technologies Inc SDX75 pin controller driver" + tristate "Qualcomm SDX75 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX75 platform. +config PINCTRL_SHIKRA + tristate "Qualcomm Shikra pin controller driver" + depends on ARM64 || COMPILE_TEST + default ARCH_QCOM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) + found on the Qualcomm Technologies Inc Shikra platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_SM4450 - tristate "Qualcomm Technologies Inc SM4450 pin controller driver" + tristate "Qualcomm SM4450 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM4450 platform. config PINCTRL_SM6115 - tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver" + tristate "Qualcomm SM6115,SM4250 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6115 and SM4250 platforms. config PINCTRL_SM6125 - tristate "Qualcomm Technologies Inc SM6125 pin controller driver" + tristate "Qualcomm SM6125 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6125 platform. config PINCTRL_SM6350 - tristate "Qualcomm Technologies Inc SM6350 pin controller driver" + tristate "Qualcomm SM6350 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6350 platform. config PINCTRL_SM6375 - tristate "Qualcomm Technologies Inc SM6375 pin controller driver" + tristate "Qualcomm SM6375 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6375 platform. config PINCTRL_SM7150 - tristate "Qualcomm Technologies Inc SM7150 pin controller driver" + tristate "Qualcomm SM7150 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM7150 platform. config PINCTRL_MILOS - tristate "Qualcomm Technologies Inc Milos pin controller driver" + tristate "Qualcomm Milos pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc Milos platform. config PINCTRL_SM8150 - tristate "Qualcomm Technologies Inc SM8150 pin controller driver" + tristate "Qualcomm SM8150 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8150 platform. config PINCTRL_SM8250 - tristate "Qualcomm Technologies Inc SM8250 pin controller driver" + tristate "Qualcomm SM8250 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8250 platform. config PINCTRL_SM8350 - tristate "Qualcomm Technologies Inc SM8350 pin controller driver" + tristate "Qualcomm SM8350 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8350 platform. config PINCTRL_SM8450 - tristate "Qualcomm Technologies Inc SM8450 pin controller driver" + tristate "Qualcomm SM8450 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8450 platform. config PINCTRL_SM8550 - tristate "Qualcomm Technologies Inc SM8550 pin controller driver" + tristate "Qualcomm SM8550 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8550 platform. config PINCTRL_SM8650 - tristate "Qualcomm Technologies Inc SM8650 pin controller driver" + tristate "Qualcomm SM8650 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8650 platform. config PINCTRL_SM8750 - tristate "Qualcomm Technologies Inc SM8750 pin controller driver" + tristate "Qualcomm SM8750 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8750 platform. config PINCTRL_X1E80100 - tristate "Qualcomm Technologies Inc X1E80100 pin controller driver" + tristate "Qualcomm X1E80100 pin controller driver" depends on ARM64 || COMPILE_TEST + default ARCH_QCOM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 84bda3ada874..43ecd246afe8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -15,7 +15,9 @@ obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o +obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o +obj-$(CONFIG_PINCTRL_MAILI) += pinctrl-maili.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o @@ -37,6 +39,7 @@ obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o +obj-$(CONFIG_PINCTRL_NORD) += pinctrl-nord.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o @@ -57,12 +60,14 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o +obj-$(CONFIG_PINCTRL_SHIKRA) += pinctrl-shikra.o obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o +obj-$(CONFIG_PINCTRL_SM6350_LPASS_LPI) += pinctrl-sm6350-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index 3654913f1ae5..a47f3d4f1ea5 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -622,6 +622,7 @@ static const struct of_device_id apq8064_pinctrl_of_match[] = { { .compatible = "qcom,apq8064-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); static struct platform_driver apq8064_pinctrl_driver = { .driver = { @@ -646,4 +647,3 @@ module_exit(apq8064_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index 9fdbe6743512..e3c1f86aba7d 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -1198,6 +1198,7 @@ static const struct of_device_id apq8084_pinctrl_of_match[] = { { .compatible = "qcom,apq8084-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match); static struct platform_driver apq8084_pinctrl_driver = { .driver = { @@ -1221,4 +1222,3 @@ module_exit(apq8084_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c index c1f756cbcdeb..58545e14710e 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -54,30 +54,6 @@ .intr_detection_width = 2, \ } -#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .grp = PINCTRL_PINGROUP(#pg_name, \ - pg_name##_pins, \ - ARRAY_SIZE(pg_name##_pins)), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - #define UFS_RESET(pg_name, ctl, io) \ { \ .grp = PINCTRL_PINGROUP(#pg_name, \ @@ -563,15 +539,32 @@ enum eliza_functions { msm_mux_qup1_se0, msm_mux_qup1_se1, msm_mux_qup1_se2, + msm_mux_qup1_se2_l2_mira, + msm_mux_qup1_se2_l2_mirb, + msm_mux_qup1_se2_l3_mira, + msm_mux_qup1_se2_l3_mirb, msm_mux_qup1_se3, - msm_mux_qup1_se4, + msm_mux_qup1_se4_01, + msm_mux_qup1_se4_23, msm_mux_qup1_se5, msm_mux_qup1_se6, + msm_mux_qup1_se6_l1_mira, + msm_mux_qup1_se6_l1_mirb, + msm_mux_qup1_se6_l3_mira, + msm_mux_qup1_se6_l3_mirb, msm_mux_qup1_se7, + msm_mux_qup1_se7_l0_mira, + msm_mux_qup1_se7_l0_mirb, + msm_mux_qup1_se7_l1_mira, + msm_mux_qup1_se7_l1_mirb, msm_mux_qup2_se0, msm_mux_qup2_se1, msm_mux_qup2_se2, msm_mux_qup2_se3, + msm_mux_qup2_se3_l0_mira, + msm_mux_qup2_se3_l0_mirb, + msm_mux_qup2_se3_l1_mira, + msm_mux_qup2_se3_l1_mirb, msm_mux_qup2_se4, msm_mux_qup2_se5, msm_mux_qup2_se6, @@ -978,15 +971,35 @@ static const char *const qup1_se1_groups[] = { }; static const char *const qup1_se2_groups[] = { - "gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gpio42", "gpio30", + "gpio52", "gpio53", "gpio40", "gpio42", "gpio30", +}; + +static const char *const qup1_se2_l2_mira_groups[] = { + "gpio54", +}; + +static const char *const qup1_se2_l2_mirb_groups[] = { + "gpio52", +}; + +static const char *const qup1_se2_l3_mira_groups[] = { + "gpio55", +}; + +static const char *const qup1_se2_l3_mirb_groups[] = { + "gpio53", }; static const char *const qup1_se3_groups[] = { "gpio44", "gpio45", "gpio46", "gpio47", }; -static const char *const qup1_se4_groups[] = { - "gpio36", "gpio37", "gpio37", "gpio36", +static const char *const qup1_se4_01_groups[] = { + "gpio36", "gpio37", +}; + +static const char *const qup1_se4_23_groups[] = { + "gpio36", "gpio37", }; static const char *const qup1_se5_groups[] = { @@ -994,11 +1007,43 @@ static const char *const qup1_se5_groups[] = { }; static const char *const qup1_se6_groups[] = { - "gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55", + "gpio40", "gpio42", +}; + +static const char *const qup1_se6_l1_mira_groups[] = { + "gpio42", +}; + +static const char *const qup1_se6_l1_mirb_groups[] = { + "gpio54", +}; + +static const char *const qup1_se6_l3_mira_groups[] = { + "gpio40", +}; + +static const char *const qup1_se6_l3_mirb_groups[] = { + "gpio55", }; static const char *const qup1_se7_groups[] = { - "gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78", + "gpio78", "gpio114", +}; + +static const char *const qup1_se7_l0_mira_groups[] = { + "gpio81", +}; + +static const char *const qup1_se7_l0_mirb_groups[] = { + "gpio78", +}; + +static const char *const qup1_se7_l1_mira_groups[] = { + "gpio80", +}; + +static const char *const qup1_se7_l1_mirb_groups[] = { + "gpio114", }; static const char *const qup2_se0_groups[] = { @@ -1014,7 +1059,23 @@ static const char *const qup2_se2_groups[] = { }; static const char *const qup2_se3_groups[] = { - "gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116", + "gpio100", "gpio116", +}; + +static const char *const qup2_se3_l0_mira_groups[] = { + "gpio79", +}; + +static const char *const qup2_se3_l0_mirb_groups[] = { + "gpio116", +}; + +static const char *const qup2_se3_l1_mira_groups[] = { + "gpio97", +}; + +static const char *const qup2_se3_l1_mirb_groups[] = { + "gpio100", }; static const char *const qup2_se4_groups[] = { @@ -1236,15 +1297,32 @@ static const struct pinfunction eliza_functions[] = { MSM_PIN_FUNCTION(qup1_se0), MSM_PIN_FUNCTION(qup1_se1), MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se2_l2_mira), + MSM_PIN_FUNCTION(qup1_se2_l2_mirb), + MSM_PIN_FUNCTION(qup1_se2_l3_mira), + MSM_PIN_FUNCTION(qup1_se2_l3_mirb), MSM_PIN_FUNCTION(qup1_se3), - MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se4_01), + MSM_PIN_FUNCTION(qup1_se4_23), MSM_PIN_FUNCTION(qup1_se5), MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se6_l1_mira), + MSM_PIN_FUNCTION(qup1_se6_l1_mirb), + MSM_PIN_FUNCTION(qup1_se6_l3_mira), + MSM_PIN_FUNCTION(qup1_se6_l3_mirb), MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup1_se7_l0_mira), + MSM_PIN_FUNCTION(qup1_se7_l0_mirb), + MSM_PIN_FUNCTION(qup1_se7_l1_mira), + MSM_PIN_FUNCTION(qup1_se7_l1_mirb), MSM_PIN_FUNCTION(qup2_se0), MSM_PIN_FUNCTION(qup2_se1), MSM_PIN_FUNCTION(qup2_se2), MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se3_l0_mira), + MSM_PIN_FUNCTION(qup2_se3_l0_mirb), + MSM_PIN_FUNCTION(qup2_se3_l1_mira), + MSM_PIN_FUNCTION(qup2_se3_l1_mirb), MSM_PIN_FUNCTION(qup2_se4), MSM_PIN_FUNCTION(qup2_se5), MSM_PIN_FUNCTION(qup2_se6), @@ -1322,33 +1400,33 @@ static const struct msm_pingroup eliza_groups[] = { [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _), [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _), [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _), - [36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), - [37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), - [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), - [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), - [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), + [36] = PINGROUP(36, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se4_01, qup1_se4_23, ibi_i3c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, sdc2, _, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, sdc2, _, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _), - [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6_l1_mira, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _), [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _), [44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _), [45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _), [46] = PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _), [47] = PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _), - [48] = PINGROUP(48, _, _, _, _, _, _, _, _, _, _, _), - [49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, sdc2, _, _, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, sdc2, _, _, _, _, _, _, _, _, _, _), [50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), - [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _), - [52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), - [53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _), - [54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _), - [55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _), + [51] = PINGROUP(51, sdc2, _, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), + [53] = PINGROUP(53, qup1_se2, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_traceclk, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _), [56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _), [57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _), [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _), [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _), [60] = PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _), [61] = PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _), - [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, sdc2, _, _, _, _, _, _, _, _, _, _), [63] = PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _, _, _, _, _), [64] = PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _), [65] = PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _), @@ -1358,16 +1436,16 @@ static const struct msm_pingroup eliza_groups[] = { [69] = PINGROUP(69, cam_mclk, audio_ext_mclk0, resout_gpio, prng_rosc1, _, _, _, _, _, _, _), [70] = PINGROUP(70, cci_i2c_sda, tmess_prng2, _, phase_flag, atest_char, _, _, _, _, _, _), [71] = PINGROUP(71, cci_i2c_scl, tmess_prng3, _, phase_flag, atest_char, _, _, _, _, _, _), - [72] = PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _), + [72] = PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracectl, atest_char, _, _, _, _, _, _, _), [73] = PINGROUP(73, cci_i2c_scl, tmess_prng0, qdss_cti, atest_char, _, _, _, _, _, _, _), [74] = PINGROUP(74, cci_i2c_sda, prng_rosc3, qdss_cti, atest_char, _, _, _, _, _, _, _), [75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _), [76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _), [77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _), - [78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _), - [79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _), - [80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _), - [81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup1_se7, qup1_se7_l0_mirb, _, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _, _, _, _, _, _), [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _), [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _), [84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _), @@ -1383,10 +1461,10 @@ static const struct msm_pingroup eliza_groups[] = { [94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _), [95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _), [96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), - [97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, _, _, _), [98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _), [99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _), - [100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _), + [100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _), [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _), @@ -1400,9 +1478,9 @@ static const struct msm_pingroup eliza_groups[] = { [111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _), [112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _), [113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _), - [114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _), + [114] = PINGROUP(114, qup1_se7, qup1_se7_l1_mirb, _, qdss_gpio_tracedata, _, _, _, _, _, _, _), [115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _), - [116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _), + [116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3_l0_mirb, _, _, _, _, _, _, _), [117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _), [118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _), [119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _), @@ -1430,10 +1508,10 @@ static const struct msm_pingroup eliza_groups[] = { [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, egpio), [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, egpio), [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, egpio), - [144] = PINGROUP(144, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio), + [144] = PINGROUP(144, _, qdss_gpio_tracectl, _, _, _, _, _, _, _, _, egpio), [145] = PINGROUP(145, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _, egpio), [146] = PINGROUP(146, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio), - [147] = PINGROUP(147, ddr_bist_fail, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, ddr_bist_fail, _, qdss_gpio_traceclk, _, _, _, _, _, _, _, egpio), [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio), [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _, _, egpio), [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _, _, egpio), @@ -1519,6 +1597,7 @@ static const struct of_device_id eliza_tlmm_of_match[] = { { .compatible = "qcom,eliza-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match); static struct platform_driver eliza_tlmm_driver = { .driver = { @@ -1542,4 +1621,3 @@ module_exit(eliza_tlmm_exit); MODULE_DESCRIPTION("QTI Eliza TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c index 9838c7839923..20f076e59375 100644 --- a/drivers/pinctrl/qcom/pinctrl-glymur.c +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -1777,6 +1777,7 @@ static const struct of_device_id glymur_tlmm_of_match[] = { { .compatible = "qcom,mahua-tlmm", .data = &mahua_tlmm }, { }, }; +MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match); static int glymur_tlmm_probe(struct platform_device *pdev) { @@ -1811,4 +1812,3 @@ module_exit(glymur_tlmm_exit); MODULE_DESCRIPTION("QTI Glymur TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-hawi.c b/drivers/pinctrl/qcom/pinctrl-hawi.c index 5c7894f3b9cb..cdde69e954a7 100644 --- a/drivers/pinctrl/qcom/pinctrl-hawi.c +++ b/drivers/pinctrl/qcom/pinctrl-hawi.c @@ -1584,6 +1584,7 @@ static const struct of_device_id hawi_tlmm_of_match[] = { { .compatible = "qcom,hawi-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match); static struct platform_driver hawi_tlmm_driver = { .driver = { @@ -1607,4 +1608,3 @@ module_exit(hawi_tlmm_exit); MODULE_DESCRIPTION("QTI Hawi TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index c5f0decc3eb3..adf7c8631f72 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -479,7 +479,7 @@ static const struct pinfunction ipq4019_functions[] = { QCA_PIN_FUNCTION(blsp_uart0), QCA_PIN_FUNCTION(blsp_uart1), QCA_PIN_FUNCTION(chip_rst), - QCA_PIN_FUNCTION(gpio), + QCA_GPIO_PIN_FUNCTION(gpio), QCA_PIN_FUNCTION(i2s_rx), QCA_PIN_FUNCTION(i2s_spdif_in), QCA_PIN_FUNCTION(i2s_spdif_out), @@ -702,6 +702,7 @@ static const struct of_device_id ipq4019_pinctrl_of_match[] = { { .compatible = "qcom,ipq4019-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match); static struct platform_driver ipq4019_pinctrl_driver = { .driver = { @@ -725,4 +726,3 @@ module_exit(ipq4019_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c index 0698c8f0110b..03cfba9534f8 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -4,7 +4,6 @@ */ #include <linux/module.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-msm.h" diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5210.c b/drivers/pinctrl/qcom/pinctrl-ipq5210.c index 827a4ad07a6b..d5b4eb3e7343 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5210.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5210.c @@ -867,6 +867,7 @@ static const struct of_device_id ipq5210_tlmm_of_match[] = { { .compatible = "qcom,ipq5210-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq5210_tlmm_of_match); static int ipq5210_tlmm_probe(struct platform_device *pdev) { diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c index cc83f9362a85..9a42e343ff17 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -1072,6 +1072,7 @@ static const struct of_device_id ipq6018_pinctrl_of_match[] = { { .compatible = "qcom,ipq6018-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match); static struct platform_driver ipq6018_pinctrl_driver = { .driver = { @@ -1095,4 +1096,3 @@ module_exit(ipq6018_pinctrl_exit); MODULE_DESCRIPTION("QTI ipq6018 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c index 0a9e357e64c6..0a50486337d3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -480,7 +480,7 @@ static const char * const ps_hold_groups[] = { }; static const struct pinfunction ipq8064_functions[] = { - IPQ_PIN_FUNCTION(gpio), + IPQ_GPIO_PIN_FUNCTION(gpio), IPQ_PIN_FUNCTION(mdio), IPQ_PIN_FUNCTION(ssbi), IPQ_PIN_FUNCTION(spmi), @@ -507,19 +507,19 @@ static const struct pinfunction ipq8064_functions[] = { IPQ_PIN_FUNCTION(usb2_hsic), IPQ_PIN_FUNCTION(rgmii2), IPQ_PIN_FUNCTION(sata), - IPQ_PIN_FUNCTION(pcie1_rst), + IPQ_GPIO_PIN_FUNCTION(pcie1_rst), IPQ_PIN_FUNCTION(pcie1_prsnt), IPQ_PIN_FUNCTION(pcie1_pwren_n), IPQ_PIN_FUNCTION(pcie1_pwren), IPQ_PIN_FUNCTION(pcie1_pwrflt), IPQ_PIN_FUNCTION(pcie1_clk_req), - IPQ_PIN_FUNCTION(pcie2_rst), + IPQ_GPIO_PIN_FUNCTION(pcie2_rst), IPQ_PIN_FUNCTION(pcie2_prsnt), IPQ_PIN_FUNCTION(pcie2_pwren_n), IPQ_PIN_FUNCTION(pcie2_pwren), IPQ_PIN_FUNCTION(pcie2_pwrflt), IPQ_PIN_FUNCTION(pcie2_clk_req), - IPQ_PIN_FUNCTION(pcie3_rst), + IPQ_GPIO_PIN_FUNCTION(pcie3_rst), IPQ_PIN_FUNCTION(pcie3_prsnt), IPQ_PIN_FUNCTION(pcie3_pwren_n), IPQ_PIN_FUNCTION(pcie3_pwren), @@ -624,6 +624,7 @@ static const struct of_device_id ipq8064_pinctrl_of_match[] = { { .compatible = "qcom,ipq8064-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); static struct platform_driver ipq8064_pinctrl_driver = { .driver = { @@ -648,4 +649,3 @@ module_exit(ipq8064_pinctrl_exit); MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c index 64ce8ea8f544..0b95f52adcc3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8074.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -1033,6 +1033,7 @@ static const struct of_device_id ipq8074_pinctrl_of_match[] = { { .compatible = "qcom,ipq8074-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match); static struct platform_driver ipq8074_pinctrl_driver = { .driver = { @@ -1056,4 +1057,3 @@ module_exit(ipq8074_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9650.c b/drivers/pinctrl/qcom/pinctrl-ipq9650.c new file mode 100644 index 000000000000..5399d7ad934c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq9650.c @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + }, \ + .nfuncs = 10, \ + } + +static const struct pinctrl_pin_desc ipq9650_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); + +enum ipq9650_functions { + msm_mux_atest_char_start, + msm_mux_atest_char_status0, + msm_mux_atest_char_status1, + msm_mux_atest_char_status2, + msm_mux_atest_char_status3, + msm_mux_atest_tic_en, + msm_mux_audio_pri_mclk_in0, + msm_mux_audio_pri_mclk_out0, + msm_mux_audio_pri_mclk_in1, + msm_mux_audio_pri_mclk_out1, + msm_mux_audio_pri, + msm_mux_audio_sec, + msm_mux_audio_sec_mclk_in0, + msm_mux_audio_sec_mclk_out0, + msm_mux_audio_sec_mclk_in1, + msm_mux_audio_sec_mclk_out1, + msm_mux_core_voltage_0, + msm_mux_core_voltage_1, + msm_mux_core_voltage_2, + msm_mux_core_voltage_3, + msm_mux_core_voltage_4, + msm_mux_cri_rng0, + msm_mux_cri_rng1, + msm_mux_cri_rng2, + msm_mux_dbg_out_clk, + msm_mux_gcc_plltest_bypassnl, + msm_mux_gcc_plltest_resetn, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_mdc_mst, + msm_mux_mdc_slv0, + msm_mux_mdc_slv1, + msm_mux_mdio_mst, + msm_mux_mdio_slv, + msm_mux_mdio_slv0, + msm_mux_mdio_slv1, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk_req_n, + msm_mux_pcie2_wake, + msm_mux_pcie3_clk_req_n, + msm_mux_pcie3_wake, + msm_mux_pcie4_clk_req_n, + msm_mux_pcie4_wake, + msm_mux_pll_bist_sync, + msm_mux_pll_test, + msm_mux_pwm, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs_n, + msm_mux_qup_se0, + msm_mux_qup_se1, + msm_mux_qup_se2, + msm_mux_qup_se3, + msm_mux_qup_se4, + msm_mux_qup_se5, + msm_mux_qup_se6, + msm_mux_qup_se7, + msm_mux_resout, + msm_mux_rx_los0, + msm_mux_rx_los1, + msm_mux_rx_los2, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_tsens_max, + msm_mux_tsn, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char *const atest_char_start_groups[] = { + "gpio21", +}; + +static const char *const atest_char_status0_groups[] = { + "gpio33", +}; + +static const char *const atest_char_status1_groups[] = { + "gpio35", +}; + +static const char *const atest_char_status2_groups[] = { + "gpio22", +}; + +static const char *const atest_char_status3_groups[] = { + "gpio23", +}; + +static const char *const atest_tic_en_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_in0_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_out0_groups[] = { + "gpio53", +}; + +static const char *const audio_pri_mclk_in1_groups[] = { + "gpio51", +}; + +static const char *const audio_pri_mclk_out1_groups[] = { + "gpio51", +}; + +static const char *const audio_pri_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const audio_sec_mclk_in0_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_out0_groups[] = { + "gpio37", +}; + +static const char *const audio_sec_mclk_in1_groups[] = { + "gpio39", +}; + +static const char *const audio_sec_mclk_out1_groups[] = { + "gpio39", +}; + +static const char *const audio_sec_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char *const core_voltage_0_groups[] = { + "gpio16", +}; + +static const char *const core_voltage_1_groups[] = { + "gpio17", +}; + +static const char *const core_voltage_2_groups[] = { + "gpio33", +}; + +static const char *const core_voltage_3_groups[] = { + "gpio34", +}; + +static const char *const core_voltage_4_groups[] = { + "gpio35", +}; + +static const char *const cri_rng0_groups[] = { + "gpio6", +}; + +static const char *const cri_rng1_groups[] = { + "gpio7", +}; + +static const char *const cri_rng2_groups[] = { + "gpio8", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio46", +}; + +static const char *const gcc_plltest_bypassnl_groups[] = { + "gpio33", +}; + +static const char *const gcc_plltest_resetn_groups[] = { + "gpio35", +}; + +static const char *const gcc_tlmm_groups[] = { + "gpio34", +}; + +static const char *const mdc_mst_groups[] = { + "gpio22", +}; + +static const char *const mdc_slv0_groups[] = { + "gpio20", +}; + +static const char *const mdc_slv1_groups[] = { + "gpio14", +}; + +static const char *const mdio_mst_groups[] = { + "gpio23", +}; + +static const char *const mdio_slv_groups[] = { + "gpio46", + "gpio47", +}; + +static const char *const mdio_slv0_groups[] = { + "gpio21", +}; + +static const char *const mdio_slv1_groups[] = { + "gpio15", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio24", +}; + +static const char *const pcie0_wake_groups[] = { + "gpio26", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio27", +}; + +static const char *const pcie1_wake_groups[] = { + "gpio29", +}; + +static const char *const pcie2_clk_req_n_groups[] = { + "gpio51", +}; + +static const char *const pcie2_wake_groups[] = { + "gpio53", +}; + +static const char *const pcie3_clk_req_n_groups[] = { + "gpio40", +}; + +static const char *const pcie3_wake_groups[] = { + "gpio42", +}; + +static const char *const pcie4_clk_req_n_groups[] = { + "gpio30", +}; + +static const char *const pcie4_wake_groups[] = { + "gpio32", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio47", +}; + +static const char *const pll_test_groups[] = { + "gpio39", +}; + +static const char *const pwm_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio16", + "gpio17", "gpio33", "gpio34", "gpio35", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", +}; + +static const char *const qdss_cti_trig_in_a0_groups[] = { + "gpio53", +}; + +static const char *const qdss_cti_trig_in_a1_groups[] = { + "gpio29", +}; + +static const char *const qdss_cti_trig_in_b0_groups[] = { + "gpio42", +}; + +static const char *const qdss_cti_trig_in_b1_groups[] = { + "gpio43", +}; + +static const char *const qdss_cti_trig_out_a0_groups[] = { + "gpio51", +}; + +static const char *const qdss_cti_trig_out_a1_groups[] = { + "gpio27", +}; + +static const char *const qdss_cti_trig_out_b0_groups[] = { + "gpio40", +}; + +static const char *const qdss_cti_trig_out_b1_groups[] = { + "gpio44", +}; + +static const char *const qdss_traceclk_a_groups[] = { + "gpio45", +}; + +static const char *const qdss_tracectl_a_groups[] = { + "gpio46", +}; + +static const char *const qdss_tracedata_a_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qspi_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qspi_clk_groups[] = { + "gpio5", +}; + +static const char *const qspi_cs_n_groups[] = { + "gpio4", +}; + +static const char *const qup_se0_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio51", "gpio53", +}; + +static const char *const qup_se1_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio27", "gpio29", +}; + +static const char *const qup_se2_groups[] = { + "gpio27", "gpio29", "gpio33", "gpio34", +}; + +static const char *const qup_se3_groups[] = { + "gpio16", "gpio17", "gpio20", "gpio21", +}; + +static const char *const qup_se4_groups[] = { + "gpio14", "gpio15", "gpio40", "gpio42", "gpio43", "gpio44", +}; + +static const char *const qup_se5_groups[] = { + "gpio40", "gpio42", "gpio45", "gpio46", "gpio47", "gpio48", +}; + +static const char *const qup_se6_groups[] = { + "gpio43", "gpio44", "gpio51", "gpio53", +}; + +static const char *const qup_se7_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const resout_groups[] = { + "gpio49", +}; + +static const char *const rx_los0_groups[] = { + "gpio39", "gpio47", "gpio50", +}; + +static const char *const rx_los1_groups[] = { + "gpio38", "gpio46", +}; + +static const char *const rx_los2_groups[] = { + "gpio37", "gpio45", +}; + +static const char *const sdc_clk_groups[] = { + "gpio5", +}; + +static const char *const sdc_cmd_groups[] = { + "gpio4", +}; + +static const char *const sdc_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const tsens_max_groups[] = { + "gpio14", +}; + +static const char *const tsn_groups[] = { + "gpio50", +}; + +static const struct pinfunction ipq9650_functions[] = { + MSM_PIN_FUNCTION(atest_char_start), + MSM_PIN_FUNCTION(atest_char_status0), + MSM_PIN_FUNCTION(atest_char_status1), + MSM_PIN_FUNCTION(atest_char_status2), + MSM_PIN_FUNCTION(atest_char_status3), + MSM_PIN_FUNCTION(atest_tic_en), + MSM_PIN_FUNCTION(audio_pri_mclk_in0), + MSM_PIN_FUNCTION(audio_pri_mclk_out0), + MSM_PIN_FUNCTION(audio_pri_mclk_in1), + MSM_PIN_FUNCTION(audio_pri_mclk_out1), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(audio_sec_mclk_in0), + MSM_PIN_FUNCTION(audio_sec_mclk_out0), + MSM_PIN_FUNCTION(audio_sec_mclk_in1), + MSM_PIN_FUNCTION(audio_sec_mclk_out1), + MSM_PIN_FUNCTION(core_voltage_0), + MSM_PIN_FUNCTION(core_voltage_1), + MSM_PIN_FUNCTION(core_voltage_2), + MSM_PIN_FUNCTION(core_voltage_3), + MSM_PIN_FUNCTION(core_voltage_4), + MSM_PIN_FUNCTION(cri_rng0), + MSM_PIN_FUNCTION(cri_rng1), + MSM_PIN_FUNCTION(cri_rng2), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(gcc_plltest_bypassnl), + MSM_PIN_FUNCTION(gcc_plltest_resetn), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv0), + MSM_PIN_FUNCTION(mdc_slv1), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv), + MSM_PIN_FUNCTION(mdio_slv0), + MSM_PIN_FUNCTION(mdio_slv1), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(pcie2_wake), + MSM_PIN_FUNCTION(pcie3_clk_req_n), + MSM_PIN_FUNCTION(pcie3_wake), + MSM_PIN_FUNCTION(pcie4_clk_req_n), + MSM_PIN_FUNCTION(pcie4_wake), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(pwm), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs_n), + MSM_PIN_FUNCTION(qup_se0), + MSM_PIN_FUNCTION(qup_se1), + MSM_PIN_FUNCTION(qup_se2), + MSM_PIN_FUNCTION(qup_se3), + MSM_PIN_FUNCTION(qup_se4), + MSM_PIN_FUNCTION(qup_se5), + MSM_PIN_FUNCTION(qup_se6), + MSM_PIN_FUNCTION(qup_se7), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx_los0), + MSM_PIN_FUNCTION(rx_los1), + MSM_PIN_FUNCTION(rx_los2), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(tsens_max), + MSM_PIN_FUNCTION(tsn), +}; + +static const struct msm_pingroup ipq9650_groups[] = { + [0] = PINGROUP(0, sdc_data, qspi_data, _, _, _, _, _, _, _), + [1] = PINGROUP(1, sdc_data, qspi_data, _, _, _, _, _, _, _), + [2] = PINGROUP(2, sdc_data, qspi_data, _, _, _, _, _, _, _), + [3] = PINGROUP(3, sdc_data, qspi_data, _, _, _, _, _, _, _), + [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _), + [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup_se0, pwm, _, cri_rng0, qdss_tracedata_a, _, _, _, _), + [7] = PINGROUP(7, qup_se0, pwm, _, cri_rng1, qdss_tracedata_a, _, _, _, _), + [8] = PINGROUP(8, qup_se0, pwm, _, cri_rng2, qdss_tracedata_a, _, _, _, _), + [9] = PINGROUP(9, qup_se0, pwm, _, qdss_tracedata_a, _, _, _, _, _), + [10] = PINGROUP(10, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _), + [11] = PINGROUP(11, qup_se1, pwm, _, _, qdss_tracedata_a, _, _, _, _), + [12] = PINGROUP(12, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _), + [13] = PINGROUP(13, qup_se1, _, qdss_tracedata_a, _, _, _, _, _, _), + [14] = PINGROUP(14, qup_se4, mdc_slv1, tsens_max, _, qdss_tracedata_a, _, _, _, _), + [15] = PINGROUP(15, qup_se4, mdio_slv1, _, qdss_tracedata_a, _, _, _, _, _), + [16] = PINGROUP(16, core_voltage_0, qup_se3, pwm, _, _, _, _, _, _), + [17] = PINGROUP(17, core_voltage_1, qup_se3, pwm, _, _, _, _, _, _), + [18] = PINGROUP(18, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, mdc_slv0, qup_se3, _, qdss_tracedata_a, _, _, _, _, _), + [21] = PINGROUP(21, mdio_slv0, qup_se3, atest_char_start, _, qdss_tracedata_a, _, _, _, _), + [22] = PINGROUP(22, mdc_mst, atest_char_status2, _, _, _, _, _, _, _), + [23] = PINGROUP(23, mdio_mst, atest_char_status3, _, _, _, _, _, _, _), + [24] = PINGROUP(24, pcie0_clk_req_n, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, pcie0_wake, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, pcie1_clk_req_n, qup_se2, qup_se1, _, qdss_cti_trig_out_a1, _, _, _, _), + [28] = PINGROUP(28, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, pcie1_wake, qup_se2, qup_se1, _, qdss_cti_trig_in_a1, _, _, _, _), + [30] = PINGROUP(30, pcie4_clk_req_n, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, pcie4_wake, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, core_voltage_2, qup_se2, gcc_plltest_bypassnl, pwm, atest_char_status0, _, _, _, _), + [34] = PINGROUP(34, core_voltage_3, qup_se2, gcc_tlmm, pwm, _, _, _, _, _), + [35] = PINGROUP(35, core_voltage_4, gcc_plltest_resetn, pwm, atest_char_status1, _, _, _, _, _), + [36] = PINGROUP(36, audio_pri, qup_se7, qdss_tracedata_a, _, _, _, _, _, _), + [37] = PINGROUP(37, audio_pri, qup_se7, audio_sec_mclk_out0, audio_sec_mclk_in0, rx_los2, qdss_tracedata_a, _, _, _), + [38] = PINGROUP(38, audio_pri, qup_se7, rx_los1, qdss_tracedata_a, _, _, _, _, _), + [39] = PINGROUP(39, audio_pri, qup_se7, audio_sec_mclk_out1, audio_sec_mclk_in1, pll_test, rx_los0, _, qdss_tracedata_a, _), + [40] = PINGROUP(40, pcie3_clk_req_n, qup_se5, qup_se4, _, qdss_cti_trig_out_b0, _, _, _, _), + [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, pcie3_wake, qup_se5, qup_se4, _, qdss_cti_trig_in_b0, _, _, _, _), + [43] = PINGROUP(43, qup_se4, qup_se6, pwm, _, qdss_cti_trig_in_b1, _, _, _, _), + [44] = PINGROUP(44, qup_se4, qup_se6, pwm, _, qdss_cti_trig_out_b1, _, _, _, _), + [45] = PINGROUP(45, qup_se5, rx_los2, audio_sec, pwm, _, qdss_traceclk_a, _, _, _), + [46] = PINGROUP(46, qup_se5, rx_los1, audio_sec, mdio_slv, pwm, dbg_out_clk, qdss_tracectl_a, _, _), + [47] = PINGROUP(47, qup_se5, rx_los0, audio_sec, mdio_slv, pll_bist_sync, pwm, _, _, _), + [48] = PINGROUP(48, qup_se5, audio_sec, pwm, _, _, _, _, _, _), + [49] = PINGROUP(49, resout, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, tsn, rx_los0, _, _, _, _, _, _, _), + [51] = PINGROUP(51, pcie2_clk_req_n, qup_se6, qup_se0, audio_pri_mclk_out1, audio_pri_mclk_in1, qdss_cti_trig_out_a0, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, pcie2_wake, qup_se6, qup_se0, audio_pri_mclk_out0, audio_pri_mclk_in0, qdss_cti_trig_in_a0, _, atest_tic_en, _), +}; + +static const struct msm_pinctrl_soc_data ipq9650_tlmm = { + .pins = ipq9650_pins, + .npins = ARRAY_SIZE(ipq9650_pins), + .functions = ipq9650_functions, + .nfunctions = ARRAY_SIZE(ipq9650_functions), + .groups = ipq9650_groups, + .ngroups = ARRAY_SIZE(ipq9650_groups), + .ngpios = 54, +}; + +static const struct of_device_id ipq9650_tlmm_of_match[] = { + { .compatible = "qcom,ipq9650-tlmm", }, + {}, +}; + +static int ipq9650_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq9650_tlmm); +} + +static struct platform_driver ipq9650_tlmm_driver = { + .driver = { + .name = "ipq9650-tlmm", + .of_match_table = ipq9650_tlmm_of_match, + }, + .probe = ipq9650_tlmm_probe, +}; + +static int __init ipq9650_tlmm_init(void) +{ + return platform_driver_register(&ipq9650_tlmm_driver); +} +arch_initcall(ipq9650_tlmm_init); + +static void __exit ipq9650_tlmm_exit(void) +{ + platform_driver_unregister(&ipq9650_tlmm_driver); +} +module_exit(ipq9650_tlmm_exit); + +MODULE_DESCRIPTION("QTI IPQ9650 TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-kaanapali.c b/drivers/pinctrl/qcom/pinctrl-kaanapali.c index 5cc45b9c55ab..e95ac064b84c 100644 --- a/drivers/pinctrl/qcom/pinctrl-kaanapali.c +++ b/drivers/pinctrl/qcom/pinctrl-kaanapali.c @@ -1774,6 +1774,7 @@ static const struct of_device_id kaanapali_tlmm_of_match[] = { { .compatible = "qcom,kaanapali-tlmm",}, {}, }; +MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match); static struct platform_driver kaanapali_tlmm_driver = { .driver = { @@ -1797,4 +1798,3 @@ module_exit(kaanapali_tlmm_exit); MODULE_DESCRIPTION("QTI Kaanapali TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, kaanapali_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 76aed3296279..5fd4a4eba654 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -11,10 +11,13 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/seq_file.h> +#include <linux/cleanup.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinmux.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "../pinctrl-utils.h" @@ -22,7 +25,6 @@ #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 struct lpi_pinctrl { struct device *dev; @@ -31,15 +33,14 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); const struct lpi_pinctrl_variant_data *data; }; -static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr) +static void __iomem *lpi_gpio_reg(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr) { u32 pin_offset; @@ -48,22 +49,34 @@ static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, else pin_offset = LPI_TLMM_REG_OFFSET * pin; - return ioread32(state->tlmm_base + pin_offset + addr); + return state->tlmm_base + pin_offset + addr; } -static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr, unsigned int val) +static void lpi_gpio_read_reg(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr, u32 *val) { - u32 pin_offset; + *val = ioread32(lpi_gpio_reg(state, pin, addr)); +} - if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) - pin_offset = state->data->groups[pin].pin_offset; - else - pin_offset = LPI_TLMM_REG_OFFSET * pin; +static void lpi_gpio_write_reg(struct lpi_pinctrl *state, + unsigned int pin, unsigned int addr, + unsigned int val) +{ + iowrite32(val, lpi_gpio_reg(state, pin, addr)); +} - iowrite32(val, state->tlmm_base + pin_offset + addr); +static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr, u32 *val) +{ + int ret; - return 0; + ret = pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return ret; + + lpi_gpio_read_reg(state, pin, addr, val); + + return pm_runtime_put_autosuspend(state->dev); } static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { @@ -107,8 +120,8 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, { struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct lpi_pingroup *g = &pctrl->data->groups[group]; - u32 val; - int i, pin = g->pin; + u32 io_val, val; + int i, pin = g->pin, ret; for (i = 0; i < g->nfuncs; i++) { if (g->funcs[i] == function) @@ -118,8 +131,12 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, if (WARN_ON(i == g->nfuncs)) return -EINVAL; - mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + ret = pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + + guard(mutex)(&pctrl->lock); + lpi_gpio_read_reg(pctrl, pin, LPI_GPIO_CFG_REG, &val); /* * If this is the first time muxing to GPIO and the direction is @@ -129,24 +146,25 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, */ if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && !test_and_set_bit(group, pctrl->ever_gpio)) { - u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + lpi_gpio_read_reg(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); if (io_val & LPI_GPIO_VALUE_IN_MASK) { if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val | LPI_GPIO_VALUE_OUT_MASK); + lpi_gpio_write_reg(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); } else { if (io_val & LPI_GPIO_VALUE_OUT_MASK) - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, - io_val & ~LPI_GPIO_VALUE_OUT_MASK); + lpi_gpio_write_reg(pctrl, group, + LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); } } u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); - lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + lpi_gpio_write_reg(pctrl, pin, LPI_GPIO_CFG_REG, val); - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } static const struct pinmux_ops lpi_gpio_pinmux_ops = { @@ -162,11 +180,15 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, unsigned int param = pinconf_to_config_param(*config); struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); unsigned int arg = 0; + u32 ctl_reg; int is_out; int pull; - u32 ctl_reg; + int ret; + + ret = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG, &ctl_reg); + if (ret) + return ret; - ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); is_out = ctl_reg & LPI_GPIO_OE_MASK; pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); @@ -197,6 +219,7 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, } *config = pinconf_to_config_packed(param, arg); + return 0; } @@ -206,7 +229,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, { unsigned long sval; void __iomem *reg; - int slew_offset; + int slew_offset, ret; if (slew > LPI_SLEW_RATE_MAX) { dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", @@ -220,9 +243,15 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; + else if (g->slew_base_spare_1) + reg = pctrl->slew_base + LPI_SPARE_1_REG; else reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; + ret = pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + mutex_lock(&pctrl->lock); sval = ioread32(reg); @@ -232,7 +261,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, mutex_unlock(&pctrl->lock); - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, @@ -242,8 +271,8 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; bool value, output_enabled = false; const struct lpi_pingroup *g; - int i, ret; u32 val; + int i, ret; g = &pctrl->data->groups[group]; for (i = 0; i < nconfs; i++) { @@ -287,23 +316,26 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, * As per Hardware Programming Guide, when configuring pin as output, * set the pin value before setting output-enable (OE). */ + ret = pm_runtime_resume_and_get(pctrl->dev); + if (ret < 0) + return ret; + + guard(mutex)(&pctrl->lock); if (output_enabled) { val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + lpi_gpio_write_reg(pctrl, group, LPI_GPIO_VALUE_REG, val); } - mutex_lock(&pctrl->lock); - val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); + lpi_gpio_read_reg(pctrl, group, LPI_GPIO_CFG_REG, &val); u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), LPI_GPIO_OUT_STRENGTH_MASK); u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - mutex_unlock(&pctrl->lock); + lpi_gpio_write_reg(pctrl, group, LPI_GPIO_CFG_REG, val); - return 0; + return pm_runtime_put_autosuspend(pctrl->dev); } static const struct pinconf_ops lpi_gpio_pinconf_ops = { @@ -352,9 +384,14 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip, static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) { struct lpi_pinctrl *state = gpiochip_get_data(chip); + u32 val; + int ret; + + ret = lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG, &val); + if (ret) + return ret; - return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & - LPI_GPIO_VALUE_IN_MASK; + return val & LPI_GPIO_VALUE_IN_MASK; } static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) @@ -397,7 +434,9 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s, pctldev = pctldev ? : state->ctrl; pindesc = pctldev->desc->pins[offset]; - ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); + if (lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG, &ctl_reg)) + return; + is_out = ctl_reg & LPI_GPIO_OE_MASK; func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); @@ -480,9 +519,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data = data; pctrl->dev = &pdev->dev; - pctrl->clks[0].id = "core"; - pctrl->clks[1].id = "audio"; - pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -495,13 +531,19 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } - ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret = devm_pm_clk_create(dev); if (ret) return ret; - ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); + ret = of_pm_clk_add_clks(dev); + if (ret < 0 && ret != -ENODEV) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + ret = devm_pm_runtime_enable(dev); if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + return ret; pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; @@ -540,7 +582,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) err_pinctrl: mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); return ret; } @@ -552,7 +593,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) int i; mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); for (i = 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index f48368492861..6ba0c4eba984 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -16,6 +16,7 @@ struct platform_device; struct pinctrl_pin_desc; #define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_SPARE_1_REG 0xc000 #define LPI_TLMM_REG_OFFSET 0x1000 #define LPI_SLEW_RATE_MAX 0x03 #define LPI_SLEW_BITS_SIZE 0x02 @@ -47,6 +48,7 @@ struct pinctrl_pin_desc; { \ .pin = id, \ .slew_offset = soff, \ + .slew_base_spare_1 = false, \ .funcs = (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -62,6 +64,7 @@ struct pinctrl_pin_desc; { \ .pin = id, \ .slew_offset = soff, \ + .slew_base_spare_1 = false, \ .funcs = (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -73,6 +76,22 @@ struct pinctrl_pin_desc; .pin_offset = poff, \ } +#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \ + { \ + .pin = id, \ + .slew_offset = soff, \ + .slew_base_spare_1 = true, \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + .pin_offset = 0, \ + } + /* * Slew rate control is done in the same register as rest of the * pin configuration. @@ -87,6 +106,7 @@ struct lpi_pingroup { unsigned int *funcs; unsigned int nfuncs; unsigned int pin_offset; + bool slew_base_spare_1; }; struct lpi_function { diff --git a/drivers/pinctrl/qcom/pinctrl-maili.c b/drivers/pinctrl/qcom/pinctrl-maili.c new file mode 100644 index 000000000000..ffa084cfad64 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-maili.c @@ -0,0 +1,1625 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc maili_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "UFS_RESET"), + PINCTRL_PIN(227, "SDC2_CLK"), + PINCTRL_PIN(228, "SDC2_CMD"), + PINCTRL_PIN(229, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); + +static const unsigned int ufs_reset_pins[] = { 226 }; +static const unsigned int sdc2_clk_pins[] = { 227 }; +static const unsigned int sdc2_cmd_pins[] = { 228 }; +static const unsigned int sdc2_data_pins[] = { 229 }; + +enum maili_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_cci_i2c2, + msm_mux_cci_i2c3, + msm_mux_cci_timer, + msm_mux_coex_espmi, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dp_hot, + msm_mux_egpio, + msm_mux_gcc_gp, + msm_mux_gnss_adc, + msm_mux_host2wlan_sol, + msm_mux_host_rst, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2s0, + msm_mux_i2s1, + msm_mux_ibi_i3c, + msm_mux_ibi_i3c_qup5_se0, + msm_mux_jitter_bist, + msm_mux_mdp_esync0, + msm_mux_mdp_esync1, + msm_mux_mdp_esync2, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync5_out, + msm_mux_modem_pps_in, + msm_mux_modem_pps_out, + msm_mux_nav_gpio, + msm_mux_nav_gpio0, + msm_mux_nav_gpio3, + msm_mux_nav_rffe, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_rst_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_qdss_cti, + msm_mux_qlink, + msm_mux_qspi, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4_01, + msm_mux_qup2_se4_23, + msm_mux_qup3_se0, + msm_mux_qup3_se1, + msm_mux_qup3_se2, + msm_mux_qup3_se3, + msm_mux_qup3_se4, + msm_mux_qup3_se5, + msm_mux_qup4_se0, + msm_mux_qup4_se1, + msm_mux_qup4_se2, + msm_mux_qup4_se3_01, + msm_mux_qup4_se3_23, + msm_mux_qup4_se3_l3, + msm_mux_qup4_se4_01, + msm_mux_qup4_se4_23, + msm_mux_qup4_se4_l3, + msm_mux_qup5_se0, + msm_mux_rng_rosc, + msm_mux_sd_write_protect, + msm_mux_sdc2_clk, + msm_mux_sdc2_cmd, + msm_mux_sdc2_data, + msm_mux_sdc2_rclk, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sys_throttle, + msm_mux_tb_trig_sdc, + msm_mux_tmess_rng, + msm_mux_tsense_clm, + msm_mux_tsense_pwm, + msm_mux_uim0, + msm_mux_uim1, + msm_mux_usb0_hs, + msm_mux_usb_phy, + msm_mux_vfr, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const aoss_cti_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const atest_char_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133", +}; + +static const char *const atest_usb_groups[] = { + "gpio78", "gpio79", "gpio102", "gpio103", "gpio104", +}; + +static const char *const audio_ext_mclk_groups[] = { + "gpio120", "gpio121", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio120", +}; + +static const char *const cam_mclk_groups[] = { + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", +}; + +static const char *const cci_async_in_groups[] = { + "gpio15", "gpio109", "gpio110", +}; + +static const char *const cci_i2c0_groups[] = { + "gpio109", "gpio110", +}; + +static const char *const cci_i2c1_groups[] = { + "gpio111", "gpio112", +}; + +static const char *const cci_i2c2_groups[] = { + "gpio113", "gpio114", +}; + +static const char *const cci_i2c3_groups[] = { + "gpio107", "gpio160", +}; + +static const char *const cci_timer_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160", +}; + +static const char *const coex_espmi_groups[] = { + "gpio144", "gpio145", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio144", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio145", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio82", +}; + +static const char *const ddr_bist_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio45", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", +}; + +static const char *const dp_hot_groups[] = { + "gpio47", +}; + +static const char *const egpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", "gpio217", "gpio218", +}; + +static const char *const gcc_gp_groups[] = { + "gpio17", "gpio86", "gpio87", "gpio97", "gpio155", "gpio156", +}; + +static const char *const gnss_adc_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio23", +}; + +static const char *const host2wlan_sol_groups[] = { + "gpio204", +}; + +static const char *const host_rst_groups[] = { + "gpio106", +}; + +static const char *const i2chub0_se0_groups[] = { + "gpio66", "gpio67", +}; + +static const char *const i2chub0_se1_groups[] = { + "gpio78", "gpio79", +}; + +static const char *const i2chub0_se2_groups[] = { + "gpio68", "gpio69", +}; + +static const char *const i2chub0_se3_groups[] = { + "gpio70", "gpio71", +}; + +static const char *const i2chub0_se4_groups[] = { + "gpio72", "gpio73", +}; + +static const char *const i2s0_groups[] = { + "gpio46", "gpio84", "gpio161", "gpio162", +}; + +static const char *const i2s1_groups[] = { + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9", + "gpio12", "gpio13", "gpio24", "gpio25", "gpio28", "gpio29", + "gpio32", "gpio33", "gpio36", "gpio37", "gpio48", "gpio49", + "gpio60", "gpio61", "gpio64", "gpio65", "gpio85", "gpio89", + "gpio117", "gpio118", +}; + +static const char *const ibi_i3c_qup5_se0_groups[] = { + "gpio8", "gpio9", +}; + +static const char *const jitter_bist_groups[] = { + "gpio73", +}; + +static const char *const mdp_esync0_groups[] = { + "gpio88", "gpio100", +}; + +static const char *const mdp_esync1_groups[] = { + "gpio86", "gpio100", +}; + +static const char *const mdp_esync2_groups[] = { + "gpio87", "gpio97", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio97", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio98", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio98", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync5_out_groups[] = { + "gpio87", +}; + +static const char *const modem_pps_in_groups[] = { + "gpio151", +}; + +static const char *const modem_pps_out_groups[] = { + "gpio151", +}; + +static const char *const nav_gpio_groups[] = { + "gpio146", "gpio147", "gpio148", "gpio151", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio150", +}; + +static const char *const nav_gpio3_groups[] = { + "gpio150", +}; + +static const char *const nav_rffe_groups[] = { + "gpio134", "gpio135", "gpio138", "gpio139", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio103", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio221", +}; + +static const char *const pcie1_rst_n_groups[] = { + "gpio220", +}; + +static const char *const phase_flag_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio45", "gpio46", "gpio47", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio161", "gpio162", "gpio169", "gpio170", "gpio171", + "gpio174", "gpio175", "gpio178", "gpio179", "gpio180", "gpio181", + "gpio182", "gpio183", "gpio205", "gpio222", "gpio223", "gpio224", + "gpio225", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio104", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio94", +}; + +static const char *const qdss_cti_groups[] = { + "gpio72", "gpio73", "gpio82", "gpio83", "gpio222", "gpio223", + "gpio224", "gpio225", +}; + +static const char *const qlink_groups[] = { + "gpio152", "gpio153", "gpio154", +}; + +static const char *const qspi_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const qspi_clk_groups[] = { + "gpio83", +}; + +static const char *const qspi_cs_groups[] = { + "gpio146", "gpio148", +}; + +static const char *const qup1_se0_groups[] = { + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const qup1_se1_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio188", "gpio189", "gpio192", "gpio193", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132", +}; + +static const char *const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se7_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qup2_se3_groups[] = { + "gpio97", "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char *const qup2_se4_01_groups[] = { + "gpio208", "gpio209", +}; + +static const char *const qup2_se4_23_groups[] = { + "gpio208", "gpio209", +}; + +static const char *const qup3_se0_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio82", "gpio83", +}; + +static const char *const qup3_se1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15", +}; + +static const char *const qup3_se2_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char *const qup3_se3_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup3_se4_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup3_se5_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup4_se0_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup4_se1_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup4_se2_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup4_se3_01_groups[] = { + "gpio84", "gpio121", +}; + +static const char *const qup4_se3_23_groups[] = { + "gpio84", "gpio121", +}; + +static const char *const qup4_se3_l3_groups[] = { + "gpio98", +}; + +static const char *const qup4_se4_01_groups[] = { + "gpio161", "gpio162", +}; + +static const char *const qup4_se4_23_groups[] = { + "gpio161", "gpio162", +}; + +static const char *const qup4_se4_l3_groups[] = { + "gpio88", +}; + +static const char *const qup5_se0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio16", "gpio17", "gpio85", "gpio89", "gpio100", "gpio214", "gpio215", +}; + +static const char *const rng_rosc_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio85", +}; + +static const char *const sdc2_clk_groups[] = { + "gpio56", +}; + +static const char *const sdc2_cmd_groups[] = { + "gpio57", +}; + +static const char *const sdc2_data_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const sdc2_rclk_groups[] = { + "gpio54", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio83", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio148", +}; + +static const char *const sdc4_data_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const sys_throttle_groups[] = { + "gpio99", +}; + +static const char *const tb_trig_sdc_groups[] = { + "gpio88", "gpio146", +}; + +static const char *const tmess_rng_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const tsense_clm_groups[] = { + "gpio87", "gpio97", "gpio98", "gpio99", "gpio105", "gpio106", + "gpio159", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio35", "gpio38", "gpio58", "gpio87", "gpio97", "gpio98", "gpio99", +}; + +static const char *const uim0_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", +}; + +static const char *const uim1_groups[] = { + "gpio36", "gpio37", "gpio39", "gpio54", "gpio55", "gpio56", "gpio70", + "gpio71", "gpio72", "gpio130", "gpio131", "gpio132", "gpio133", +}; + +static const char *const usb0_hs_groups[] = { + "gpio79", +}; + +static const char *const usb_phy_groups[] = { + "gpio59", "gpio60", +}; + +static const char *const vfr_groups[] = { + "gpio146", "gpio151", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio16", +}; + +static const char *const wcn_sw_groups[] = { + "gpio18", "gpio19", "gpio155", "gpio156", +}; + +static const struct pinfunction maili_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(cci_i2c2), + MSM_PIN_FUNCTION(cci_i2c3), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(coex_espmi), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp), + MSM_PIN_FUNCTION(gnss_adc), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(host_rst), + MSM_PIN_FUNCTION(i2chub0_se0), + MSM_PIN_FUNCTION(i2chub0_se1), + MSM_PIN_FUNCTION(i2chub0_se2), + MSM_PIN_FUNCTION(i2chub0_se3), + MSM_PIN_FUNCTION(i2chub0_se4), + MSM_PIN_FUNCTION(i2s0), + MSM_PIN_FUNCTION(i2s1), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(ibi_i3c_qup5_se0), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0), + MSM_PIN_FUNCTION(mdp_esync1), + MSM_PIN_FUNCTION(mdp_esync2), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync5_out), + MSM_PIN_FUNCTION(modem_pps_in), + MSM_PIN_FUNCTION(modem_pps_out), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(nav_rffe), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_rst_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4_01), + MSM_PIN_FUNCTION(qup2_se4_23), + MSM_PIN_FUNCTION(qup3_se0), + MSM_PIN_FUNCTION(qup3_se1), + MSM_PIN_FUNCTION(qup3_se2), + MSM_PIN_FUNCTION(qup3_se3), + MSM_PIN_FUNCTION(qup3_se4), + MSM_PIN_FUNCTION(qup3_se5), + MSM_PIN_FUNCTION(qup4_se0), + MSM_PIN_FUNCTION(qup4_se1), + MSM_PIN_FUNCTION(qup4_se2), + MSM_PIN_FUNCTION(qup4_se3_01), + MSM_PIN_FUNCTION(qup4_se3_23), + MSM_PIN_FUNCTION(qup4_se3_l3), + MSM_PIN_FUNCTION(qup4_se4_01), + MSM_PIN_FUNCTION(qup4_se4_23), + MSM_PIN_FUNCTION(qup4_se4_l3), + MSM_PIN_FUNCTION(qup5_se0), + MSM_PIN_FUNCTION(rng_rosc), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc2_clk), + MSM_PIN_FUNCTION(sdc2_cmd), + MSM_PIN_FUNCTION(sdc2_data), + MSM_PIN_FUNCTION(sdc2_rclk), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sys_throttle), + MSM_PIN_FUNCTION(tb_trig_sdc), + MSM_PIN_FUNCTION(tmess_rng), + MSM_PIN_FUNCTION(tsense_clm), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim0), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), +}; + +static const struct msm_pingroup maili_groups[] = { + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [8] = PINGROUP(8, qup3_se1, ibi_i3c, qup5_se0, ibi_i3c_qup5_se0, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup3_se1, ibi_i3c, qup5_se0, ibi_i3c_qup5_se0, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup3_se1, qup5_se0, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup3_se1, qup5_se0, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, qup5_se0, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, qup5_se0, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup3_se2, qup5_se0, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup3_se3, qup5_se0, _, vsense_trigger_mirnat, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup3_se3, qup5_se0, gcc_gp, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, wcn_sw, qup3_se3, _, gnss_adc, _, _, _, _, _, _, _), + [19] = PINGROUP(19, wcn_sw, qup3_se3, _, gnss_adc, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup3_se4, _, gnss_adc, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup3_se4, _, gnss_adc, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup3_se5, ibi_i3c, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup3_se5, ibi_i3c, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio), + [31] = PINGROUP(31, qup4_se1, _, _, _, _, _, _, _, _, _, egpio), + [32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup4_se2, tsense_pwm, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se4, tsense_pwm, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se4, uim1, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se2, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se2, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se2, _, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup1_se2, _, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se3, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se3, ddr_bist, phase_flag, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, i2s0, phase_flag, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, dp_hot, phase_flag, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [52] = PINGROUP(52, qup1_se5, _, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup1_se5, _, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se5, uim1, sdc2_rclk, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, uim1, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup1_se6, uim1, sdc2_clk, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup1_se6, sdc2_cmd, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup1_se6, tsense_pwm, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se6, usb_phy, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup3_se0, rng_rosc, tmess_rng, ibi_i3c, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qup3_se0, rng_rosc, tmess_rng, ibi_i3c, _, _, _, _, _, _, _), + [66] = PINGROUP(66, i2chub0_se0, qup3_se0, rng_rosc, tmess_rng, _, ddr_pxi, _, _, _, _, _), + [67] = PINGROUP(67, i2chub0_se0, qup3_se0, _, ddr_pxi, _, _, _, _, _, _, _), + [68] = PINGROUP(68, i2chub0_se2, _, ddr_pxi, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, i2chub0_se2, _, ddr_pxi, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, i2chub0_se3, uim1, _, _, ddr_pxi, _, _, _, _, _, _), + [71] = PINGROUP(71, i2chub0_se3, uim1, _, _, ddr_pxi, _, _, _, _, _, _), + [72] = PINGROUP(72, i2chub0_se4, uim1, qdss_cti, _, ddr_pxi, _, _, _, _, _, _), + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, ddr_pxi, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup1_se1, aoss_cti, sdc2_data, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, i2chub0_se1, _, atest_usb, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, atest_usb, _, _, _, _, _, _, _), + [80] = PINGROUP(80, sdc4_data, qspi, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, sdc4_data, qspi, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, sdc4_data, qdss_cti, qspi, qup3_se0, dbg_out_clk, _, _, _, _, _, _), + [83] = PINGROUP(83, sdc4_clk, qdss_cti, qspi_clk, qup3_se0, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qup4_se3_01, qup4_se3_23, rng_rosc, tmess_rng, i2s0, _, _, _, _, _, _), + [85] = PINGROUP(85, sd_write_protect, qup5_se0, ibi_i3c, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp, + _, _, _, _, _, _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, mdp_esync2, + gcc_gp, tsense_clm, tsense_pwm, _, _, _), + [88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _), + [89] = PINGROUP(89, qup5_se0, ibi_i3c, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, gcc_gp, tsense_clm, tsense_pwm, + _, _, _, _, _), + [98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, tsense_clm, tsense_pwm, + _, _, _, _, _, _), + [99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_esync1, mdp_esync0, qup5_se0, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, atest_usb, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, pcie0_clk_req_n, atest_usb, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, pll_bist_sync, atest_usb, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cci_i2c3, cci_timer, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c2, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c2, _, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, qup2_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, qup2_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, audio_ext_mclk, qup4_se3_01, qup4_se3_23, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [127] = PINGROUP(127, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [128] = PINGROUP(128, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [129] = PINGROUP(129, uim0, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), + [133] = PINGROUP(133, uim1, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, coex_uart1_rx, coex_espmi, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, coex_uart1_tx, coex_espmi, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, vfr, nav_gpio, tb_trig_sdc, qspi_cs, _, _, _, _, _, _), + [147] = PINGROUP(147, _, nav_gpio, sdc4_data, qspi, _, _, _, _, _, _, _), + [148] = PINGROUP(148, nav_gpio, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, nav_gpio, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qlink, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qlink, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qlink, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, wcn_sw, gcc_gp, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, wcn_sw, gcc_gp, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, cci_timer, cci_i2c3, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qup4_se4_01, qup4_se4_23, i2s0, phase_flag, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qup4_se4_01, qup4_se4_23, i2s0, phase_flag, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, qup1_se1, _, _, _, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, host2wlan_sol, _, _, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, _, _, _, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, _, _, _, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio), + [210] = PINGROUP(210, _, _, _, _, _, _, _, _, _, _, _), + [211] = PINGROUP(211, _, _, _, _, _, _, _, _, _, _, _), + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), + [214] = PINGROUP(214, qup5_se0, _, _, _, _, _, _, _, _, _, egpio), + [215] = PINGROUP(215, qup5_se0, _, _, _, _, _, _, _, _, _, egpio), + [216] = PINGROUP(216, _, _, _, _, _, _, _, _, _, _, egpio), + [217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio), + [218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio), + [219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _), + [220] = PINGROUP(220, pcie1_rst_n, _, _, _, _, _, _, _, _, _, _), + [221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [222] = PINGROUP(222, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [223] = PINGROUP(223, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [224] = PINGROUP(224, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [225] = PINGROUP(225, qup1_se0, i2s1, qdss_cti, phase_flag, _, _, _, _, _, _, _), + [226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000), + [227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6), + [228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3), + [229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map maili_pdc_map[] = { + { 0, 111 }, { 3, 119 }, { 4, 112 }, { 7, 113 }, { 8, 114 }, { 11, 115 }, + { 12, 121 }, { 15, 137 }, { 16, 122 }, { 17, 147 }, { 18, 149 }, { 19, 118 }, + { 23, 123 }, { 24, 124 }, { 27, 125 }, { 28, 131 }, { 31, 132 }, { 32, 133 }, + { 35, 107 }, { 36, 134 }, { 39, 135 }, { 43, 136 }, { 47, 160 }, { 48, 141 }, + { 51, 120 }, { 55, 110 }, { 57, 142 }, { 58, 143 }, { 59, 144 }, { 60, 145 }, + { 61, 151 }, { 63, 130 }, { 64, 116 }, { 65, 129 }, { 67, 138 }, { 68, 152 }, + { 69, 153 }, { 75, 157 }, { 77, 154 }, { 78, 155 }, { 79, 161 }, { 80, 162 }, + { 81, 163 }, { 82, 164 }, { 83, 171 }, { 84, 140 }, { 85, 165 }, { 86, 166 }, + { 87, 167 }, { 88, 168 }, { 95, 169 }, { 96, 170 }, { 97, 139 }, { 98, 156 }, + { 99, 117 }, { 100, 199 }, { 103, 173 }, { 104, 174 }, { 117, 201 }, { 120, 175 }, + { 123, 176 }, { 125, 177 }, { 129, 159 }, { 133, 106 }, { 144, 178 }, { 146, 179 }, + { 151, 180 }, { 152, 181 }, { 155, 128 }, { 158, 126 }, { 162, 148 }, { 164, 182 }, + { 165, 183 }, { 167, 184 }, { 168, 185 }, { 174, 186 }, { 177, 187 }, { 179, 188 }, + { 183, 189 }, { 184, 190 }, { 185, 191 }, { 186, 158 }, { 188, 150 }, { 202, 108 }, + { 203, 109 }, { 205, 146 }, { 209, 192 }, { 213, 127 }, { 215, 200 }, { 216, 193 }, + { 220, 172 }, { 221, 194 }, { 222, 195 }, { 223, 196 }, { 224, 197 }, { 225, 198 }, +}; + +static const struct msm_pinctrl_soc_data maili_tlmm = { + .pins = maili_pins, + .npins = ARRAY_SIZE(maili_pins), + .functions = maili_functions, + .nfunctions = ARRAY_SIZE(maili_functions), + .groups = maili_groups, + .ngroups = ARRAY_SIZE(maili_groups), + .ngpios = 227, + .wakeirq_map = maili_pdc_map, + .nwakeirq_map = ARRAY_SIZE(maili_pdc_map), + .egpio_func = 11, +}; + +static const struct of_device_id maili_tlmm_of_match[] = { + { .compatible = "qcom,maili-tlmm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, maili_tlmm_of_match); + +static int maili_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &maili_tlmm); +} + +static struct platform_driver maili_tlmm_driver = { + .driver = { + .name = "maili-tlmm", + .of_match_table = maili_tlmm_of_match, + }, + .probe = maili_tlmm_probe, +}; + +static int __init maili_tlmm_init(void) +{ + return platform_driver_register(&maili_tlmm_driver); +} +arch_initcall(maili_tlmm_init); + +static void __exit maili_tlmm_exit(void) +{ + platform_driver_unregister(&maili_tlmm_driver); +} +module_exit(maili_tlmm_exit); + +MODULE_DESCRIPTION("Qualcomm Maili TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c index 5794b0a11010..ce61eb415755 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9607.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -1050,6 +1050,7 @@ static const struct of_device_id mdm9607_pinctrl_of_match[] = { { .compatible = "qcom,mdm9607-tlmm", }, { } }; +MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match); static struct platform_driver mdm9607_pinctrl_driver = { .driver = { @@ -1073,4 +1074,3 @@ module_exit(mdm9607_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm mdm9607 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, mdm9607_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c index 729fe3d7e14e..f87e4d9a8f4f 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c @@ -439,6 +439,7 @@ static const struct of_device_id mdm9615_pinctrl_of_match[] = { { .compatible = "qcom,mdm9615-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match); static struct platform_driver mdm9615_pinctrl_driver = { .driver = { @@ -463,4 +464,3 @@ module_exit(mdm9615_pinctrl_exit); MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); MODULE_DESCRIPTION("Qualcomm MDM9615 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c index 3bf6fe0cf1bb..cb4934cd6f75 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -146,6 +148,33 @@ static const struct lpi_pingroup milos_groups[] = { LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _), }; +static const struct lpi_pingroup eliza_groups[] = { + LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 11, wsa_swr_clk, i2s2_clk, _, _), + LPI_PINGROUP(11, 11, wsa_swr_data, i2s2_ws, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, ext_mclk1_a, _), + LPI_PINGROUP(14, 11, swr_tx_data, ext_mclk1_d, _, _), + /* gpio15 - gpio18 do not really exist */ + LPI_PINGROUP(15, 11, _, _, _, _), + LPI_PINGROUP(16, 11, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, qca_swr_clk, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, qca_swr_data, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, dmic4_clk, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _), +}; + static const struct lpi_function milos_functions[] = { LPI_FUNCTION(gpio), LPI_FUNCTION(dmic1_clk), @@ -194,8 +223,21 @@ static const struct lpi_pinctrl_variant_data milos_lpi_data = { .nfunctions = ARRAY_SIZE(milos_functions), }; +static const struct lpi_pinctrl_variant_data eliza_lpi_data = { + .pins = milos_lpi_pins, + .npins = ARRAY_SIZE(milos_lpi_pins), + .groups = eliza_groups, + .ngroups = ARRAY_SIZE(eliza_groups), + .functions = milos_functions, + .nfunctions = ARRAY_SIZE(milos_functions), + .flags = LPI_FLAG_SLEW_RATE_SAME_REG, +}; + static const struct of_device_id lpi_pinctrl_of_match[] = { { + .compatible = "qcom,eliza-lpass-lpi-pinctrl", + .data = &eliza_lpi_data, + }, { .compatible = "qcom,milos-lpass-lpi-pinctrl", .data = &milos_lpi_data, }, @@ -203,10 +245,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-milos-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-milos.c b/drivers/pinctrl/qcom/pinctrl-milos.c index 74b5253257af..f5079a0ce0a3 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos.c +++ b/drivers/pinctrl/qcom/pinctrl-milos.c @@ -1310,6 +1310,7 @@ static const struct of_device_id milos_tlmm_of_match[] = { { .compatible = "qcom,milos-tlmm" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, milos_tlmm_of_match); static struct platform_driver milos_tlmm_driver = { .driver = { @@ -1333,4 +1334,3 @@ module_exit(milos_tlmm_exit); MODULE_DESCRIPTION("QTI Milos TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, milos_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 45b3a2763eb8..27f06bbc113c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -810,8 +810,7 @@ static const struct gpio_chip msm_gpio_template = { * Algorithm comes from Google's msmgpio driver. */ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, - const struct msm_pingroup *g, - struct irq_data *d) + const struct msm_pingroup *g) { int loop_limit = 100; unsigned val, val2, intstat; @@ -995,6 +994,16 @@ static void msm_gpio_irq_ack(struct irq_data *d) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) msm_gpio_update_dual_edge_parent(d); + + /* + * During early initialization of the IRQ hierarchy, + * irq_ack() is called by __irq_set_handler() before + * the parent IRQ chip has been set up. This is why + * we additionally need to check for d->parent_data->chip. + */ + + if (d->parent_data->chip && d->parent_data->chip->irq_ack) + irq_chip_ack_parent(d); return; } @@ -1005,17 +1014,15 @@ static void msm_gpio_irq_ack(struct irq_data *d) msm_ack_intr_status(pctrl, g); if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); + msm_gpio_update_dual_edge_pos(pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static void msm_gpio_irq_eoi(struct irq_data *d) { - d = d->parent_data; - - if (d) - d->chip->irq_eoi(d); + if (d->parent_data) + irq_chip_eoi_parent(d); } static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d, @@ -1037,8 +1044,6 @@ static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc, const struct msm_pingroup *g; int i; - bitmap_fill(valid_mask, ngpios); - for (i = 0; i < ngpios; i++) { g = &pctrl->soc->groups[i]; @@ -1069,7 +1074,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { clear_bit(d->hwirq, pctrl->dual_edge_irqs); - irq_set_handler_locked(d, handle_fasteoi_irq); + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(d, handle_fasteoi_irq); + else + irq_set_handler_locked(d, handle_fasteoi_ack_irq); return 0; } @@ -1179,13 +1187,13 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) msm_ack_intr_status(pctrl, g); if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); + msm_gpio_update_dual_edge_pos(pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(d, handle_level_irq); - else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + else if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(d, handle_edge_irq); return 0; @@ -1242,12 +1250,12 @@ static int msm_gpio_irq_reqres(struct irq_data *d) /* * If the wakeup_enable bit is present and marked as available for the * requested GPIO, it should be enabled when the GPIO is marked as - * wake irq in order to allow the interrupt event to be transfered to - * the PDC HW. + * wake irq in order to allow the interrupt event to be transferred to + * the PDC/MPM HW. * While the name implies only the wakeup event, it's also required for * the interrupt event. */ - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { + if (g->intr_wakeup_present_bit) { u32 intr_cfg; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -1275,7 +1283,7 @@ static void msm_gpio_irq_relres(struct irq_data *d) unsigned long flags; /* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqres() */ - if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { + if (g->intr_wakeup_present_bit) { u32 intr_cfg; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -1305,6 +1313,43 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d, return -EINVAL; } +static int msm_gpio_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool val) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + msm_writel_intr_status(val, pctrl, g); + + return 0; +} + +static int msm_gpio_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; + + if (which != IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + g = &pctrl->soc->groups[d->hwirq]; + *val = msm_readl_intr_status(pctrl, g); + + return 0; +} + static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -1393,6 +1438,8 @@ static const struct irq_chip msm_gpio_irq_chip = { .irq_request_resources = msm_gpio_irq_reqres, .irq_release_resources = msm_gpio_irq_relres, .irq_set_affinity = msm_gpio_irq_set_affinity, + .irq_set_irqchip_state = msm_gpio_irq_set_irqchip_state, + .irq_get_irqchip_state = msm_gpio_irq_get_irqchip_state, .irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity, .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -1593,11 +1640,11 @@ int msm_pinctrl_probe(struct platform_device *pdev, pctrl->desc.pins = pctrl->soc->pins; pctrl->desc.npins = pctrl->soc->npins; - pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); - if (IS_ERR(pctrl->pctrl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pctrl->pctrl); - } + ret = devm_pinctrl_register_and_init(&pdev->dev, &pctrl->desc, + pctrl, &pctrl->pctrl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Couldn't register pinctrl driver\n"); for (i = 0; i < soc_data->nfunctions; i++) { func = &soc_data->functions[i]; @@ -1607,6 +1654,11 @@ int msm_pinctrl_probe(struct platform_device *pdev, return ret; } + ret = pinctrl_enable(pctrl->pctrl); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Couldn't enable pinctrl driver\n"); + ret = msm_gpio_init(pctrl); if (ret) return ret; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index a4af279f748a..b94ba1a4177e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -24,6 +24,11 @@ struct pinctrl_pin_desc; fname##_groups, \ ARRAY_SIZE(fname##_groups)) +#define IPQ_GPIO_PIN_FUNCTION(fname) \ + [IPQ_MUX_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ + fname##_groups, \ + ARRAY_SIZE(fname##_groups)) + #define MSM_PIN_FUNCTION(fname) \ [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ fname##_groups, \ @@ -39,6 +44,11 @@ struct pinctrl_pin_desc; fname##_groups, \ ARRAY_SIZE(fname##_groups)) +#define QCA_GPIO_PIN_FUNCTION(fname) \ + [qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ + fname##_groups, \ + ARRAY_SIZE(fname##_groups)) + /** * struct msm_pingroup - Qualcomm pingroup definition * @grp: Generic data of the pin group (name and pins) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index d27b7599ea83..6f02e7c2499e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -645,6 +645,7 @@ static const struct of_device_id msm8226_pinctrl_of_match[] = { { .compatible = "qcom,msm8226-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match); static struct platform_driver msm8226_pinctrl_driver = { .driver = { @@ -669,4 +670,3 @@ module_exit(msm8226_pinctrl_exit); MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>"); MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c index 5ded00396cd9..5b28a1c21a88 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -974,6 +974,7 @@ static const struct of_device_id msm8660_pinctrl_of_match[] = { { .compatible = "qcom,msm8660-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match); static struct platform_driver msm8660_pinctrl_driver = { .driver = { @@ -998,4 +999,3 @@ module_exit(msm8660_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm MSM8660 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8660_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index 709c5d1d4d0a..d115035ff96a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -960,6 +960,7 @@ static const struct of_device_id msm8916_pinctrl_of_match[] = { { .compatible = "qcom,msm8916-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match); static struct platform_driver msm8916_pinctrl_driver = { .driver = { @@ -983,4 +984,3 @@ module_exit(msm8916_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm msm8916 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c index 02ea89f5feaa..d537fdaae148 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8953.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -1807,6 +1807,7 @@ static const struct of_device_id msm8953_pinctrl_of_match[] = { { .compatible = "qcom,msm8953-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match); static struct platform_driver msm8953_pinctrl_driver = { .driver = { @@ -1830,4 +1831,3 @@ module_exit(msm8953_pinctrl_exit); MODULE_DESCRIPTION("QTI msm8953 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8953_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c index 2fb15208aba0..a373150468ca 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -1239,6 +1239,7 @@ static const struct of_device_id msm8960_pinctrl_of_match[] = { { .compatible = "qcom,msm8960-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); static struct platform_driver msm8960_pinctrl_driver = { .driver = { @@ -1263,4 +1264,3 @@ module_exit(msm8960_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index 906a90778b97..bba3c87d8144 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -1087,6 +1087,7 @@ static const struct of_device_id msm8976_pinctrl_of_match[] = { { .compatible = "qcom,msm8976-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match); static struct platform_driver msm8976_pinctrl_driver = { .driver = { @@ -1110,4 +1111,3 @@ module_exit(msm8976_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm msm8976 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c index ecbe6b91d1da..fdaa67c5869f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8994.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c @@ -1334,6 +1334,7 @@ static const struct of_device_id msm8994_pinctrl_of_match[] = { { .compatible = "qcom,msm8994-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, msm8994_pinctrl_of_match); static struct platform_driver msm8994_pinctrl_driver = { .driver = { @@ -1357,4 +1358,3 @@ module_exit(msm8994_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm MSM8994 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8994_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c index 73b07a10a957..332b18a8fa9c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8996.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -1911,6 +1911,7 @@ static const struct of_device_id msm8996_pinctrl_of_match[] = { { .compatible = "qcom,msm8996-pinctrl", }, { } }; +MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match); static struct platform_driver msm8996_pinctrl_driver = { .driver = { @@ -1934,4 +1935,3 @@ module_exit(msm8996_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm msm8996 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8996_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index dcf11b79e562..0552c8212b29 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8998.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -1525,6 +1525,7 @@ static const struct of_device_id msm8998_pinctrl_of_match[] = { { .compatible = "qcom,msm8998-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match); static struct platform_driver msm8998_pinctrl_driver = { .driver = { @@ -1548,4 +1549,3 @@ module_exit(msm8998_pinctrl_exit); MODULE_DESCRIPTION("QTI msm8998 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index ff432ec5815a..9422629ec6ca 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -1073,6 +1073,7 @@ static const struct of_device_id msm8x74_pinctrl_of_match[] = { { .compatible = "qcom,msm8974-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); static struct platform_driver msm8x74_pinctrl_driver = { .driver = { @@ -1097,5 +1098,4 @@ module_exit(msm8x74_pinctrl_exit); MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>"); MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c new file mode 100644 index 000000000000..7f37f8e819ba --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-nord.c @@ -0,0 +1,1782 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc nord_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); + +static const unsigned int ufs_reset_pins[] = { 181 }; + +enum nord_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_aud_intfc0_clk, + msm_mux_aud_intfc0_data, + msm_mux_aud_intfc0_ws, + msm_mux_aud_intfc10_clk, + msm_mux_aud_intfc10_data, + msm_mux_aud_intfc10_ws, + msm_mux_aud_intfc1_clk, + msm_mux_aud_intfc1_data, + msm_mux_aud_intfc1_ws, + msm_mux_aud_intfc2_clk, + msm_mux_aud_intfc2_data, + msm_mux_aud_intfc2_ws, + msm_mux_aud_intfc3_clk, + msm_mux_aud_intfc3_data, + msm_mux_aud_intfc3_ws, + msm_mux_aud_intfc4_clk, + msm_mux_aud_intfc4_data, + msm_mux_aud_intfc4_ws, + msm_mux_aud_intfc5_clk, + msm_mux_aud_intfc5_data, + msm_mux_aud_intfc5_ws, + msm_mux_aud_intfc6_clk, + msm_mux_aud_intfc6_data, + msm_mux_aud_intfc6_ws, + msm_mux_aud_intfc7_clk, + msm_mux_aud_intfc7_data, + msm_mux_aud_intfc7_ws, + msm_mux_aud_intfc8_clk, + msm_mux_aud_intfc8_data, + msm_mux_aud_intfc8_ws, + msm_mux_aud_intfc9_clk, + msm_mux_aud_intfc9_data, + msm_mux_aud_intfc9_ws, + msm_mux_aud_mclk0_mira, + msm_mux_aud_mclk0_mirb, + msm_mux_aud_mclk1_mira, + msm_mux_aud_mclk1_mirb, + msm_mux_aud_mclk2_mira, + msm_mux_aud_mclk2_mirb, + msm_mux_aud_refclk0, + msm_mux_aud_refclk1, + msm_mux_bist_done, + msm_mux_ccu_async_in, + msm_mux_ccu_i2c_scl, + msm_mux_ccu_i2c_sda, + msm_mux_ccu_timer, + msm_mux_clink_debug, + msm_mux_dbg_out, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi, + msm_mux_dp_rx0, + msm_mux_dp_rx00, + msm_mux_dp_rx01, + msm_mux_dp_rx0_mute, + msm_mux_dp_rx1, + msm_mux_dp_rx10, + msm_mux_dp_rx11, + msm_mux_dp_rx1_mute, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_hot, + msm_mux_edp1_lcd, + msm_mux_edp2_hot, + msm_mux_edp2_lcd, + msm_mux_edp3_hot, + msm_mux_edp3_lcd, + msm_mux_emac0_mcg, + msm_mux_emac0_mdc, + msm_mux_emac0_mdio, + msm_mux_emac0_ptp, + msm_mux_emac1_mcg, + msm_mux_emac1_mdc, + msm_mux_emac1_mdio, + msm_mux_emac1_ptp, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_gcc_gp4_clk, + msm_mux_gcc_gp5_clk, + msm_mux_gcc_gp6_clk, + msm_mux_gcc_gp7_clk, + msm_mux_gcc_gp8_clk, + msm_mux_jitter_bist, + msm_mux_lbist_pass, + msm_mux_mbist_pass, + msm_mux_mdp0_vsync_out, + msm_mux_mdp1_vsync_out, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie2_clk_req_n, + msm_mux_pcie3_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_pwrbrk_i_n, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qspi, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2_01, + msm_mux_qup1_se2_23, + msm_mux_qup1_se3_01, + msm_mux_qup1_se3_23, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup3_se0_mira, + msm_mux_qup3_se0_mirb, + msm_mux_sailss_ospi, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_smb_alert, + msm_mux_smb_alert_n, + msm_mux_smb_clk, + msm_mux_smb_dat, + msm_mux_tb_trig_sdc4, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tsc_timer, + msm_mux_tsense_pwm, + msm_mux_usb0_hs, + msm_mux_usb0_phy_ps, + msm_mux_usb1_hs, + msm_mux_usb1_phy_ps, + msm_mux_usb2_hs, + msm_mux_usxgmii0_phy, + msm_mux_usxgmii1_phy, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", +}; + +static const char *const aoss_cti_groups[] = { + "gpio83", + "gpio84", + "gpio85", + "gpio86", +}; + +static const char *const atest_char_groups[] = { + "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", +}; + +static const char *const atest_usb20_groups[] = { + "gpio126", + "gpio128", + "gpio130", +}; + +static const char *const atest_usb21_groups[] = { + "gpio127", + "gpio129", + "gpio131", +}; + +static const char *const aud_intfc0_clk_groups[] = { + "gpio57", +}; + +static const char *const aud_intfc0_data_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", "gpio66", +}; + +static const char *const aud_intfc0_ws_groups[] = { + "gpio58", +}; + +static const char *const aud_intfc10_clk_groups[] = { + "gpio61", +}; + +static const char *const aud_intfc10_data_groups[] = { + "gpio81", "gpio82", +}; + +static const char *const aud_intfc10_ws_groups[] = { + "gpio62", +}; + +static const char *const aud_intfc1_clk_groups[] = { + "gpio67", +}; + +static const char *const aud_intfc1_data_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", +}; + +static const char *const aud_intfc1_ws_groups[] = { + "gpio68", +}; + +static const char *const aud_intfc2_clk_groups[] = { + "gpio77", +}; + +static const char *const aud_intfc2_data_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", +}; + +static const char *const aud_intfc2_ws_groups[] = { + "gpio78", +}; + +static const char *const aud_intfc3_clk_groups[] = { + "gpio83", +}; + +static const char *const aud_intfc3_data_groups[] = { + "gpio85", "gpio86", +}; + +static const char *const aud_intfc3_ws_groups[] = { + "gpio84", +}; + +static const char *const aud_intfc4_clk_groups[] = { + "gpio87", +}; + +static const char *const aud_intfc4_data_groups[] = { + "gpio89", "gpio90", +}; + +static const char *const aud_intfc4_ws_groups[] = { + "gpio88", +}; + +static const char *const aud_intfc5_clk_groups[] = { + "gpio91", +}; + +static const char *const aud_intfc5_data_groups[] = { + "gpio93", "gpio94", +}; + +static const char *const aud_intfc5_ws_groups[] = { + "gpio92", +}; + +static const char *const aud_intfc6_clk_groups[] = { + "gpio95", +}; + +static const char *const aud_intfc6_data_groups[] = { + "gpio97", "gpio98", +}; + +static const char *const aud_intfc6_ws_groups[] = { + "gpio96", +}; + +static const char *const aud_intfc7_clk_groups[] = { + "gpio63", +}; + +static const char *const aud_intfc7_data_groups[] = { + "gpio65", "gpio66", +}; + +static const char *const aud_intfc7_ws_groups[] = { + "gpio64", +}; + +static const char *const aud_intfc8_clk_groups[] = { + "gpio73", +}; + +static const char *const aud_intfc8_data_groups[] = { + "gpio75", "gpio76", +}; + +static const char *const aud_intfc8_ws_groups[] = { + "gpio74", +}; + +static const char *const aud_intfc9_clk_groups[] = { + "gpio70", +}; + +static const char *const aud_intfc9_data_groups[] = { + "gpio72", +}; + +static const char *const aud_intfc9_ws_groups[] = { + "gpio71", +}; + +static const char *const aud_mclk0_mira_groups[] = { + "gpio99", +}; + +static const char *const aud_mclk0_mirb_groups[] = { + "gpio86", +}; + +static const char *const aud_mclk1_mira_groups[] = { + "gpio100", +}; + +static const char *const aud_mclk1_mirb_groups[] = { + "gpio90", +}; + +static const char *const aud_mclk2_mira_groups[] = { + "gpio101", +}; + +static const char *const aud_mclk2_mirb_groups[] = { + "gpio94", +}; + +static const char *const aud_refclk0_groups[] = { + "gpio100", +}; + +static const char *const aud_refclk1_groups[] = { + "gpio101", +}; + +static const char *const bist_done_groups[] = { + "gpio168", +}; + +static const char *const ccu_async_in_groups[] = { + "gpio45", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", +}; + +static const char *const ccu_i2c_scl_groups[] = { + "gpio16", "gpio18", "gpio20", "gpio22", "gpio24", + "gpio114", "gpio116", "gpio126", "gpio130", "gpio132", +}; + +static const char *const ccu_i2c_sda_groups[] = { + "gpio15", "gpio17", "gpio19", "gpio21", "gpio23", + "gpio113", "gpio115", "gpio125", "gpio129", "gpio131", +}; + +static const char *const ccu_timer_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", + "gpio31", "gpio32", "gpio33", "gpio34", "gpio143", "gpio144", + "gpio150", "gpio151", "gpio152", "gpio153", +}; + +static const char *const clink_debug_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio51", + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const dbg_out_groups[] = { + "gpio113", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio165", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio37", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio39", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio36", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio38", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio99", "gpio100", "gpio109", "gpio110", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio126", "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", + "gpio136", "gpio137", "gpio138", "gpio139", "gpio162", "gpio163", + "gpio164", "gpio165", +}; + +static const char *const dp_rx0_groups[] = { + "gpio55", "gpio83", "gpio84", "gpio85", "gpio86", + "gpio88", "gpio89", "gpio137", "gpio138", +}; + +static const char *const dp_rx00_groups[] = { + "gpio99", +}; + +static const char *const dp_rx01_groups[] = { + "gpio100", +}; + +static const char *const dp_rx0_mute_groups[] = { + "gpio35", +}; + +static const char *const dp_rx1_groups[] = { + "gpio56", "gpio92", "gpio93", "gpio95", "gpio96", + "gpio97", "gpio98", "gpio158", "gpio159", +}; + +static const char *const dp_rx10_groups[] = { + "gpio121", +}; + +static const char *const dp_rx11_groups[] = { + "gpio122", +}; + +static const char *const dp_rx1_mute_groups[] = { + "gpio36", +}; + +static const char *const edp0_hot_groups[] = { + "gpio51", +}; + +static const char *const edp0_lcd_groups[] = { + "gpio47", +}; + +static const char *const edp1_hot_groups[] = { + "gpio52", +}; + +static const char *const edp1_lcd_groups[] = { + "gpio48", +}; + +static const char *const edp2_hot_groups[] = { + "gpio53", +}; + +static const char *const edp2_lcd_groups[] = { + "gpio49", +}; + +static const char *const edp3_hot_groups[] = { + "gpio54", +}; + +static const char *const edp3_lcd_groups[] = { + "gpio50", +}; + +static const char *const emac0_mcg_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const emac0_mdc_groups[] = { + "gpio47", +}; + +static const char *const emac0_mdio_groups[] = { + "gpio48", +}; + +static const char *const emac0_ptp_groups[] = { + "gpio133", "gpio134", "gpio135", "gpio136", + "gpio139", "gpio140", "gpio141", "gpio142", +}; + +static const char *const emac1_mcg_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const emac1_mdc_groups[] = { + "gpio49", +}; + +static const char *const emac1_mdio_groups[] = { + "gpio50", +}; + +static const char *const emac1_ptp_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", + "gpio41", "gpio42", "gpio43", "gpio44", +}; + +static const char *const gcc_gp1_clk_groups[] = { + "gpio51", +}; + +static const char *const gcc_gp2_clk_groups[] = { + "gpio52", +}; + +static const char *const gcc_gp3_clk_groups[] = { + "gpio42", +}; + +static const char *const gcc_gp4_clk_groups[] = { + "gpio43", +}; + +static const char *const gcc_gp5_clk_groups[] = { + "gpio105", +}; + +static const char *const gcc_gp6_clk_groups[] = { + "gpio106", +}; + +static const char *const gcc_gp7_clk_groups[] = { + "gpio13", +}; + +static const char *const gcc_gp8_clk_groups[] = { + "gpio14", +}; + +static const char *const jitter_bist_groups[] = { + "gpio123", + "gpio138", +}; + +static const char *const lbist_pass_groups[] = { + "gpio121", +}; + +static const char *const mbist_pass_groups[] = { + "gpio122", +}; + +static const char *const mdp0_vsync_out_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116", "gpio121", "gpio122", + "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", +}; + +static const char *const mdp1_vsync_out_groups[] = { + "gpio123", "gpio124", "gpio125", "gpio126", "gpio129", "gpio130", + "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio109", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio110", +}; + +static const char *const mdp_vsync_s_groups[] = { + "gpio144", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio1", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio4", +}; + +static const char *const pcie2_clk_req_n_groups[] = { + "gpio7", +}; + +static const char *const pcie3_clk_req_n_groups[] = { + "gpio10", +}; + +static const char *const phase_flag_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", + "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio98", "gpio101", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio176", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio100", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio117", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio118", +}; + +static const char *const pwrbrk_i_n_groups[] = { + "gpio167", +}; + +static const char *const qdss_cti_groups[] = { + "gpio41", "gpio42", "gpio110", "gpio138", + "gpio142", "gpio144", "gpio162", "gpio163", +}; + +static const char *const qdss_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", + "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio108", +}; + +static const char *const qspi_groups[] = { + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", +}; + +static const char *const qup0_se0_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; + +static const char *const qup0_se1_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", +}; + +static const char *const qup0_se2_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116", +}; + +static const char *const qup0_se3_groups[] = { + "gpio113", "gpio114", "gpio115", "gpio116", +}; + +static const char *const qup0_se4_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qup0_se5_groups[] = { + "gpio109", "gpio110", "gpio121", "gpio122", +}; + +static const char *const qup1_se0_groups[] = { + "gpio123", "gpio124", "gpio125", "gpio126", +}; + +static const char *const qup1_se1_groups[] = { + "gpio123", "gpio124", "gpio125", "gpio126", +}; + +static const char *const qup1_se2_01_groups[] = { + "gpio127", "gpio128", +}; + +static const char *const qup1_se2_23_groups[] = { + "gpio127", "gpio128", +}; + +static const char *const qup1_se3_01_groups[] = { + "gpio129", "gpio130", +}; + +static const char *const qup1_se3_23_groups[] = { + "gpio129", "gpio130", +}; + +static const char *const qup1_se4_groups[] = { + "gpio131", "gpio132", "gpio137", "gpio138", +}; + +static const char *const qup1_se5_groups[] = { + "gpio133", "gpio134", "gpio135", "gpio136", +}; + +static const char *const qup1_se6_groups[] = { + "gpio131", "gpio132", "gpio137", "gpio138", +}; + +static const char *const qup2_se0_groups[] = { + "gpio139", "gpio140", "gpio141", "gpio142", +}; + +static const char *const qup2_se1_groups[] = { + "gpio143", "gpio144", "gpio154", "gpio155", +}; + +static const char *const qup2_se2_groups[] = { + "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", +}; + +static const char *const qup2_se3_groups[] = { + "gpio150", "gpio151", "gpio152", "gpio153", +}; + +static const char *const qup2_se4_groups[] = { + "gpio143", "gpio144", "gpio150", "gpio151", + "gpio152", "gpio154", "gpio155", +}; + +static const char *const qup2_se5_groups[] = { + "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char *const qup2_se6_groups[] = { + "gpio156", "gpio157", "gpio158", "gpio159", +}; + +static const char *const qup3_se0_mira_groups[] = { + "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", +}; + +static const char *const qup3_se0_mirb_groups[] = { + "gpio102", "gpio103", +}; + +static const char *const sailss_ospi_groups[] = { + "gpio164", + "gpio165", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio175", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio174", +}; + +static const char *const sdc4_data_groups[] = { + "gpio170", + "gpio171", + "gpio172", + "gpio173", +}; + +static const char *const smb_alert_groups[] = { + "gpio110", +}; + +static const char *const smb_alert_n_groups[] = { + "gpio109", +}; + +static const char *const smb_clk_groups[] = { + "gpio112", +}; + +static const char *const smb_dat_groups[] = { + "gpio111", +}; + +static const char *const tb_trig_sdc4_groups[] = { + "gpio169", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio94", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio95", +}; + +static const char *const tsc_timer_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", +}; + +static const char *const usb0_hs_groups[] = { + "gpio12", +}; + +static const char *const usb0_phy_ps_groups[] = { + "gpio164", +}; + +static const char *const usb1_hs_groups[] = { + "gpio13", +}; + +static const char *const usb1_phy_ps_groups[] = { + "gpio165", +}; + +static const char *const usb2_hs_groups[] = { + "gpio14", +}; + +static const char *const usxgmii0_phy_groups[] = { + "gpio45", +}; + +static const char *const usxgmii1_phy_groups[] = { + "gpio46", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio132", +}; + +static const char *const wcn_sw_groups[] = { + "gpio161", +}; + +static const char *const wcn_sw_ctrl_groups[] = { + "gpio160", +}; + +static const struct pinfunction nord_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(aud_intfc0_clk), + MSM_PIN_FUNCTION(aud_intfc0_data), + MSM_PIN_FUNCTION(aud_intfc0_ws), + MSM_PIN_FUNCTION(aud_intfc10_clk), + MSM_PIN_FUNCTION(aud_intfc10_data), + MSM_PIN_FUNCTION(aud_intfc10_ws), + MSM_PIN_FUNCTION(aud_intfc1_clk), + MSM_PIN_FUNCTION(aud_intfc1_data), + MSM_PIN_FUNCTION(aud_intfc1_ws), + MSM_PIN_FUNCTION(aud_intfc2_clk), + MSM_PIN_FUNCTION(aud_intfc2_data), + MSM_PIN_FUNCTION(aud_intfc2_ws), + MSM_PIN_FUNCTION(aud_intfc3_clk), + MSM_PIN_FUNCTION(aud_intfc3_data), + MSM_PIN_FUNCTION(aud_intfc3_ws), + MSM_PIN_FUNCTION(aud_intfc4_clk), + MSM_PIN_FUNCTION(aud_intfc4_data), + MSM_PIN_FUNCTION(aud_intfc4_ws), + MSM_PIN_FUNCTION(aud_intfc5_clk), + MSM_PIN_FUNCTION(aud_intfc5_data), + MSM_PIN_FUNCTION(aud_intfc5_ws), + MSM_PIN_FUNCTION(aud_intfc6_clk), + MSM_PIN_FUNCTION(aud_intfc6_data), + MSM_PIN_FUNCTION(aud_intfc6_ws), + MSM_PIN_FUNCTION(aud_intfc7_clk), + MSM_PIN_FUNCTION(aud_intfc7_data), + MSM_PIN_FUNCTION(aud_intfc7_ws), + MSM_PIN_FUNCTION(aud_intfc8_clk), + MSM_PIN_FUNCTION(aud_intfc8_data), + MSM_PIN_FUNCTION(aud_intfc8_ws), + MSM_PIN_FUNCTION(aud_intfc9_clk), + MSM_PIN_FUNCTION(aud_intfc9_data), + MSM_PIN_FUNCTION(aud_intfc9_ws), + MSM_PIN_FUNCTION(aud_mclk0_mira), + MSM_PIN_FUNCTION(aud_mclk0_mirb), + MSM_PIN_FUNCTION(aud_mclk1_mira), + MSM_PIN_FUNCTION(aud_mclk1_mirb), + MSM_PIN_FUNCTION(aud_mclk2_mira), + MSM_PIN_FUNCTION(aud_mclk2_mirb), + MSM_PIN_FUNCTION(aud_refclk0), + MSM_PIN_FUNCTION(aud_refclk1), + MSM_PIN_FUNCTION(bist_done), + MSM_PIN_FUNCTION(ccu_async_in), + MSM_PIN_FUNCTION(ccu_i2c_scl), + MSM_PIN_FUNCTION(ccu_i2c_sda), + MSM_PIN_FUNCTION(ccu_timer), + MSM_PIN_FUNCTION(clink_debug), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_rx0), + MSM_PIN_FUNCTION(dp_rx00), + MSM_PIN_FUNCTION(dp_rx01), + MSM_PIN_FUNCTION(dp_rx0_mute), + MSM_PIN_FUNCTION(dp_rx1), + MSM_PIN_FUNCTION(dp_rx10), + MSM_PIN_FUNCTION(dp_rx11), + MSM_PIN_FUNCTION(dp_rx1_mute), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_hot), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(edp2_hot), + MSM_PIN_FUNCTION(edp2_lcd), + MSM_PIN_FUNCTION(edp3_hot), + MSM_PIN_FUNCTION(edp3_lcd), + MSM_PIN_FUNCTION(emac0_mcg), + MSM_PIN_FUNCTION(emac0_mdc), + MSM_PIN_FUNCTION(emac0_mdio), + MSM_PIN_FUNCTION(emac0_ptp), + MSM_PIN_FUNCTION(emac1_mcg), + MSM_PIN_FUNCTION(emac1_mdc), + MSM_PIN_FUNCTION(emac1_mdio), + MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(gcc_gp4_clk), + MSM_PIN_FUNCTION(gcc_gp5_clk), + MSM_PIN_FUNCTION(gcc_gp6_clk), + MSM_PIN_FUNCTION(gcc_gp7_clk), + MSM_PIN_FUNCTION(gcc_gp8_clk), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lbist_pass), + MSM_PIN_FUNCTION(mbist_pass), + MSM_PIN_FUNCTION(mdp0_vsync_out), + MSM_PIN_FUNCTION(mdp1_vsync_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(pcie3_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(pwrbrk_i_n), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2_01), + MSM_PIN_FUNCTION(qup1_se2_23), + MSM_PIN_FUNCTION(qup1_se3_01), + MSM_PIN_FUNCTION(qup1_se3_23), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup3_se0_mira), + MSM_PIN_FUNCTION(qup3_se0_mirb), + MSM_PIN_FUNCTION(sailss_ospi), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(smb_alert), + MSM_PIN_FUNCTION(smb_alert_n), + MSM_PIN_FUNCTION(smb_clk), + MSM_PIN_FUNCTION(smb_dat), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tsc_timer), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(usb1_hs), + MSM_PIN_FUNCTION(usb1_phy_ps), + MSM_PIN_FUNCTION(usb2_hs), + MSM_PIN_FUNCTION(usxgmii0_phy), + MSM_PIN_FUNCTION(usxgmii1_phy), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup nord_groups[] = { + [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, _, _, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, _, _, _, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, pcie2_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, _, _, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, _, _, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, pcie3_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, _, _, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, usb0_hs, clink_debug, _, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, usb1_hs, clink_debug, gcc_gp7_clk, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, usb2_hs, clink_debug, gcc_gp8_clk, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, ccu_i2c_sda, _, _, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, ccu_i2c_scl, _, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, ccu_timer, tsc_timer, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, dp_rx0_mute, _, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, dp_rx1_mute, ddr_bist_start, _, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, emac1_ptp, ddr_bist_complete, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, emac1_ptp, ddr_bist_stop, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, emac1_ptp, ddr_bist_fail, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, emac1_ptp, _, _, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, emac1_ptp, qdss_cti, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, emac1_ptp, qdss_cti, gcc_gp3_clk, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, emac1_ptp, gcc_gp4_clk, tsense_pwm, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, emac1_ptp, tsense_pwm, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, usxgmii0_phy, ccu_async_in, tsense_pwm, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, usxgmii1_phy, tsense_pwm, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, emac0_mdc, edp0_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, emac0_mdio, edp1_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, emac1_mdc, edp2_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, emac1_mdio, edp3_lcd, tsense_pwm, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, edp0_hot, clink_debug, gcc_gp1_clk, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, edp1_hot, clink_debug, gcc_gp2_clk, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, edp2_hot, clink_debug, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, edp3_hot, clink_debug, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, dp_rx0, clink_debug, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, dp_rx1, _, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, aud_intfc0_clk, _, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, aud_intfc0_ws, _, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, aud_intfc0_data, _, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, aud_intfc0_data, _, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, aud_intfc0_data, aud_intfc10_clk, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, aud_intfc0_data, aud_intfc10_ws, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, aud_intfc0_data, aud_intfc7_clk, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, aud_intfc0_data, aud_intfc7_ws, _, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, aud_intfc1_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [68] = PINGROUP(68, aud_intfc1_ws, phase_flag, _, qdss, _, _, _, _, _, _, _), + [69] = PINGROUP(69, aud_intfc1_data, phase_flag, _, qdss, _, _, _, _, _, _, _), + [70] = PINGROUP(70, aud_intfc1_data, aud_intfc9_clk, phase_flag, + _, qdss, _, _, _, _, _, _), + [71] = PINGROUP(71, aud_intfc1_data, aud_intfc9_ws, phase_flag, + _, qdss, _, _, _, _, _, _), + [72] = PINGROUP(72, aud_intfc1_data, aud_intfc9_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [73] = PINGROUP(73, aud_intfc1_data, aud_intfc8_clk, phase_flag, + _, qdss, _, _, _, _, _, _), + [74] = PINGROUP(74, aud_intfc1_data, aud_intfc8_ws, phase_flag, + _, qdss, _, _, _, _, _, _), + [75] = PINGROUP(75, aud_intfc1_data, aud_intfc8_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [76] = PINGROUP(76, aud_intfc1_data, aud_intfc8_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [77] = PINGROUP(77, aud_intfc2_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [78] = PINGROUP(78, aud_intfc2_ws, phase_flag, _, qdss, _, _, _, _, _, _, _), + [79] = PINGROUP(79, aud_intfc2_data, phase_flag, _, qdss, _, _, _, _, _, _, _), + [80] = PINGROUP(80, aud_intfc2_data, phase_flag, _, _, qdss, _, _, _, _, _, _), + [81] = PINGROUP(81, aud_intfc2_data, aud_intfc10_data, phase_flag, + _, _, qdss, _, _, _, _, _), + [82] = PINGROUP(82, aud_intfc2_data, aud_intfc10_data, phase_flag, + _, qdss, _, _, _, _, _, _), + [83] = PINGROUP(83, aud_intfc3_clk, dp_rx0, aoss_cti, phase_flag, _, qdss, + _, _, _, _, _), + [84] = PINGROUP(84, aud_intfc3_ws, dp_rx0, aoss_cti, phase_flag, _, qdss, + _, _, _, _, _), + [85] = PINGROUP(85, aud_intfc3_data, dp_rx0, aoss_cti, phase_flag, + _, qdss, _, _, _, _, _), + [86] = PINGROUP(86, aud_intfc3_data, aud_mclk0_mirb, dp_rx0, aoss_cti, phase_flag, + _, qdss, _, _, _, _), + [87] = PINGROUP(87, aud_intfc4_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [88] = PINGROUP(88, aud_intfc4_ws, dp_rx0, phase_flag, _, qdss, _, _, _, _, _, _), + [89] = PINGROUP(89, aud_intfc4_data, dp_rx0, phase_flag, _, qdss, + _, _, _, _, _, _), + [90] = PINGROUP(90, aud_intfc4_data, aud_mclk1_mirb, phase_flag, + _, qdss, _, _, _, _, _, _), + [91] = PINGROUP(91, aud_intfc5_clk, phase_flag, _, qdss, _, _, _, _, _, _, _), + [92] = PINGROUP(92, aud_intfc5_ws, dp_rx1, phase_flag, _, qdss, _, _, _, _, _, _), + [93] = PINGROUP(93, aud_intfc5_data, dp_rx1, phase_flag, _, qdss, + _, _, _, _, _, _), + [94] = PINGROUP(94, aud_intfc5_data, aud_mclk2_mirb, phase_flag, tmess_prng0, + _, qdss, _, _, _, _, _), + [95] = PINGROUP(95, aud_intfc6_clk, dp_rx1, phase_flag, tmess_prng1, + _, qdss, _, _, _, _, _), + [96] = PINGROUP(96, aud_intfc6_ws, dp_rx1, phase_flag, _, qdss, + _, _, _, _, _, _), + [97] = PINGROUP(97, aud_intfc6_data, dp_rx1, qdss, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, aud_intfc6_data, dp_rx1, phase_flag, _, qdss, + _, _, _, _, _, _), + [99] = PINGROUP(99, aud_mclk0_mira, qdss, dp_rx00, ddr_pxi, _, _, _, _, _, _, _), + [100] = PINGROUP(100, aud_mclk1_mira, aud_refclk0, pll_clk_aux, + qdss, dp_rx01, ddr_pxi, _, _, _, _, _), + [101] = PINGROUP(101, aud_mclk2_mira, aud_refclk1, phase_flag, _, qdss, + _, _, _, _, _, _), + [102] = PINGROUP(102, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, qspi, qup3_se0_mira, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, qspi, qup3_se0_mira, gcc_gp5_clk, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, qspi, qup3_se0_mira, gcc_gp6_clk, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, qspi, qup3_se0_mira, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, qspi, qup3_se0_mira, qdss, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, qup0_se0, qup0_se1, qup0_se5, mdp_vsync_e, + smb_alert_n, _, ddr_pxi, _, _, _, _), + [110] = PINGROUP(110, qup0_se0, qup0_se1, qup0_se5, qdss_cti, + mdp_vsync_p, smb_alert, _, ddr_pxi, _, _, _), + [111] = PINGROUP(111, qup0_se1, qup0_se0, smb_dat, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, qup0_se1, qup0_se0, smb_clk, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, qup0_se2, qup0_se3, ccu_i2c_sda, mdp0_vsync_out, + dbg_out, ddr_pxi, _, _, _, _, _), + [114] = PINGROUP(114, qup0_se2, qup0_se3, ccu_i2c_scl, mdp0_vsync_out, + _, ddr_pxi, _, _, _, _, _), + [115] = PINGROUP(115, qup0_se3, qup0_se2, ccu_i2c_sda, mdp0_vsync_out, + _, ddr_pxi, _, _, _, _, _), + [116] = PINGROUP(116, qup0_se3, qup0_se2, ccu_i2c_scl, mdp0_vsync_out, + _, ddr_pxi, _, _, _, _, _), + [117] = PINGROUP(117, qup0_se4, prng_rosc0, _, ddr_pxi, _, _, _, _, _, _, _), + [118] = PINGROUP(118, qup0_se4, prng_rosc1, _, ddr_pxi, _, _, _, _, _, _, _), + [119] = PINGROUP(119, qup0_se4, _, ddr_pxi, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, qup0_se4, _, ddr_pxi, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, qup0_se5, lbist_pass, mdp0_vsync_out, _, dp_rx10, ddr_pxi, + _, _, _, _, _), + [122] = PINGROUP(122, qup0_se5, mbist_pass, mdp0_vsync_out, _, dp_rx11, ddr_pxi, + _, _, _, _, _), + [123] = PINGROUP(123, qup1_se0, qup1_se1, mdp1_vsync_out, jitter_bist, + _, _, _, _, _, _, _), + [124] = PINGROUP(124, qup1_se0, qup1_se1, mdp1_vsync_out, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, qup1_se1, qup1_se0, ccu_i2c_sda, mdp1_vsync_out, + _, _, _, _, _, _, _), + [126] = PINGROUP(126, qup1_se1, qup1_se0, ccu_i2c_scl, mdp1_vsync_out, + _, atest_usb20, ddr_pxi, _, _, _, _), + [127] = PINGROUP(127, qup1_se2_23, qup1_se2_01, _, atest_usb21, ddr_pxi, + _, _, _, _, _, _), + [128] = PINGROUP(128, qup1_se2_23, qup1_se2_01, _, atest_usb20, ddr_pxi, + _, _, _, _, _, _), + [129] = PINGROUP(129, qup1_se3_23, qup1_se3_01, ccu_i2c_sda, mdp1_vsync_out, + _, atest_usb21, ddr_pxi, _, _, _, _), + [130] = PINGROUP(130, qup1_se3_23, qup1_se3_01, ccu_i2c_scl, mdp1_vsync_out, + _, atest_usb20, ddr_pxi, _, _, _, _), + [131] = PINGROUP(131, qup1_se4, qup1_se6, ccu_i2c_sda, mdp1_vsync_out, + _, atest_usb21, ddr_pxi, _, _, _, _), + [132] = PINGROUP(132, qup1_se4, qup1_se6, ccu_i2c_scl, mdp1_vsync_out, + _, vsense_trigger_mirnat, ddr_pxi, _, _, _, _), + [133] = PINGROUP(133, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, + _, _, _, _, _, _), + [134] = PINGROUP(134, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, + _, _, _, _, _, _), + [135] = PINGROUP(135, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, + _, _, _, _, _, _), + [136] = PINGROUP(136, qup1_se5, emac0_ptp, _, ddr_pxi, _, _, _, _, _, _, _), + [137] = PINGROUP(137, qup1_se6, qup1_se4, dp_rx0, _, ddr_pxi, _, _, _, _, _, _), + [138] = PINGROUP(138, qup1_se6, qup1_se4, dp_rx0, qdss_cti, jitter_bist, ddr_pxi, + _, _, _, _, _), + [139] = PINGROUP(139, qup2_se0, emac0_ptp, mdp0_vsync_out, ddr_pxi, + _, _, _, _, _, _, _), + [140] = PINGROUP(140, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, qup2_se0, emac0_ptp, qdss_cti, mdp0_vsync_out, _, _, _, _, _, _, _), + [143] = PINGROUP(143, qup2_se1, qup2_se4, ccu_timer, mdp0_vsync_out, + _, _, _, _, _, _, _), + [144] = PINGROUP(144, qup2_se1, qup2_se4, ccu_timer, qdss_cti, mdp_vsync_s, + _, _, _, _, _, _), + [145] = PINGROUP(145, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qup2_se3, ccu_timer, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qup2_se4, qup2_se1, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, qup2_se4, qup2_se1, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qup2_se5, qup2_se6, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qup2_se5, qup2_se6, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, wcn_sw, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qdss_cti, _, ddr_pxi, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, qdss_cti, _, ddr_pxi, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, usb0_phy_ps, _, sailss_ospi, ddr_pxi, _, _, _, _, _, _, _), + [165] = PINGROUP(165, usb1_phy_ps, dbg_out_clk, sailss_ospi, ddr_pxi, + _, _, _, _, _, _, _), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, pwrbrk_i_n, _, _, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, bist_done, _, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, tb_trig_sdc4, _, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, sdc4_data, _, _, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, sdc4_cmd, _, _, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, sdc4_clk, _, _, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, ccu_async_in, pll_bist_sync, atest_char, + _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, ccu_async_in, atest_char, _, _, _, _, _, _, _, _, _), + [181] = UFS_RESET(ufs_reset, 0xbd004, 0xbe000), +}; + +static const struct msm_gpio_wakeirq_map nord_pdc_map[] = { + { 0, 67 }, { 1, 68 }, { 2, 82 }, { 3, 69 }, { 4, 70 }, + { 5, 83 }, { 6, 71 }, { 7, 72 }, { 8, 84 }, { 9, 73 }, + { 10, 119 }, { 11, 85 }, { 45, 107 }, { 46, 98 }, { 102, 77 }, + { 108, 78 }, { 110, 120 }, { 114, 80 }, { 116, 81 }, { 120, 117 }, + { 124, 108 }, { 126, 99 }, { 128, 100 }, { 132, 101 }, { 138, 87 }, + { 142, 88 }, { 144, 89 }, { 153, 90 }, { 157, 91 }, { 159, 118 }, + { 160, 110 }, { 161, 79 }, { 166, 109 }, { 168, 111 }, +}; + +static const struct msm_pinctrl_soc_data nord_tlmm = { + .pins = nord_pins, + .npins = ARRAY_SIZE(nord_pins), + .functions = nord_functions, + .nfunctions = ARRAY_SIZE(nord_functions), + .groups = nord_groups, + .ngroups = ARRAY_SIZE(nord_groups), + .ngpios = 182, + .wakeirq_map = nord_pdc_map, + .nwakeirq_map = ARRAY_SIZE(nord_pdc_map), + .egpio_func = 11, +}; + +static const struct of_device_id nord_tlmm_of_match[] = { + { .compatible = "qcom,nord-tlmm", .data = &nord_tlmm }, + {}, +}; + +static int nord_tlmm_probe(struct platform_device *pdev) +{ + const struct msm_pinctrl_soc_data *pinctrl_data; + struct device *dev = &pdev->dev; + + pinctrl_data = device_get_match_data(dev); + if (!pinctrl_data) + return -EINVAL; + + return msm_pinctrl_probe(pdev, &nord_tlmm); +} + +static struct platform_driver nord_tlmm_driver = { + .driver = { + .name = "nord-tlmm", + .of_match_table = nord_tlmm_of_match, + }, + .probe = nord_tlmm_probe, +}; + +static int __init nord_tlmm_init(void) +{ + return platform_driver_register(&nord_tlmm_driver); +} +arch_initcall(nord_tlmm_init); + +static void __exit nord_tlmm_exit(void) +{ + platform_driver_unregister(&nord_tlmm_driver); +} +module_exit(nord_tlmm_exit); + +MODULE_DESCRIPTION("QTI Nord TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, nord_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index 3b28ac498885..ffec2fd6412c 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -75,29 +75,6 @@ .intr_detection_width = -1, \ } -#define UFS_RESET(pg_name, offset) \ - { \ - .grp = PINCTRL_PINGROUP(#pg_name, \ - pg_name##_pins, \ - ARRAY_SIZE(pg_name##_pins)), \ - .ctl_reg = offset, \ - .io_reg = offset + 0x4, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = 3, \ - .drv_bit = 0, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = 0, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } static const struct pinctrl_pin_desc qcm2290_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), @@ -1124,6 +1101,7 @@ static const struct of_device_id qcm2290_pinctrl_of_match[] = { { .compatible = "qcom,qcm2290-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match); static struct platform_driver qcm2290_pinctrl_driver = { .driver = { @@ -1147,4 +1125,3 @@ module_exit(qcm2290_pinctrl_exit); MODULE_DESCRIPTION("QTI QCM2290 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, qcm2290_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 1048a7093b2e..01c0f0b2839a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -1635,6 +1635,7 @@ static const struct of_device_id qcs404_pinctrl_of_match[] = { { .compatible = "qcom,qcs404-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, qcs404_pinctrl_of_match); static struct platform_driver qcs404_pinctrl_driver = { .driver = { @@ -1658,4 +1659,3 @@ module_exit(qcs404_pinctrl_exit); MODULE_DESCRIPTION("Qualcomm QCS404 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, qcs404_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c index 0ed4332d989e..0e7df184122b 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs615.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c @@ -1040,11 +1040,11 @@ static const struct msm_pingroup qcs615_groups[] = { static const struct msm_gpio_wakeirq_map qcs615_pdc_map[] = { { 1, 45 }, { 3, 31 }, { 7, 55 }, { 9, 110 }, { 11, 34 }, { 13, 33 }, { 14, 35 }, { 17, 46 }, { 19, 48 }, { 21, 83 }, - { 22, 36 }, { 26, 38 }, { 35, 37 }, { 39, 125 }, { 41, 47 }, - { 47, 49 }, { 48, 51 }, { 50, 52 }, { 51, 123 }, { 55, 56 }, + { 22, 36 }, { 26, 38 }, { 35, 37 }, { 39, 118 }, { 41, 47 }, + { 47, 49 }, { 48, 51 }, { 50, 52 }, { 51, 116 }, { 55, 56 }, { 56, 57 }, { 57, 58 }, { 60, 60 }, { 71, 54 }, { 80, 73 }, { 81, 64 }, { 82, 50 }, { 83, 65 }, { 84, 92 }, { 85, 99 }, - { 86, 67 }, { 87, 84 }, { 88, 124 }, { 89, 122 }, { 90, 69 }, + { 86, 67 }, { 87, 84 }, { 88, 117 }, { 89, 115 }, { 90, 69 }, { 92, 88 }, { 93, 75 }, { 94, 91 }, { 95, 72 }, { 96, 82 }, { 97, 74 }, { 98, 95 }, { 99, 94 }, { 100, 100 }, { 101, 40 }, { 102, 93 }, { 103, 77 }, { 104, 78 }, { 105, 96 }, { 107, 97 }, @@ -1073,6 +1073,7 @@ static const struct of_device_id qcs615_tlmm_of_match[] = { }, {}, }; +MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match); static int qcs615_tlmm_probe(struct platform_device *pdev) { @@ -1101,4 +1102,3 @@ module_exit(qcs615_tlmm_exit); MODULE_DESCRIPTION("QTI QCS615 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c index 852cd36df6d5..9a904d809e11 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -100,12 +100,6 @@ .intr_detection_width = -1, \ } -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - #define QUP_I3C_6_MODE_OFFSET 0xaf000 #define QUP_I3C_7_MODE_OFFSET 0xb0000 #define QUP_I3C_13_MODE_OFFSET 0xb1000 diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c index 5125df7eb127..1ef77f82820c 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdu1000.c +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -75,36 +75,6 @@ .intr_detection_width = -1, \ } -#define UFS_RESET(pg_name, offset) \ - { \ - .grp = PINCTRL_PINGROUP(#pg_name, \ - pg_name##_pins, \ - ARRAY_SIZE(pg_name##_pins)), \ - .ctl_reg = offset, \ - .io_reg = offset + 0x4, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = 3, \ - .drv_bit = 0, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = 0, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - static const struct pinctrl_pin_desc qdu1000_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index e9a510d3583f..5dbaa50cbff0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -101,12 +101,6 @@ .intr_detection_width = -1, \ } -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - #define QUP_I3C_6_MODE_OFFSET 0xAF000 #define QUP_I3C_7_MODE_OFFSET 0xB0000 #define QUP_I3C_13_MODE_OFFSET 0xB1000 diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index 01cfcb416f33..a02a9a78a557 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -1148,6 +1148,7 @@ static const struct of_device_id sc7180_pinctrl_of_match[] = { { .compatible = "qcom,sc7180-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match); static struct platform_driver sc7180_pinctrl_driver = { .driver = { @@ -1172,4 +1173,3 @@ module_exit(sc7180_pinctrl_exit); MODULE_DESCRIPTION("QTI sc7180 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8..a61df10d46cb 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -129,20 +131,25 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sc7280-lpass-lpi-pinctrl", - .data = &sc7280_lpi_data, + .compatible = "qcom,sc7280-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, }, { - .compatible = "qcom,sm8350-lpass-lpi-pinctrl", - .data = &sc7280_lpi_data, + .compatible = "qcom,sm8350-lpass-lpi-pinctrl", + .data = &sc7280_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sc7280-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sc7280-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index f22fd56efd89..bb32a56649df 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -1494,6 +1494,7 @@ static const struct of_device_id sc7280_pinctrl_of_match[] = { { .compatible = "qcom,sc7280-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match); static struct platform_driver sc7280_pinctrl_driver = { .driver = { @@ -1518,4 +1519,3 @@ module_exit(sc7280_pinctrl_exit); MODULE_DESCRIPTION("QTI sc7280 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sc7280_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4..27c47710365e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -166,17 +168,22 @@ static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl", - .data = &sc8280xp_lpi_data, + .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl", + .data = &sc8280xp_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sc8280xp-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c index 4056b9fa32f8..e018bd11626c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -1881,16 +1881,17 @@ static const struct msm_gpio_wakeirq_map sc8280xp_pdc_map[] = { { 126, 200 }, { 127, 225 }, { 128, 262 }, { 129, 201 }, { 130, 209 }, { 131, 173 }, { 132, 202 }, { 136, 210 }, { 138, 171 }, { 139, 226 }, { 140, 227 }, { 142, 228 }, - { 144, 229 }, { 145, 230 }, { 146, 231 }, { 148, 232 }, - { 149, 233 }, { 150, 234 }, { 152, 235 }, { 154, 212 }, - { 157, 213 }, { 161, 219 }, { 170, 236 }, { 171, 221 }, - { 174, 222 }, { 175, 237 }, { 176, 223 }, { 177, 170 }, - { 180, 238 }, { 181, 239 }, { 182, 240 }, { 183, 241 }, - { 184, 242 }, { 185, 243 }, { 190, 178 }, { 193, 184 }, - { 196, 185 }, { 198, 186 }, { 200, 174 }, { 201, 175 }, - { 205, 176 }, { 206, 177 }, { 208, 187 }, { 210, 198 }, - { 211, 199 }, { 212, 204 }, { 215, 205 }, { 220, 188 }, - { 221, 194 }, { 223, 195 }, { 225, 196 }, { 227, 197 }, + { 143, 261 }, { 144, 229 }, { 145, 230 }, { 146, 231 }, + { 148, 232 }, { 149, 233 }, { 150, 234 }, { 151, 264 }, + { 152, 235 }, { 154, 212 }, { 157, 213 }, { 161, 219 }, + { 170, 236 }, { 171, 221 }, { 174, 222 }, { 175, 237 }, + { 176, 223 }, { 177, 170 }, { 180, 238 }, { 181, 239 }, + { 182, 240 }, { 183, 241 }, { 184, 242 }, { 185, 243 }, + { 190, 178 }, { 193, 184 }, { 196, 185 }, { 198, 186 }, + { 200, 174 }, { 201, 175 }, { 205, 176 }, { 206, 177 }, + { 208, 187 }, { 210, 198 }, { 211, 199 }, { 212, 204 }, + { 215, 205 }, { 220, 188 }, { 221, 194 }, { 223, 195 }, + { 225, 196 }, { 227, 197 }, }; static struct msm_pinctrl_soc_data sc8280xp_pinctrl = { diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c index 65411abfbfac..7b5aacaae7d7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -10,6 +10,8 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-lpass-lpi.h" @@ -145,10 +147,15 @@ static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm660_lpi_pinctrl_driver = { .driver = { .name = "qcom-sdm660-lpass-lpi-pinctrl", .of_match_table = sdm660_lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index ab0368653d30..c4a1ec90a341 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -1433,6 +1433,7 @@ static const struct of_device_id sdm660_pinctrl_of_match[] = { { .compatible = "qcom,sdm630-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); static struct platform_driver sdm660_pinctrl_driver = { .driver = { @@ -1456,4 +1457,3 @@ module_exit(sdm660_pinctrl_exit); MODULE_DESCRIPTION("QTI sdm660 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c index 858146c408d0..0a31f7ad2e0d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-lpass-lpi.h" @@ -151,10 +153,15 @@ static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver sdm670_lpi_pinctrl_driver = { .driver = { .name = "qcom-sdm670-lpass-lpi-pinctrl", .of_match_table = sdm670_lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index b5ed2311b70e..48fbe3623e17 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1339,6 +1339,7 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = { { .compatible = "qcom,sdm845-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match); static struct platform_driver sdm845_pinctrl_driver = { .driver = { @@ -1364,4 +1365,3 @@ module_exit(sdm845_pinctrl_exit); MODULE_DESCRIPTION("QTI sdm845 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c index 3e87f5927924..656a0726db92 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx55.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -981,6 +981,7 @@ static const struct of_device_id sdx55_pinctrl_of_match[] = { { .compatible = "qcom,sdx55-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); static struct platform_driver sdx55_pinctrl_driver = { .driver = { @@ -1004,4 +1005,3 @@ module_exit(sdx55_pinctrl_exit); MODULE_DESCRIPTION("QTI sdx55 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdx55_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c index 4e787341b2a2..dde8993ca9b1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx65.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -929,6 +929,7 @@ static const struct of_device_id sdx65_pinctrl_of_match[] = { { .compatible = "qcom,sdx65-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); static struct platform_driver sdx65_pinctrl_driver = { .driver = { @@ -952,4 +953,3 @@ module_exit(sdx65_pinctrl_exit); MODULE_DESCRIPTION("QTI sdx65 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c new file mode 100644 index 000000000000..55aec2f675e6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-shikra.c @@ -0,0 +1,1254 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_enable_bit = 7, \ + .intr_wakeup_present_bit = 6, \ + .intr_target_width = 4, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc shikra_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "SDC1_RCLK"), + PINCTRL_PIN(167, "SDC1_CLK"), + PINCTRL_PIN(168, "SDC1_CMD"), + PINCTRL_PIN(169, "SDC1_DATA"), + PINCTRL_PIN(170, "SDC2_CLK"), + PINCTRL_PIN(171, "SDC2_CMD"), + PINCTRL_PIN(172, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); + +static const unsigned int sdc1_rclk_pins[] = { 166 }; +static const unsigned int sdc1_clk_pins[] = { 167 }; +static const unsigned int sdc1_cmd_pins[] = { 168 }; +static const unsigned int sdc1_data_pins[] = { 169 }; +static const unsigned int sdc2_clk_pins[] = { 170 }; +static const unsigned int sdc2_cmd_pins[] = { 171 }; +static const unsigned int sdc2_data_pins[] = { 172 }; + +enum shikra_functions { + msm_mux_gpio, + msm_mux_agera_pll, + msm_mux_atest_bbrx, + msm_mux_atest_char, + msm_mux_atest_gpsadc, + msm_mux_atest_tsens, + msm_mux_atest_usb, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_cci_timer, + msm_mux_char_exec, + msm_mux_cri_trng, + msm_mux_dac_calib, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dmic, + msm_mux_emac_dll, + msm_mux_emac_mcg, + msm_mux_emac_phy, + msm_mux_emac0_ptp_aux, + msm_mux_emac0_ptp_pps, + msm_mux_emac1_ptp_aux, + msm_mux_emac1_ptp_pps, + msm_mux_ext_mclk, + msm_mux_gcc_gp, + msm_mux_gsm0_tx, + msm_mux_i2s0, + msm_mux_i2s1, + msm_mux_i2s2, + msm_mux_i2s3, + msm_mux_jitter_bist, + msm_mux_m_voc, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_out0, + msm_mux_mdp_vsync_out1, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_mpm_pwr, + msm_mux_mss_lte, + msm_mux_nav_gpio, + msm_mux_pa_indicator_or, + msm_mux_pbs_in, + msm_mux_pbs_out, + msm_mux_pcie0_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll, + msm_mux_prng_rosc, + msm_mux_pwm, + msm_mux_qdss_cti, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se1_01, + msm_mux_qup0_se1_23, + msm_mux_qup0_se2, + msm_mux_qup0_se3_01, + msm_mux_qup0_se3_23, + msm_mux_qup0_se4_01, + msm_mux_qup0_se4_23, + msm_mux_qup0_se5, + msm_mux_qup0_se6, + msm_mux_qup0_se7_01, + msm_mux_qup0_se7_23, + msm_mux_qup0_se8, + msm_mux_qup0_se9, + msm_mux_qup0_se9_01, + msm_mux_qup0_se9_23, + msm_mux_rgmii, + msm_mux_sd_write_protect, + msm_mux_sdc_cdc, + msm_mux_sdc_tb_trig, + msm_mux_ssbi_wtr, + msm_mux_swr0_rx, + msm_mux_swr0_tx, + msm_mux_tgu_ch_trigout, + msm_mux_tsc_async, + msm_mux_tsense_pwm, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_unused_adsp, + msm_mux_unused_gsm1, + msm_mux_usb0_phy_ps, + msm_mux_vfr, + msm_mux_vsense_trigger_mirnat, + msm_mux_wlan, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", +}; + +static const char *const agera_pll_groups[] = { + "gpio22", "gpio23", +}; + +static const char *const atest_bbrx_groups[] = { + "gpio58", "gpio59", +}; + +static const char *const atest_char_groups[] = { + "gpio56", "gpio57", "gpio54", "gpio55", "gpio62", +}; + +static const char *const atest_gpsadc_groups[] = { + "gpio60", "gpio96", +}; + +static const char *const atest_tsens_groups[] = { + "gpio1", "gpio2", +}; + +static const char *const atest_usb_groups[] = { + "gpio53", "gpio58", "gpio59", "gpio60", "gpio61", "gpio96", + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char *const cam_mclk_groups[] = { + "gpio34", "gpio35", "gpio96", "gpio98", +}; + +static const char *const cci_async_groups[] = { + "gpio39", +}; + +static const char *const cci_i2c0_groups[] = { + "gpio36", "gpio37", +}; + +static const char *const cci_i2c1_groups[] = { + "gpio41", "gpio42", +}; + +static const char *const cci_timer_groups[] = { + "gpio38", "gpio40", "gpio43", "gpio47", +}; + +static const char *const char_exec_groups[] = { + "gpio12", "gpio13", +}; + +static const char *const cri_trng_groups[] = { + "gpio6", "gpio7", "gpio20", +}; + +static const char *const dac_calib_groups[] = { + "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", + "gpio9", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", + "gpio19", "gpio63", "gpio64", "gpio66", "gpio68", "gpio69", + "gpio70", "gpio88", "gpio89", "gpio90", "gpio97", "gpio116", + "gpio117", "gpio118", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio61", +}; + +static const char *const ddr_bist_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char *const dmic_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char *const emac_dll_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; + +static const char *const emac_mcg_groups[] = { + "gpio28", "gpio29", "gpio40", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", +}; + +static const char *const emac_phy_groups[] = { + "gpio120", "gpio136", +}; + +static const char *const emac0_ptp_aux_groups[] = { + "gpio60", "gpio63", "gpio69", "gpio85", +}; + +static const char *const emac0_ptp_pps_groups[] = { + "gpio60", "gpio63", "gpio69", "gpio85", +}; + +static const char *const emac1_ptp_aux_groups[] = { + "gpio31", "gpio33", "gpio60", "gpio68", +}; + +static const char *const emac1_ptp_pps_groups[] = { + "gpio31", "gpio33", "gpio60", "gpio68", +}; + +static const char *const ext_mclk_groups[] = { + "gpio103", "gpio104", "gpio110", "gpio114", +}; + +static const char *const gcc_gp_groups[] = { + "gpio45", "gpio53", "gpio61", "gpio88", "gpio89", "gpio110", +}; + +static const char *const gsm0_tx_groups[] = { + "gpio75", +}; + +static const char *const i2s0_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", +}; + +static const char *const i2s1_groups[] = { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char *const i2s2_groups[] = { + "gpio100", "gpio101", "gpio102", "gpio103", +}; + +static const char *const i2s3_groups[] = { + "gpio111", "gpio112", "gpio113", "gpio114", +}; + +static const char *const jitter_bist_groups[] = { + "gpio96", "gpio99", +}; + +static const char *const m_voc_groups[] = { + "gpio0", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio94", +}; + +static const char *const mdp_vsync_out0_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_out1_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync_s_groups[] = { + "gpio95", +}; + +static const char *const mpm_pwr_groups[] = { + "gpio1", +}; + +static const char *const mss_lte_groups[] = { + "gpio115", "gpio116", +}; + +static const char *const nav_gpio_groups[] = { + "gpio53", "gpio58", "gpio63", "gpio71", "gpio91", "gpio92", + "gpio95", "gpio100", "gpio101", "gpio104", +}; + +static const char *const pa_indicator_or_groups[] = { + "gpio61", +}; + +static const char *const pbs_in_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", "gpio53", "gpio54", + "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", + "gpio61", "gpio62", "gpio63", "gpio74", +}; + +static const char *const pbs_out_groups[] = { + "gpio22", "gpio23", "gpio24", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio117", +}; + +static const char *const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio11", "gpio16", + "gpio17", "gpio28", "gpio29", "gpio30", "gpio31", "gpio48", + "gpio49", "gpio50", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio62", "gpio63", "gpio64", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio74", "gpio102", +}; + +static const char *const pll_groups[] = { + "gpio14", "gpio22", "gpio43", "gpio44", "gpio74", "gpio76", +}; + +static const char *const prng_rosc_groups[] = { + "gpio27", "gpio28", +}; + +static const char *const pwm_groups[] = { + "gpio32", "gpio40", "gpio45", "gpio53", "gpio54", "gpio55", + "gpio56", "gpio57", "gpio58", "gpio61", "gpio62", "gpio68", + "gpio77", "gpio79", "gpio80", "gpio87", "gpio102" +}; + +static const char *const qdss_cti_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio94", "gpio95", +}; + +static const char *const qup0_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup0_se1_groups[] = { + "gpio28", "gpio29", +}; + +static const char *const qup0_se1_01_groups[] = { + "gpio4", "gpio5", +}; + +static const char *const qup0_se1_23_groups[] = { + "gpio4", "gpio5", +}; + +static const char *const qup0_se2_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio30", "gpio31", +}; + +static const char *const qup0_se3_01_groups[] = { + "gpio10", "gpio11", +}; + +static const char *const qup0_se3_23_groups[] = { + "gpio10", "gpio11", +}; + +static const char *const qup0_se4_01_groups[] = { + "gpio12", "gpio13", +}; + +static const char *const qup0_se4_23_groups[] = { + "gpio12", "gpio13", +}; + +static const char *const qup0_se5_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char *const qup0_se6_groups[] = { + "gpio18", "gpio19", "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup0_se7_01_groups[] = { + "gpio20", "gpio21", +}; + +static const char *const qup0_se7_23_groups[] = { + "gpio20", "gpio21", +}; + +static const char *const qup0_se8_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char *const qup0_se9_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup0_se9_01_groups[] = { + "gpio26", "gpio27", +}; + +static const char *const qup0_se9_23_groups[] = { + "gpio26", "gpio27", +}; + +static const char *const rgmii_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio134", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio109", +}; + +static const char *const sdc_cdc_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", +}; + +static const char *const sdc_tb_trig_groups[] = { + "gpio32", "gpio33", +}; + +static const char *const ssbi_wtr_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char *const swr0_rx_groups[] = { + "gpio107", "gpio108", "gpio109", +}; + +static const char *const swr0_tx_groups[] = { + "gpio105", "gpio106", +}; + +static const char *const tgu_ch_trigout_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char *const tsc_async_groups[] = { + "gpio45", "gpio46", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio21", +}; + +static const char *const uim1_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; + +static const char *const uim2_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", +}; + +static const char *const unused_adsp_groups[] = { + "gpio35", +}; + +static const char *const unused_gsm1_groups[] = { + "gpio64", +}; + +static const char *const usb0_phy_ps_groups[] = { + "gpio90", +}; + +static const char *const vfr_groups[] = { + "gpio59", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio58", +}; + +static const char *const wlan_groups[] = { + "gpio14", "gpio15", +}; + +static const struct pinfunction shikra_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(agera_pll), + MSM_PIN_FUNCTION(atest_bbrx), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_gpsadc), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(char_exec), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dac_calib), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dmic), + MSM_PIN_FUNCTION(emac_dll), + MSM_PIN_FUNCTION(emac_mcg), + MSM_PIN_FUNCTION(emac_phy), + MSM_PIN_FUNCTION(emac0_ptp_aux), + MSM_PIN_FUNCTION(emac0_ptp_pps), + MSM_PIN_FUNCTION(emac1_ptp_aux), + MSM_PIN_FUNCTION(emac1_ptp_pps), + MSM_PIN_FUNCTION(ext_mclk), + MSM_PIN_FUNCTION(gcc_gp), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(i2s0), + MSM_PIN_FUNCTION(i2s1), + MSM_PIN_FUNCTION(i2s2), + MSM_PIN_FUNCTION(i2s3), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_out0), + MSM_PIN_FUNCTION(mdp_vsync_out1), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(mpm_pwr), + MSM_PIN_FUNCTION(mss_lte), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(pa_indicator_or), + MSM_PIN_FUNCTION(pbs_in), + MSM_PIN_FUNCTION(pbs_out), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwm), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se1_01), + MSM_PIN_FUNCTION(qup0_se1_23), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3_01), + MSM_PIN_FUNCTION(qup0_se3_23), + MSM_PIN_FUNCTION(qup0_se4_01), + MSM_PIN_FUNCTION(qup0_se4_23), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup0_se6), + MSM_PIN_FUNCTION(qup0_se7_01), + MSM_PIN_FUNCTION(qup0_se7_23), + MSM_PIN_FUNCTION(qup0_se8), + MSM_PIN_FUNCTION(qup0_se9), + MSM_PIN_FUNCTION(qup0_se9_01), + MSM_PIN_FUNCTION(qup0_se9_23), + MSM_PIN_FUNCTION(rgmii), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc_cdc), + MSM_PIN_FUNCTION(sdc_tb_trig), + MSM_PIN_FUNCTION(ssbi_wtr), + MSM_PIN_FUNCTION(swr0_rx), + MSM_PIN_FUNCTION(swr0_tx), + MSM_PIN_FUNCTION(tgu_ch_trigout), + MSM_PIN_FUNCTION(tsc_async), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(uim2), + MSM_PIN_FUNCTION(unused_adsp), + MSM_PIN_FUNCTION(unused_gsm1), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(vfr), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wlan), +}; + +static const struct msm_pingroup shikra_groups[] = { + [0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _), + [2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _), + [4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _, + _, _), + [5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _), + [6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), + [7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _), + [8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _), + [15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _), + [16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), + [17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _), + [18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti, + _, _, _, _), + [29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _), + [30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _), + [31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag, + qdss_cti, _, _, _, _), + [32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _), + [46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _), + [51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _), + [54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb, + vsense_trigger_mirnat, emac_dll, _, _), + [59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _), + [60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _, + pbs_in, atest_gpsadc, atest_usb, emac_dll, _), + [61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb, + emac_dll, _, _, _), + [62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _), + [63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag, + dac_calib, _, _, _), + [64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _, + _, _), + [69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib, + _, _, _, _), + [70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _), + [71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _), + [72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _), + [75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _, + _, _), + [97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _), + [99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _), + [102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _), + [103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _), + [111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _), + [166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0), + [167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6), + [168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3), + [169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0), + [170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6), + [171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3), + [172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = { + {1, 9 }, {2, 31 }, {5, 49 }, {6, 53 }, {9, 72 }, {10, 10 }, + {12, 22 }, {14, 26 }, {17, 29 }, {18, 24 }, {20, 32 }, {22, 33 }, + {25, 34 }, {27, 35 }, {28, 36 }, {29, 37 }, {30, 38 }, {31, 39 }, + {32, 40 }, {33, 41 }, {38, 42 }, {40, 43 }, {43, 44 }, {44, 45 }, + {45, 46 }, {46, 47 }, {47, 48 }, {48, 60 }, {50, 50 }, {51, 51 }, + {52, 61 }, {53, 62 }, {57, 52 }, {58, 63 }, {60, 54 }, {63, 64 }, + {73, 55 }, {74, 56 }, {75, 57 }, {77, 3 }, {80, 4 }, {84, 5 }, + {85, 67 }, {86, 69 }, {88, 70 }, {89, 71 }, {90, 73 }, {91, 74 }, + {92, 75 }, {93, 76 }, {94, 77 }, {95, 78 }, {97, 79 }, {99, 80 }, + {100, 11 }, {101, 13 }, {102, 14 }, {103, 15 }, {106, 16 }, {108, 17 }, + {112, 18 }, {116, 19 }, {117, 20 }, {119, 21 }, {120, 23 }, {136, 25 }, + {159, 27 }, {161, 28 }, +}; + +static const struct msm_pinctrl_soc_data shikra_tlmm = { + .pins = shikra_pins, + .npins = ARRAY_SIZE(shikra_pins), + .functions = shikra_functions, + .nfunctions = ARRAY_SIZE(shikra_functions), + .groups = shikra_groups, + .ngroups = ARRAY_SIZE(shikra_groups), + .ngpios = 166, + .wakeirq_map = shikra_mpm_map, + .nwakeirq_map = ARRAY_SIZE(shikra_mpm_map), +}; + +static int shikra_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &shikra_tlmm); +} + +static const struct of_device_id shikra_tlmm_of_match[] = { + { .compatible = "qcom,shikra-tlmm", .data = &shikra_tlmm }, + {}, +}; +MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match); + +static struct platform_driver shikra_tlmm_driver = { + .driver = { + .name = "shikra-tlmm", + .of_match_table = shikra_tlmm_of_match, + }, + .probe = shikra_tlmm_probe, +}; + +static int __init shikra_tlmm_init(void) +{ + return platform_driver_register(&shikra_tlmm_driver); +} +arch_initcall(shikra_tlmm_init); + +static void __exit shikra_tlmm_exit(void) +{ + platform_driver_unregister(&shikra_tlmm_driver); +} +module_exit(shikra_tlmm_exit); + +MODULE_DESCRIPTION("QTI Shikra TLMM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc..75bafa62426a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sm4250-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm4450.c b/drivers/pinctrl/qcom/pinctrl-sm4450.c index 83650f173b01..51a66a20dc66 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4450.c @@ -99,13 +99,6 @@ .intr_detection_width = -1, \ } -#define QUP_I3C(qup_mode, qup_offset) \ - { \ - .mode = qup_mode, \ - .offset = qup_offset, \ - } - - static const struct pinctrl_pin_desc sm4450_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2..05435ea6e17a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match[] = { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { .name = "qcom-sm6115-lpass-lpi-pinctrl", .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index 234451fbf47b..0099c474c442 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -47,6 +47,8 @@ enum { .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -374,6 +376,7 @@ enum sm6115_functions { msm_mux_ddr_pxi1, msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -451,6 +454,11 @@ static const char * const gpio_groups[] = { "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", }; +static const char * const egpio_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", +}; static const char * const ddr_bist_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", }; @@ -681,6 +689,7 @@ static const struct pinfunction sm6115_functions[] = { MSM_PIN_FUNCTION(ddr_pxi1), MSM_PIN_FUNCTION(ddr_pxi2), MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), @@ -839,21 +848,21 @@ static const struct msm_pingroup sm6115_groups[] = { [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), - [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _), - [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), - [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _), - [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _), - [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), - [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), - [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), - [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), - [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), - [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), - [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _), - [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), - [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _), - [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _), - [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, egpio), + [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, egpio), + [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, egpio), + [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, egpio), + [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), + [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), + [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio), + [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio), + [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, egpio), + [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, egpio), + [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, egpio), + [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), + [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, egpio), + [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, egpio), + [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, egpio), [113] = UFS_RESET(ufs_reset, 0x78000), [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0), [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6), @@ -886,6 +895,7 @@ static const struct msm_pinctrl_soc_data sm6115_tlmm = { .ntiles = ARRAY_SIZE(sm6115_tiles), .wakeirq_map = sm6115_mpm_map, .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map), + .egpio_func = 9, }; static int sm6115_tlmm_probe(struct platform_device *pdev) @@ -897,6 +907,7 @@ static const struct of_device_id sm6115_tlmm_of_match[] = { { .compatible = "qcom,sm6115-tlmm", }, { } }; +MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); static struct platform_driver sm6115_tlmm_driver = { .driver = { @@ -920,4 +931,3 @@ module_exit(sm6115_tlmm_exit); MODULE_DESCRIPTION("QTI sm6115 tlmm driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index 2cf9136860fc..7447ef9a4931 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -1256,6 +1256,7 @@ static const struct of_device_id sm6125_tlmm_of_match[] = { { .compatible = "qcom,sm6125-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match); static struct platform_driver sm6125_tlmm_driver = { .driver = { @@ -1279,4 +1280,3 @@ module_exit(sm6125_tlmm_exit); MODULE_DESCRIPTION("QTI sm6125 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c new file mode 100644 index 000000000000..946b23084304 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sm6350_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; + +static const struct lpi_pingroup sm6350_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP_SLEW_SPARE_1(14, 0, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sm6350_functions[] = { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm6350_lpi_data = { + .pins = sm6350_lpi_pins, + .npins = ARRAY_SIZE(sm6350_lpi_pins), + .groups = sm6350_groups, + .ngroups = ARRAY_SIZE(sm6350_groups), + .functions = sm6350_functions, + .nfunctions = ARRAY_SIZE(sm6350_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sm6350-lpass-lpi-pinctrl", + .data = &sm6350_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sm6350-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm SM6350 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c index eb8cd4aa8a97..4089c96ff736 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -1363,6 +1363,7 @@ static const struct of_device_id sm6350_tlmm_of_match[] = { { .compatible = "qcom,sm6350-tlmm" }, { }, }; +MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match); static struct platform_driver sm6350_tlmm_driver = { .driver = { @@ -1386,4 +1387,3 @@ module_exit(sm6350_tlmm_exit); MODULE_DESCRIPTION("QTI SM6350 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm6350_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c index d4547dd9f21f..8da71d940b90 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6375.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c @@ -1506,6 +1506,7 @@ static const struct of_device_id sm6375_tlmm_of_match[] = { { .compatible = "qcom,sm6375-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm6375_tlmm_of_match); static struct platform_driver sm6375_tlmm_driver = { .driver = { @@ -1529,4 +1530,3 @@ module_exit(sm6375_tlmm_exit); MODULE_DESCRIPTION("QTI SM6375 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm6375_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c index 0767261f5149..526cc7bb3c6c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -1493,18 +1493,18 @@ static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = { { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 }, - { 39, 125 }, { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 }, - { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 51, 123 }, + { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 }, + { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 }, { 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 }, { 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 }, - { 88, 117 }, { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, + { 88, 117 }, { 90, 69 }, { 91, 70 }, { 93, 75 }, { 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 }, { 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 }, { 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 }, { 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 }, { 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 }, - { 144, 115 }, { 144, 122 }, { 147, 102 }, { 150, 107 }, + { 144, 115 }, { 147, 102 }, { 150, 107 }, { 152, 108 }, { 153, 109 } }; @@ -1532,6 +1532,7 @@ static const struct of_device_id sm8150_pinctrl_of_match[] = { { .compatible = "qcom,sm8150-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match); static struct platform_driver sm8150_pinctrl_driver = { .driver = { @@ -1555,4 +1556,3 @@ module_exit(sm8150_pinctrl_exit); MODULE_DESCRIPTION("QTI sm8150 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c index c27452eece3e..454de788be21 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -7,6 +7,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -127,17 +129,22 @@ static const struct lpi_pinctrl_variant_data sm8250_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8250-lpass-lpi-pinctrl", - .data = &sm8250_lpi_data, + .compatible = "qcom,sm8250-lpass-lpi-pinctrl", + .data = &sm8250_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8250-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index f73f3b052de4..abf5f68ef62f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -1354,6 +1354,7 @@ static const struct of_device_id sm8250_pinctrl_of_match[] = { { .compatible = "qcom,sm8250-pinctrl", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); static struct platform_driver sm8250_pinctrl_driver = { .driver = { @@ -1377,4 +1378,3 @@ module_exit(sm8250_pinctrl_exit); MODULE_DESCRIPTION("QTI sm8250 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c index 377ddfc77e4f..8bd278c97171 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -1632,6 +1632,7 @@ static const struct of_device_id sm8350_tlmm_of_match[] = { { .compatible = "qcom,sm8350-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match); static struct platform_driver sm8350_tlmm_driver = { .driver = { @@ -1655,4 +1656,3 @@ module_exit(sm8350_tlmm_exit); MODULE_DESCRIPTION("QTI SM8350 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8350_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e..834eee8dcce9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -195,17 +197,22 @@ static const struct lpi_pinctrl_variant_data sm8450_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8450-lpass-lpi-pinctrl", - .data = &sm8450_lpi_data, + .compatible = "qcom,sm8450-lpass-lpi-pinctrl", + .data = &sm8450_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8450-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index a1d84074ea49..8ca5b6e15e6c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -1667,6 +1667,7 @@ static const struct of_device_id sm8450_tlmm_of_match[] = { { .compatible = "qcom,sm8450-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match); static struct platform_driver sm8450_tlmm_driver = { .driver = { @@ -1690,4 +1691,3 @@ module_exit(sm8450_tlmm_exit); MODULE_DESCRIPTION("QTI SM8450 TLMM driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c2..875e04e5d2b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -203,17 +205,22 @@ static const struct lpi_pinctrl_variant_data sm8550_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8550-lpass-lpi-pinctrl", - .data = &sm8550_lpi_data, + .compatible = "qcom,sm8550-lpass-lpi-pinctrl", + .data = &sm8550_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8550-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index cc8fbf4d5e84..d12256d970a0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -1752,6 +1752,7 @@ static const struct of_device_id sm8550_tlmm_of_match[] = { { .compatible = "qcom,sm8550-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); static struct platform_driver sm8550_tlmm_driver = { .driver = { @@ -1775,4 +1776,3 @@ module_exit(sm8550_tlmm_exit); MODULE_DESCRIPTION("QTI SM8550 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm8550_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d..bc7889c993d0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -6,6 +6,8 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> #include "pinctrl-lpass-lpi.h" @@ -210,17 +212,22 @@ static const struct lpi_pinctrl_variant_data sm8650_lpi_data = { static const struct of_device_id lpi_pinctrl_of_match[] = { { - .compatible = "qcom,sm8650-lpass-lpi-pinctrl", - .data = &sm8650_lpi_data, + .compatible = "qcom,sm8650-lpass-lpi-pinctrl", + .data = &sm8650_lpi_data, }, { } }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); +static const struct dev_pm_ops lpi_pinctrl_pm_ops = { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver = { .driver = { - .name = "qcom-sm8650-lpass-lpi-pinctrl", - .of_match_table = lpi_pinctrl_of_match, + .name = "qcom-sm8650-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + .pm = pm_ptr(&lpi_pinctrl_pm_ops), }, .probe = lpi_pinctrl_probe, .remove = lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index ab41292e3b4e..cf57d226c47f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -1732,6 +1732,7 @@ static const struct of_device_id sm8650_tlmm_of_match[] = { { .compatible = "qcom,sm8650-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, sm8650_tlmm_of_match); static struct platform_driver sm8650_tlmm_driver = { .driver = { @@ -1755,4 +1756,3 @@ module_exit(sm8650_tlmm_exit); MODULE_DESCRIPTION("QTI SM8650 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm8650_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c index 4cfe73f30fac..f27e55c088d5 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8750.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c @@ -1701,6 +1701,7 @@ static const struct of_device_id sm8750_tlmm_of_match[] = { { .compatible = "qcom,sm8750-tlmm", }, {}, }; +MODULE_DEVICE_TABLE(of, sm8750_tlmm_of_match); static struct platform_driver sm8750_tlmm_driver = { .driver = { @@ -1724,4 +1725,3 @@ module_exit(sm8750_tlmm_exit); MODULE_DESCRIPTION("QTI SM8750 TLMM driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, sm8750_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index d02d42513ebb..922c27177b5a 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1229,6 +1229,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm7550-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm8010-gpio", .data = (void *) 2 }, { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, @@ -1261,6 +1262,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 }, { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmg1110-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmh0101-gpio", .data = (void *)18 }, { .compatible = "qcom,pmh0104-gpio", .data = (void *)8 }, { .compatible = "qcom,pmh0110-gpio", .data = (void *)14 }, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 5c966d51eda7..c42dd7c736fe 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -53,7 +53,7 @@ #define PM8XXX_GPIO_PHYSICAL_OFFSET 1 /* custom pinconf parameters */ -#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1) +#define PM8XXX_QCOM_DRIVE_STRENGTH (PIN_CONFIG_END + 1) #define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2) /** @@ -97,13 +97,13 @@ struct pm8xxx_gpio { }; static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = { - {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0}, + {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGTH, 0}, {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0}, }; #ifdef CONFIG_DEBUG_FS static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = { - PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true), + PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGTH, "drive-strength", NULL, true), PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true), }; #endif @@ -291,7 +291,7 @@ static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_POWER_SOURCE: arg = pin->power_source; break; - case PM8XXX_QCOM_DRIVE_STRENGH: + case PM8XXX_QCOM_DRIVE_STRENGTH: arg = pin->output_strength; break; case PIN_CONFIG_DRIVE_PUSH_PULL: @@ -373,7 +373,7 @@ static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, pin->power_source = arg; banks |= BIT(0); break; - case PM8XXX_QCOM_DRIVE_STRENGH: + case PM8XXX_QCOM_DRIVE_STRENGTH: if (arg > PMIC_GPIO_STRENGTH_LOW) { dev_err(pctrl->dev, "invalid drive strength\n"); return -EINVAL; diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index a9fe75fc45e5..e4c0abcd95b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1836,9 +1836,7 @@ static const struct msm_pinctrl_soc_data x1e80100_pinctrl = { .ngroups = ARRAY_SIZE(x1e80100_groups), .ngpios = 239, .wakeirq_map = x1e80100_pdc_map, - /* TODO: Enabling PDC currently breaks GPIO interrupts */ - .nwakeirq_map = 0, - /* .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), */ + .nwakeirq_map = ARRAY_SIZE(x1e80100_pdc_map), .egpio_func = 9, }; @@ -1851,6 +1849,7 @@ static const struct of_device_id x1e80100_pinctrl_of_match[] = { { .compatible = "qcom,x1e80100-tlmm", }, { }, }; +MODULE_DEVICE_TABLE(of, x1e80100_pinctrl_of_match); static struct platform_driver x1e80100_pinctrl_driver = { .driver = { @@ -1874,4 +1873,3 @@ module_exit(x1e80100_pinctrl_exit); MODULE_DESCRIPTION("QTI X1E80100 TLMM pinctrl driver"); MODULE_LICENSE("GPL"); -MODULE_DEVICE_TABLE(of, x1e80100_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c index 7d7fff538755..13c417731be7 100644 --- a/drivers/pinctrl/qcom/tlmm-test.c +++ b/drivers/pinctrl/qcom/tlmm-test.c @@ -33,7 +33,7 @@ * dynamically, rather then relying on e.g. Devicetree and phandles. */ -#define MSM_PULL_MASK GENMASK(2, 0) +#define MSM_PULL_MASK GENMASK(1, 0) #define MSM_PULL_DOWN 1 #define MSM_PULL_UP 3 #define TLMM_REG_SIZE 0x1000 @@ -273,7 +273,6 @@ static void tlmm_test_low(struct kunit *test) int i; priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH; - atomic_set(&priv->intr_op_remain, 9); tlmm_output_high(); @@ -298,7 +297,6 @@ static void tlmm_test_high(struct kunit *test) int i; priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW; - atomic_set(&priv->intr_op_remain, 9); tlmm_output_low(); @@ -521,7 +519,6 @@ static void tlmm_test_rising_while_disabled(struct kunit *test) unsigned int before_edge; priv->intr_op = TLMM_TEST_COUNT; - atomic_set(&priv->thread_op_remain, 10); tlmm_output_low(); @@ -581,6 +578,9 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) int ret; int i; + if (!strcmp(tlmm_reg_name, "default_region")) + return of_address_to_resource(tlmm, 0, res); + count = of_property_count_strings(tlmm, "reg-names"); if (count <= 0) { pr_err("failed to find tlmm reg name\n"); @@ -597,18 +597,14 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) return -EINVAL; } - if (!strcmp(tlmm_reg_name, "default_region")) { - ret = of_address_to_resource(tlmm, 0, res); - } else { - for (i = 0; i < count; i++) { - if (!strcmp(reg_names[i], tlmm_reg_name)) { - ret = of_address_to_resource(tlmm, i, res); - break; - } + for (i = 0; i < count; i++) { + if (!strcmp(reg_names[i], tlmm_reg_name)) { + ret = of_address_to_resource(tlmm, i, res); + break; } - if (i == count) - ret = -EINVAL; } + if (i == count) + ret = -EINVAL; kfree(reg_names); diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig index 054e85db99e7..a156c4ef556e 100644 --- a/drivers/pinctrl/realtek/Kconfig +++ b/drivers/pinctrl/realtek/Kconfig @@ -2,8 +2,8 @@ config PINCTRL_RTD tristate "Realtek DHC core pin controller driver" - depends on ARCH_REALTEK - default y + depends on ARCH_REALTEK || (COMPILE_TEST && OF) + default ARCH_REALTEK select PINMUX select GENERIC_PINCONF select REGMAP_MMIO @@ -11,22 +11,22 @@ config PINCTRL_RTD config PINCTRL_RTD1619B tristate "Realtek DHC 1619B pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK config PINCTRL_RTD1319D tristate "Realtek DHC 1319D pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK config PINCTRL_RTD1315E tristate "Realtek DHC 1315E pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK config PINCTRL_RTD1625 tristate "Realtek DHC 1625 pin controller driver" depends on PINCTRL_RTD - default y + default ARCH_REALTEK help This driver enables support for the pin controller on the Realtek RTD1625 SoCs. diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index a2c672508a4b..60222339726b 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -34,14 +34,14 @@ struct rtd_pinctrl { }; /* custom pinconf parameters */ -#define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1) -#define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2) +#define RTD_DRIVE_STRENGTH_P (PIN_CONFIG_END + 1) +#define RTD_DRIVE_STRENGTH_N (PIN_CONFIG_END + 2) #define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3) #define RTD_HIGH_VIL (PIN_CONFIG_END + 4) static const struct pinconf_generic_params rtd_custom_bindings[] = { - {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0}, - {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0}, + {"realtek,drive-strength-p", RTD_DRIVE_STRENGTH_P, 0}, + {"realtek,drive-strength-n", RTD_DRIVE_STRENGTH_N, 0}, {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0}, {"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0}, }; @@ -473,7 +473,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, val = 1; break; - case RTD_DRIVE_STRENGH_P: + case RTD_DRIVE_STRENGTH_P: sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); if (!sconfig_desc) { dev_err(data->dev, "P driving unsupported for pin: %s\n", name); @@ -490,7 +490,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, val = set_val << p_off; break; - case RTD_DRIVE_STRENGH_N: + case RTD_DRIVE_STRENGTH_N: sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); if (!sconfig_desc) { dev_err(data->dev, "N driving unsupported for pin: %s\n", name); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1625.c b/drivers/pinctrl/realtek/pinctrl-rtd1625.c index 2d623bdbf9ca..88f2be37f743 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd1625.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd1625.c @@ -986,7 +986,7 @@ static const char * const rtd1625_iso_pwm0_loc2_groups[] = { }; static const char * const rtd1625_iso_spdif_in_coaxial_groups[] = { - "gpio_163", "spdif_sel", "spdif_in_mode" + "gpio_163", "spdif_in_mode" }; static const char * const rtd1625_iso_spdif_in_gpio_groups[] = { @@ -2867,7 +2867,7 @@ static const struct rtd_pin_config_desc rtd1625_ve4_configs[] = { [RTD1625_VE4_GPIO_6] = RTK_PIN_CONFIG_V2(gpio_6, 0x1c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_7] = RTK_PIN_CONFIG_V2(gpio_7, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_12] = RTK_PIN_CONFIG_V2(gpio_12, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), - [RTD1625_VE4_GPIO_13] = RTK_PIN_CONFIG_V2(gpio_13, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_13] = RTK_PIN_CONFIG_V2(gpio_13, 0x20, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_16] = RTK_PIN_CONFIG_V2(gpio_16, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_17] = RTK_PIN_CONFIG_V2(gpio_17, 0x20, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), [RTD1625_VE4_GPIO_18] = RTK_PIN_CONFIG_V2(gpio_18, 0x24, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 0840668638d9..a466ebf99593 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -1380,40 +1380,40 @@ static int sh_pfc_probe(struct platform_device *pdev) static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_SH7203 - { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, + { .name = "pfc-sh7203", .driver_data = (kernel_ulong_t)&sh7203_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7264 - { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, + { .name = "pfc-sh7264", .driver_data = (kernel_ulong_t)&sh7264_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7269 - { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, + { .name = "pfc-sh7269", .driver_data = (kernel_ulong_t)&sh7269_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7720 - { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, + { .name = "pfc-sh7720", .driver_data = (kernel_ulong_t)&sh7720_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7722 - { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, + { .name = "pfc-sh7722", .driver_data = (kernel_ulong_t)&sh7722_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7723 - { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, + { .name = "pfc-sh7723", .driver_data = (kernel_ulong_t)&sh7723_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7724 - { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, + { .name = "pfc-sh7724", .driver_data = (kernel_ulong_t)&sh7724_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7734 - { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, + { .name = "pfc-sh7734", .driver_data = (kernel_ulong_t)&sh7734_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7757 - { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, + { .name = "pfc-sh7757", .driver_data = (kernel_ulong_t)&sh7757_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7785 - { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, + { .name = "pfc-sh7785", .driver_data = (kernel_ulong_t)&sh7785_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SH7786 - { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, + { .name = "pfc-sh7786", .driver_data = (kernel_ulong_t)&sh7786_pinmux_info }, #endif #ifdef CONFIG_PINCTRL_PFC_SHX3 - { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, + { .name = "pfc-shx3", .driver_data = (kernel_ulong_t)&shx3_pinmux_info }, #endif { /* sentinel */ } }; diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index 8618f32ed26a..4cab641c3350 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -44,12 +44,12 @@ struct rza2_pinctrl_priv { struct device *dev; void __iomem *base; - struct pinctrl_pin_desc *pins; struct pinctrl_desc desc; struct pinctrl_dev *pctl; struct pinctrl_gpio_range gpio_range; - int npins; + unsigned int npins; struct mutex mutex; /* serialize adding groups and functions */ + struct pinctrl_pin_desc pins[] __counted_by(npins); }; #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */ @@ -289,21 +289,15 @@ static int rza2_gpio_register(struct rza2_pinctrl_priv *priv) static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv) { - struct pinctrl_pin_desc *pins; unsigned int i; int ret; - pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL); - if (!pins) - return -ENOMEM; - - priv->pins = pins; - priv->desc.pins = pins; + priv->desc.pins = priv->pins; priv->desc.npins = priv->npins; for (i = 0; i < priv->npins; i++) { - pins[i].number = i; - pins[i].name = rza2_gpio_names[i]; + priv->pins[i].number = i; + priv->pins[i].name = rza2_gpio_names[i]; } ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv, @@ -482,12 +476,17 @@ static const struct pinmux_ops rza2_pinmux_ops = { static int rza2_pinctrl_probe(struct platform_device *pdev) { struct rza2_pinctrl_priv *priv; + unsigned int npins; int ret; - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + npins = (uintptr_t)of_device_get_match_data(&pdev->dev) * + RZA2_PINS_PER_PORT; + + priv = devm_kzalloc(&pdev->dev, struct_size(priv, pins, npins), GFP_KERNEL); if (!priv) return -ENOMEM; + priv->npins = npins; priv->dev = &pdev->dev; priv->base = devm_platform_ioremap_resource(pdev, 0); @@ -498,9 +497,6 @@ static int rza2_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); - priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) * - RZA2_PINS_PER_PORT; - priv->desc.name = DRIVER_NAME; priv->desc.pctlops = &rza2_pinctrl_ops; priv->desc.pmxops = &rza2_pinmux_ops; diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 561e6018fd89..be52d47d77ae 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -11,12 +11,14 @@ #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/property.h> +#include <linux/regmap.h> #include <linux/seq_file.h> #include <linux/spinlock.h> @@ -26,6 +28,7 @@ #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> +#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h> #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h> #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> @@ -63,10 +66,18 @@ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ #define PIN_CFG_ELC BIT(17) #define PIN_CFG_IOLH_RZV2H BIT(18) +#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ +#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ +#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ +#define PIN_CFG_OTHER_POC_MASK \ + (PIN_CFG_PVDD1833_OTH_AWO_POC | \ + PIN_CFG_PVDD1833_OTH_ISO_POC | \ + PIN_CFG_WDTOVF_N_POC) + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -85,6 +96,18 @@ #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) +#define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \ + (PIN_CFG_IO_VMC_##ether | \ + PIN_CFG_IOLH_C | \ + PIN_CFG_PUPD | \ + PIN_CFG_NF) + +#define RZG3L_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ + PIN_CFG_SOFT_PS) + +#define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG2L_MPXED_COMMON_PIN_FUNCS(grp) | \ + PIN_CFG_PVDD1833_OTH_##poc##_POC) + #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) #define PIN_CFG_MASK GENMASK_ULL(31, 0) @@ -131,6 +154,18 @@ FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) +#define RZG3L_CLONE_CHANNEL_PIN_MASK GENMASK(31, 24) +#define RZG3L_CLONE_CHANNEL_PORT_MASK GENMASK(23, 19) +#define RZG3L_CLONE_CHANNEL_BIT_MASK GENMASK(12, 9) +#define RZG3L_CLONE_CHANNEL_VAL_MASK BIT(8) +#define RZG3L_CLONE_CHANNEL_PFC_MASK GENMASK(7, 0) +#define RZG3L_CLONE_CHANNEL_DATA(port, pins, bit, val, pfc) \ + (FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PIN_MASK, (pins)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PORT_MASK, (port)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_BIT_MASK, (bit)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_VAL_MASK, (val)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PFC_MASK, (pfc))) + #define P(off) (0x0000 + (off)) #define PM(off) (0x0100 + (off) * 2) #define PMC(off) (0x0200 + (off)) @@ -145,7 +180,8 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) +#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ +#define OTHER_POC (0x3028) /* known on RZ/G3L only */ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -220,12 +256,16 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = { * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset * @oen: OEN register offset + * @qspi: QSPI register offset + * @other_poc: OTHER_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; u16 eth_poc; u16 oen; + u16 qspi; + u16 other_poc; }; /** @@ -287,6 +327,8 @@ struct rzg2l_pinctrl_data { const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; + const u32 *clone_channel_data; + unsigned int n_clone_channel_data; const struct rzg2l_hwcfg *hwcfg; const u64 *variable_pin_cfg; unsigned int n_variable_pin_cfg; @@ -319,12 +361,16 @@ struct rzg2l_pinctrl_pin_settings { * @pmc: PMC registers cache * @pfc: PFC registers cache * @iolh: IOLH registers cache - * @pupd: PUPD registers cache * @ien: IEN registers cache + * @pupd: PUPD registers cache * @smt: SMT registers cache + * @sr: SR registers cache + * @nod: NOD registers cache + * @clone: Clone register cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @oen: Output Enable register cache + * @other_poc: OTHER_POC register cache * @qspi: QSPI registers cache */ struct rzg2l_pinctrl_reg_cache { @@ -335,10 +381,14 @@ struct rzg2l_pinctrl_reg_cache { u32 *iolh[2]; u32 *ien[2]; u32 *pupd[2]; - u32 *smt; + u32 *smt[2]; + u32 *sr[2]; + u32 *nod[2]; + u32 clone; u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; + u8 other_poc; u8 qspi; }; @@ -353,6 +403,8 @@ struct rzg2l_pinctrl { struct clk *clk; + struct regmap *syscon; + struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); @@ -366,6 +418,7 @@ struct rzg2l_pinctrl { struct rzg2l_pinctrl_reg_cache *cache; struct rzg2l_pinctrl_reg_cache *dedicated_cache; atomic_t wakeup_path; + u32 clone_offset; }; static const u16 available_ps[] = { 1800, 2500, 3300 }; @@ -388,6 +441,60 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, return 0; } +static const u64 r9a08g046_variable_pin_cfg[] = { + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)), +}; + static const u64 r9a09g047_variable_pin_cfg[] = { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), @@ -537,6 +644,45 @@ static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl, return 0; } +static int rzg2l_pinctrl_set_clone_mode(struct rzg2l_pinctrl *pctrl, + u8 port, u8 pin, u8 func) +{ + unsigned int i; + + if (!pctrl->data->clone_channel_data) + return 0; + + switch (func) { + case 2: + case 4 ... 7: + break; + default: + return 0; + } + + for (i = 0; i < pctrl->data->n_clone_channel_data; i++) { + u32 pin_data = pctrl->data->clone_channel_data[i]; + unsigned int pin_func_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PFC_MASK, pin_data); + unsigned int pin_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PIN_MASK, pin_data); + u32 bit, val; + + if (!(pin_func_mask & BIT(func)) || + FIELD_GET(RZG3L_CLONE_CHANNEL_PORT_MASK, pin_data) != port) + continue; + + if (!(pin_mask & BIT(pin))) + continue; + + bit = FIELD_GET(RZG3L_CLONE_CHANNEL_BIT_MASK, pin_data); + val = FIELD_GET(RZG3L_CLONE_CHANNEL_VAL_MASK, pin_data); + + return regmap_update_bits(pctrl->syscon, pctrl->clone_offset, + BIT(bit), val << bit); + } + + return 0; +} + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -601,16 +747,22 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, for (i = 0; i < group->grp.npins; i++) { u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u32 port = RZG2L_PIN_ID_TO_PORT(pins[i]); u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); + unsigned int func; - ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin); + ret = rzg2l_validate_pin(pctrl, *pin_data, port, pin); if (ret) return ret; - dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); + func = psel_val[i] - hwcfg->func_base; + dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", port, pin, off, func); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); + ret = rzg2l_pinctrl_set_clone_mode(pctrl, port, pin, func); + if (ret) + return ret; + + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func); } return 0; @@ -894,7 +1046,8 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, raw_spin_unlock_irqrestore(&pctrl->lock, flags); } -static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) +static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, + u32 caps, u8 *mask) { if (caps & PIN_CFG_IO_VMC_SD0) return SD_CH(regs->sd_ch, 0); @@ -906,6 +1059,16 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; + if (caps & PIN_CFG_OTHER_POC_MASK) { + if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) + *mask = BIT(0); + else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) + *mask = BIT(1); + else + *mask = BIT(2); + + return OTHER_POC; + } return -EINVAL; } @@ -914,17 +1077,20 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; + u8 val, mask; int pwr_reg; - u8 val; if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; - pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); if (pwr_reg < 0) return pwr_reg; val = readb(pctrl->base + pwr_reg); + if (pwr_reg == OTHER_POC) + val = field_get(mask, val); + switch (val) { case PVDD_1800: return 1800; @@ -942,8 +1108,8 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; + u8 poc_val, val, mask; int pwr_reg; - u8 val; if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source = ps; @@ -952,25 +1118,37 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps switch (ps) { case 1800: - val = PVDD_1800; + poc_val = PVDD_1800; break; case 2500: if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) return -EINVAL; - val = PVDD_2500; + poc_val = PVDD_2500; break; case 3300: - val = PVDD_3300; + poc_val = PVDD_3300; break; default: return -EINVAL; } - pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); if (pwr_reg < 0) return pwr_reg; - writeb(val, pctrl->base + pwr_reg); + if (pwr_reg == OTHER_POC) { + scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { + val = readb(pctrl->base + pwr_reg); + if (poc_val) + val |= mask; + else + val &= ~mask; + writeb(val, pctrl->base + pwr_reg); + } + } else { + writeb(poc_val, pctrl->base + pwr_reg); + } + pctrl->settings[pin].power_source = ps; return 0; @@ -1083,7 +1261,7 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); - if (pin > pctrl->data->hwcfg->oen_max_pin) + if (pin != pctrl->data->hwcfg->oen_max_pin) return -EINVAL; /* @@ -1103,7 +1281,7 @@ static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) int bit; if (!pctrl->data->pin_to_oen_bit) - return -EOPNOTSUPP; + return -ENOTSUPP; bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) @@ -1145,7 +1323,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe u8 val; if (!pctrl->data->pin_to_oen_bit) - return -EOPNOTSUPP; + return -ENOTSUPP; bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) @@ -1576,7 +1754,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, break; default: - return -EOPNOTSUPP; + return -ENOTSUPP; } } @@ -1643,8 +1821,9 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { + unsigned long prev_config = 0; const unsigned int *pins; - unsigned int i, npins, prev_config = 0; + unsigned int i, npins; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); @@ -1658,7 +1837,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, /* Check config matching between to pin */ if (i && prev_config != *config) - return -EOPNOTSUPP; + return -ENOTSUPP; prev_config = *config; } @@ -2089,6 +2268,70 @@ static const u64 r9a09g047_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ }; +static const char * const rzg3l_gpio_names[] = { + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", + "", "", "", "", "", "", "", "", + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", + "", "", "", "", "", "", "", "", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", + "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", + "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", + "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", + "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", + "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", + "", "", "", "", "", "", "", "", + "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", + "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", + "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", + "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", +}; + +static const u64 r9a08g046_gpio_configs[] = { + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN), /* P2 */ + RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */ + 0x0, + RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P5 */ + RZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P6 */ + RZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P7 */ + RZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P8 */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ + RZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), /* PC */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ + RZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), /* PF */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ + RZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), /* PK */ + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG3L_MPXED_PIN_FUNCS(C)), /* PL */ + RZG2L_GPIO_PORT_PACK(8, 0x36, RZG3L_MPXED_PIN_FUNCS(C)), /* PM */ + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x3c, RZG3L_MPXED_PIN_FUNCS(A)), /* PS */ +}; + static const char * const rzv2h_gpio_names[] = { "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", @@ -2427,6 +2670,128 @@ static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, }; +static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = { + { "WDTOVF_N", RZG2L_SINGLE_PIN_PACK(0x5, 0, + (PIN_CFG_IOLH_A | PIN_CFG_WDTOVF_N_POC)) }, + { "SCIF0_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, + { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, +}; + +static const u32 r9a08g046_clone_channel_data[] = { + /* I2C ch2 Bit:0 Value:0 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(7, 6), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 2), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)), + /* I2C ch2 Bit:0 Value:1 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(2, 1), 0, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)), + /* I2C ch3 Bit:1 Value:0 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 1, 0, BIT(4)), + /* I2C ch3 Bit:1 Value:1 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P2, GENMASK(1, 0), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6) | GENMASK(3, 2), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 3) | BIT(0), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(3, 2), 1, 1, BIT(4)), + /* SCIF ch3 Bit:4 Value:0 PFC:{6,7} */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(6, 4), 4, 0, BIT(6)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 3), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(4, 2), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 3), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(2, 0), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 1), 4, 0, BIT(7)), + /* SCIF ch3 Bit:4 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(2, 0), 4, 1, BIT(7)), + /* SCIF ch4 Bit:5 Value:0 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(2, 0), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 5), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, BIT(0), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(5, 3), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(6, 4), 5, 0, BIT(7)), + /* SCIF ch4 Bit:5 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 3), 5, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 2), 5, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 5), 5, 1, BIT(7)), + /* SCIF ch5 Bit:6 Value:0 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, BIT(7), 6, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 6, 0, BIT(7)), + /* SCIF ch5 Bit:6 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6), 6, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(1, 0), 6, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(4, 2) | BIT(0), 6, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(2, 0), 6, 1, BIT(7)), + /* RSPI ch1 Bit:8 Value:0 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 0), 8, 0, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 5), 8, 0, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 8, 0, BIT(2)), + /* RSPI ch1 Bit:8 Value:1 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 0), 8, 1, BIT(2)), + /* RSPI ch2 Bit:9 Value:0 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 4), 9, 0, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(2, 0), 9, 0, BIT(2)), + /* RSPI ch2 Bit:9 Value:1 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 0), 9, 1, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, BIT(7), 9, 1, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 0), 9, 1, BIT(2)), + /* RSCI ch1 Bit:12 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(3, 0), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(3, 0), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 4), 12, 0, GENMASK(6, 5)), + /* RSCI ch1 Bit:12 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(3, 0), 12, 1, GENMASK(6, 5)), + /* RSCI ch2 Bit:13 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 4), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + /* RSCI ch2 Bit:13 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 4), 13, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | BIT(0), 13, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6) | GENMASK(1, 0), 13, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(1, 0), 13, 1, GENMASK(6, 5)), + /* RSCI ch3 Bit:14 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6), 14, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 14, 0, GENMASK(6, 5)), + /* RSCI ch3 Bit:14 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 1), 14, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(5, 2), 14, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 2), 14, 1, GENMASK(6, 5)), +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; @@ -2737,10 +3102,6 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) if (!cache->pfc) return -ENOMEM; - cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL); - if (!cache->smt) - return -ENOMEM; - for (u8 i = 0; i < 2; i++) { u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; @@ -2759,6 +3120,21 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) if (!cache->pupd[i]) return -ENOMEM; + cache->smt[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt[i]), + GFP_KERNEL); + if (!cache->smt[i]) + return -ENOMEM; + + cache->sr[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr[i]), + GFP_KERNEL); + if (!cache->sr[i]) + return -ENOMEM; + + cache->nod[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->nod[i]), + GFP_KERNEL); + if (!cache->nod[i]) + return -ENOMEM; + /* Allocate dedicated cache. */ dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, sizeof(*dedicated_cache->iolh[i]), @@ -2771,6 +3147,24 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) GFP_KERNEL); if (!dedicated_cache->ien[i]) return -ENOMEM; + + dedicated_cache->sr[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->sr[i]), + GFP_KERNEL); + if (!dedicated_cache->sr[i]) + return -ENOMEM; + + dedicated_cache->nod[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->nod[i]), + GFP_KERNEL); + if (!dedicated_cache->nod[i]) + return -ENOMEM; + + dedicated_cache->pupd[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->pupd[i]), + GFP_KERNEL); + if (!dedicated_cache->pupd[i]) + return -ENOMEM; } pctrl->cache = cache; @@ -2818,6 +3212,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) chip->direction_output = rzg2l_gpio_direction_output; chip->get = rzg2l_gpio_get; chip->set = rzg2l_gpio_set; + chip->set_config = gpiochip_generic_config; chip->label = name; chip->parent = pctrl->dev; chip->owner = THIS_MODULE; @@ -2955,6 +3350,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg3l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg3e_gpio_names)); @@ -2981,6 +3379,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) "failed to enable GPIO clk\n"); } + if (pctrl->data->clone_channel_data) { + struct device_node *np = pctrl->dev->of_node; + + pctrl->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,clonech", + 1, &pctrl->clone_offset); + if (IS_ERR(pctrl->syscon)) + return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->syscon), + "Failed to parse renesas,clonech\n"); + } + raw_spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); mutex_init(&pctrl->mutex); @@ -3002,7 +3410,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; for (u32 port = 0; port < nports; port++) { - bool has_iolh, has_ien, has_pupd, has_smt; + bool has_iolh, has_ien, has_pupd, has_smt, has_sr, has_nod; u32 off, caps; u8 pincnt; u64 cfg; @@ -3023,6 +3431,8 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen has_ien = !!(caps & PIN_CFG_IEN); has_pupd = !!(caps & PIN_CFG_PUPD); has_smt = !!(caps & PIN_CFG_SMT); + has_sr = !!(caps & PIN_CFG_SR); + has_nod = !!(caps & PIN_CFG_NOD); if (suspend) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); @@ -3049,7 +3459,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), cache->pupd[0][port]); if (pincnt >= 4) { - RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off) + 4, cache->pupd[1][port]); } } @@ -3066,8 +3476,32 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen } } - if (has_smt) - RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]); + if (has_smt) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), + cache->smt[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off) + 4, + cache->smt[1][port]); + } + } + + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), + cache->sr[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4, + cache->sr[1][port]); + } + } + + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), + cache->nod[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off) + 4, + cache->nod[1][port]); + } + } } } @@ -3082,7 +3516,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b * port offset are close together. */ for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { - bool has_iolh, has_ien; + bool has_iolh, has_ien, has_sr, has_nod, has_pupd; u32 off, next_off = 0; u64 cfg, next_cfg; u8 pincnt; @@ -3101,8 +3535,12 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b } /* And apply them in a single shot. */ - has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); + has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | + PIN_CFG_IOLH_C | PIN_CFG_IOLH_RZV2H)); has_ien = !!(caps & PIN_CFG_IEN); + has_sr = !!(caps & PIN_CFG_SR); + has_nod = !!(caps & PIN_CFG_NOD); + has_pupd = !!(caps & PIN_CFG_PUPD); pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); if (has_iolh) { @@ -3113,6 +3551,18 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), cache->ien[0][i]); } + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), + cache->sr[0][i]); + } + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), + cache->nod[0][i]); + } + if (has_pupd) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), + cache->pupd[0][i]); + } if (pincnt >= 4) { if (has_iolh) { @@ -3125,6 +3575,21 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b pctrl->base + IEN(off) + 4, cache->ien[1][i]); } + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + SR(off) + 4, + cache->sr[1][i]); + } + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + NOD(off) + 4, + cache->nod[1][i]); + } + if (has_pupd) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + PUPD(off) + 4, + cache->pupd[1][i]); + } } caps = 0; } @@ -3207,8 +3672,19 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); } - cache->qspi = readb(pctrl->base + QSPI); + if (regs->qspi) + cache->qspi = readb(pctrl->base + regs->qspi); cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); + if (regs->other_poc) + cache->other_poc = readb(pctrl->base + regs->other_poc); + + if (pctrl->syscon) { + int ret; + + ret = regmap_read(pctrl->syscon, pctrl->clone_offset, &cache->clone); + if (ret) + return ret; + } if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3227,13 +3703,22 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) unsigned long flags; int ret; + if (pctrl->syscon) { + ret = regmap_write(pctrl->syscon, pctrl->clone_offset, cache->clone); + if (ret) + return ret; + } + if (!atomic_read(&pctrl->wakeup_path)) { ret = clk_prepare_enable(pctrl->clk); if (ret) return ret; } - writeb(cache->qspi, pctrl->base + QSPI); + if (regs->qspi) + writeb(cache->qspi, pctrl->base + regs->qspi); + if (regs->other_poc) + writeb(cache->other_poc, pctrl->base + regs->other_poc); raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3291,6 +3776,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .sd_ch = 0x3000, .eth_poc = 0x300c, .oen = 0x3018, + .qspi = QSPI, }, .iolh_groupa_ua = { /* 3v3 power source */ @@ -3301,6 +3787,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .oen_max_pin = 0, }; +static const struct rzg2l_hwcfg rzg3l_hwcfg = { + .regs = { + .pwpr = 0x3000, + .sd_ch = 0x3004, + .eth_poc = 0x3010, + .oen = 0x3018, + .other_poc = OTHER_POC, + }, + .iolh_groupa_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, + }, + .iolh_groupb_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, + }, + .iolh_groupc_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, + /* 2v5 source */ + [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, + }, + .tint_start_index = 17, + .drive_strength_ua = true, + .func_base = 0, + .oen_max_pin = 1, /* Pin 1 of P{B,E}1_ISO is the maximum OEN pin. */ +}; + static const struct rzg2l_hwcfg rzg3s_hwcfg = { .regs = { .pwpr = 0x3000, @@ -3394,6 +3914,25 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; +static struct rzg2l_pinctrl_data r9a08g046_data = { + .port_pins = rzg3l_gpio_names, + .port_pin_configs = r9a08g046_gpio_configs, + .n_ports = ARRAY_SIZE(r9a08g046_gpio_configs), + .variable_pin_cfg = r9a08g046_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a08g046_variable_pin_cfg), + .dedicated_pins = rzg3l_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg3l_dedicated_pins), + .clone_channel_data = r9a08g046_clone_channel_data, + .n_clone_channel_data = ARRAY_SIZE(r9a08g046_clone_channel_data), + .hwcfg = &rzg3l_hwcfg, + .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, + .pmc_writeb = &rzg2l_pmc_writeb, + .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, + .hw_to_bias_param = &rzg2l_hw_to_bias_param, + .bias_param_to_hw = &rzg2l_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g047_data = { .port_pins = rzg3e_gpio_names, .port_pin_configs = r9a09g047_gpio_configs, @@ -3475,6 +4014,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .data = &r9a08g045_data, }, { + .compatible = "renesas,r9a08g046-pinctrl", + .data = &r9a08g046_data, + }, + { .compatible = "renesas,r9a09g047-pinctrl", .data = &r9a09g047_data, }, diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 4ba11a83b604..eb70aee39f1a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -191,6 +191,12 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, guard(raw_spinlock_irqsave)(&pctrl->lock); + reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); + /* Check if pin is already configured to the desired function */ + if ((rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(pin)) && + field_get(PFC_PIN_MASK(pin), reg64) == func) + return; + /* Set pin to 'Non-use (Hi-Z input protection)' */ reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port)); reg16 &= ~PM_PIN_MASK(pin); @@ -200,7 +206,6 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); /* Select Pin function mode with PFC register */ - reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); reg64 &= ~PFC_PIN_MASK(pin); rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port)); @@ -1140,7 +1145,7 @@ static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) struct pinctrl_desc *desc = &pctrl->desc; struct device *dev = pctrl->dev; struct pinctrl_pin_desc *pins; - unsigned int i, j; + unsigned int i; int ret; desc->name = DRV_NAME; @@ -1157,11 +1162,9 @@ static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) pctrl->pins = pins; desc->pins = pins; - for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { + for (i = 0; i < pctrl->data->n_port_pins; i++) { pins[i].number = i; pins[i].name = rzt2h_gpio_names[i]; - if (i && !(i % RZT2H_PINS_PER_PORT)) - j++; } ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl); diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index 495e7f5d4128..9029d1947bbb 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -661,7 +661,7 @@ static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, } default: - return -EOPNOTSUPP; + return -ENOTSUPP; } } @@ -695,8 +695,9 @@ static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { + unsigned long prev_config = 0; const unsigned int *pins; - unsigned int i, npins, prev_config = 0; + unsigned int i, npins; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); @@ -710,7 +711,7 @@ static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, /* Check config matches previous pins */ if (i && prev_config != *config) - return -EOPNOTSUPP; + return -ENOTSUPP; prev_config = *config; } diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 3a742f74ecd1..8585ed4bcfe0 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -719,6 +719,30 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, return 0; } +static int sh_pfc_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins = pmx->pfc->info->groups[group].pins; + unsigned int num_pins = pmx->pfc->info->groups[group].nr_pins; + unsigned long prev_config = 0; + int ret; + + for (unsigned int i = 0; i < num_pins; ++i) { + ret = sh_pfc_pinconf_get(pctldev, pins[i], config); + if (ret) + return ret; + + /* configs should match for all pins in the group */ + if (i && prev_config != *config) + return -ENOTSUPP; + + prev_config = *config; + } + + return 0; +} + static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, unsigned long *configs, unsigned num_configs) @@ -745,6 +769,7 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = { .is_generic = true, .pin_config_get = sh_pfc_pinconf_get, .pin_config_set = sh_pfc_pinconf_set, + .pin_config_group_get = sh_pfc_pinconf_group_get, .pin_config_group_set = sh_pfc_pinconf_group_set, .pin_config_config_dbg_show = pinconf_generic_dump_config, }; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index fe9f92cb037e..1aa977d2a1f8 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -943,6 +943,138 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), }; +/* pin banks of exynos8855 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = { + GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00), + GS101_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04, 0x08), + EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"), + EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"), + GS101_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x08, 0x10), + GS101_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x0c, 0x14), + GS101_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x10, 0x18), + GS101_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x14, 0x1c), + GS101_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x18, 0x20), + GS101_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x1c, 0x24), + GS101_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x20, 0x28), + GS101_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x24, 0x2c), + GS101_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x28, 0x30), + GS101_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x2c, 0x34), + GS101_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x30, 0x38), + GS101_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x34, 0x3c), + GS101_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x38, 0x40), + GS101_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x3c, 0x44), + GS101_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x40, 0x48), + GS101_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x44, 0x4c), + GS101_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x48, 0x50), + GS101_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x4c, 0x54), +}; + +/* pin banks of exynos8855 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = { + GS101_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00, 0x00), + GS101_PIN_BANK_EINTW(1, 0x20, "gpm1", 0x04, 0x04), + GS101_PIN_BANK_EINTW(1, 0x40, "gpm2", 0x08, 0x08), + GS101_PIN_BANK_EINTW(1, 0x60, "gpm3", 0x0c, 0x0c), + GS101_PIN_BANK_EINTW(1, 0x80, "gpm4", 0x10, 0x10), + GS101_PIN_BANK_EINTW(1, 0xa0, "gpm5", 0x14, 0x14), + GS101_PIN_BANK_EINTW(1, 0xc0, "gpm6", 0x18, 0x18), + GS101_PIN_BANK_EINTW(1, 0xe0, "gpm7", 0x1c, 0x1c), + GS101_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20, 0x20), + GS101_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24, 0x24), + GS101_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28, 0x28), + GS101_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c, 0x2c), + GS101_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30, 0x30), + GS101_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34, 0x34), + GS101_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38, 0x38), + GS101_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c, 0x3c), + GS101_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40, 0x40), + GS101_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44, 0x44), + GS101_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48, 0x48), + GS101_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c, 0x4c), + GS101_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50, 0x50), + GS101_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54, 0x54), +}; + +/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = { + GS101_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00, 0x00), +}; + +/* pin banks of exynos8855 pin-controller 3 (PERIC) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = { + GS101_PIN_BANK_EINTG(8, 0x0, "gpp0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(8, 0x20, "gpp1", 0x04, 0x08), + GS101_PIN_BANK_EINTG(6, 0x40, "gpp2", 0x08, 0x10), + GS101_PIN_BANK_EINTG(4, 0x60, "gpg0", 0x0c, 0x18), + GS101_PIN_BANK_EINTG(3, 0x80, "gpg1", 0x10, 0x1c), + GS101_PIN_BANK_EINTG(6, 0xa0, "gpb0", 0x14, 0x20), + GS101_PIN_BANK_EINTG(4, 0xc0, "gpb1", 0x18, 0x28), +}; + +/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = { + GS101_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00, 0x00), +}; + +/* pin banks of exynos8855 pin-controller 5 (USI) */ +static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = { + GS101_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00, 0x00), + GS101_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04, 0x08), + GS101_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08, 0x0c), + GS101_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c, 0x10), +}; + +static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos8855_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos8855_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 2 HSI UFS data */ + .pin_banks = exynos8855_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 3 PERIC data */ + .pin_banks = exynos8855_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 4 PERICMMC data */ + .pin_banks = exynos8855_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, { + /* pin-controller instance 5 USI data */ + .pin_banks = exynos8855_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = { + .ctrl = exynos8855_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos8855_pin_ctrl), +}; + /* pin banks of exynos990 pin-controller 0 (ALIVE) */ static struct samsung_pin_bank_data exynos990_pin_banks0[] = { /* Must start with EINTG banks, ordered by EINT group number. */ diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 5ac6f6b02327..5ecc9ed4c44d 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos7885_of_data }, { .compatible = "samsung,exynos850-pinctrl", .data = &exynos850_of_data }, + { .compatible = "samsung,exynos8855-pinctrl", + .data = &exynos8855_of_data }, { .compatible = "samsung,exynos8890-pinctrl", .data = &exynos8890_of_data }, { .compatible = "samsung,exynos8895-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 937600430a6e..bb02fb49b2af 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; +extern const struct samsung_pinctrl_of_match_data exynos8855_of_data; extern const struct samsung_pinctrl_of_match_data exynos8890_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; extern const struct samsung_pinctrl_of_match_data exynos9610_of_data; diff --git a/drivers/pinctrl/sophgo/pinctrl-cv18xx.c b/drivers/pinctrl/sophgo/pinctrl-cv18xx.c index c3a2dcf71f2a..36e3c4f9e90f 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv18xx.c +++ b/drivers/pinctrl/sophgo/pinctrl-cv18xx.c @@ -27,8 +27,9 @@ #include "pinctrl-cv18xx.h" struct cv1800_priv { - u32 *power_cfg; - void __iomem *regs[2]; + void __iomem *regs[2]; + unsigned int num_power_cfg; + u32 power_cfg[] __counted_by(num_power_cfg); }; static unsigned int cv1800_dt_get_pin_mux(u32 value) @@ -333,13 +334,11 @@ static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, switch (param) { case PIN_CONFIG_BIAS_PULL_DOWN: - v &= ~PIN_IO_PULLDOWN; - v |= FIELD_PREP(PIN_IO_PULLDOWN, arg); + FIELD_MODIFY(PIN_IO_PULLDOWN, &v, arg); m |= PIN_IO_PULLDOWN; break; case PIN_CONFIG_BIAS_PULL_UP: - v &= ~PIN_IO_PULLUP; - v |= FIELD_PREP(PIN_IO_PULLUP, arg); + FIELD_MODIFY(PIN_IO_PULLUP, &v, arg); m |= PIN_IO_PULLUP; break; case PIN_CONFIG_DRIVE_STRENGTH_UA: @@ -347,8 +346,7 @@ static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, priv->power_cfg, arg); if (ret < 0) return ret; - v &= ~PIN_IO_DRIVE; - v |= FIELD_PREP(PIN_IO_DRIVE, ret); + FIELD_MODIFY(PIN_IO_DRIVE, &v, ret); m |= PIN_IO_DRIVE; break; case PIN_CONFIG_INPUT_SCHMITT_UV: @@ -356,21 +354,18 @@ static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, priv->power_cfg, arg); if (ret < 0) return ret; - v &= ~PIN_IO_SCHMITT; - v |= FIELD_PREP(PIN_IO_SCHMITT, ret); + FIELD_MODIFY(PIN_IO_SCHMITT, &v, ret); m |= PIN_IO_SCHMITT; break; case PIN_CONFIG_POWER_SOURCE: /* Ignore power source as it is always fixed */ break; case PIN_CONFIG_SLEW_RATE: - v &= ~PIN_IO_OUT_FAST_SLEW; - v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg); + FIELD_MODIFY(PIN_IO_OUT_FAST_SLEW, &v, arg); m |= PIN_IO_OUT_FAST_SLEW; break; case PIN_CONFIG_BIAS_BUS_HOLD: - v &= ~PIN_IO_BUS_HOLD; - v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg); + FIELD_MODIFY(PIN_IO_BUS_HOLD, &v, arg); m |= PIN_IO_BUS_HOLD; break; default: @@ -417,14 +412,11 @@ static int cv1800_pinctrl_init(struct platform_device *pdev, const struct sophgo_pinctrl_data *pctrl_data = pctrl->data; struct cv1800_priv *priv; - priv = devm_kzalloc(&pdev->dev, sizeof(struct cv1800_priv), GFP_KERNEL); + priv = devm_kzalloc(&pdev->dev, struct_size(priv, power_cfg, pctrl_data->npds), + GFP_KERNEL); if (!priv) return -ENOMEM; - - priv->power_cfg = devm_kcalloc(&pdev->dev, pctrl_data->npds, - sizeof(u32), GFP_KERNEL); - if (!priv->power_cfg) - return -ENOMEM; + priv->num_power_cfg = pctrl_data->npds; priv->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys"); if (IS_ERR(priv->regs[0])) diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig index c021d51033d1..b2365deffe1b 100644 --- a/drivers/pinctrl/spacemit/Kconfig +++ b/drivers/pinctrl/spacemit/Kconfig @@ -8,9 +8,7 @@ config PINCTRL_SPACEMIT_K1 depends on ARCH_SPACEMIT || COMPILE_TEST depends on OF default ARCH_SPACEMIT - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF + select GENERIC_PINCTRL help Say Y to select the pinctrl driver for K1/K3 SoC. This pin controller allows selecting the mux function for diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c index b0be62b1c816..c3a7538783b8 100644 --- a/drivers/pinctrl/spacemit/pinctrl-k1.c +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -114,11 +114,6 @@ struct spacemit_pinctrl_data { const struct spacemit_pinctrl_dconf *dconf; }; -struct spacemit_pin_mux_config { - const struct spacemit_pin *pin; - u32 config; -}; - /* map pin id to pinctrl register offset, refer MFPR definition */ static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) { @@ -228,16 +223,6 @@ static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, return pctrl->regs + pctrl->data->pin_to_offset(pin); } -static u16 spacemit_dt_get_pin(u32 value) -{ - return value >> 16; -} - -static u16 spacemit_dt_get_pin_mux(u32 value) -{ - return value & GENMASK(15, 0); -} - static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl, unsigned long pin) { @@ -409,38 +394,6 @@ static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, } } -static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, - struct device_node *dn, - struct spacemit_pin_mux_config *pinmuxs, - int num_pins, const char *grpname) -{ - struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct device *dev = pctrl->dev; - enum spacemit_pin_io_type type; - u32 power = 0, i; - - of_property_read_u32(dn, "power-source", &power); - - for (i = 0; i < num_pins; i++) { - type = spacemit_to_pin_io_type(pinmuxs[i].pin); - - if (type != IO_TYPE_EXTERNAL) - continue; - - switch (power) { - case PIN_POWER_STATE_1V8: - case PIN_POWER_STATE_3V3: - break; - default: - dev_err(dev, "group %s has unsupported power\n", - grpname); - return -ENOTSUPP; - } - } - - return 0; -} - static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, const struct spacemit_pin *spin, const enum spacemit_pin_io_type type) @@ -477,126 +430,12 @@ static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset); } -static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **maps, - unsigned int *num_maps) -{ - struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct device *dev = pctrl->dev; - struct device_node *child; - struct pinctrl_map *map; - const char **grpnames; - const char *grpname; - int ngroups = 0; - int nmaps = 0; - int ret; - - for_each_available_child_of_node(np, child) - ngroups += 1; - - grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); - if (!grpnames) - return -ENOMEM; - - map = kzalloc_objs(*map, ngroups * 2); - if (!map) - return -ENOMEM; - - ngroups = 0; - guard(mutex)(&pctrl->mutex); - for_each_available_child_of_node_scoped(np, child) { - struct spacemit_pin_mux_config *pinmuxs; - unsigned int config, *pins; - int i, npins; - - npins = of_property_count_u32_elems(child, "pinmux"); - - if (npins < 1) { - dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", - np, child); - return -EINVAL; - } - - grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", - np, child); - if (!grpname) - return -ENOMEM; - - grpnames[ngroups++] = grpname; - - pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); - if (!pins) - return -ENOMEM; - - pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); - if (!pinmuxs) - return -ENOMEM; - - for (i = 0; i < npins; i++) { - ret = of_property_read_u32_index(child, "pinmux", - i, &config); - - if (ret) - return -EINVAL; - - pins[i] = spacemit_dt_get_pin(config); - pinmuxs[i].config = config; - pinmuxs[i].pin = spacemit_get_pin(pctrl, pins[i]); - - if (!pinmuxs[i].pin) - return dev_err_probe(dev, -ENODEV, "failed to get pin %d\n", pins[i]); - } - - ret = spacemit_pctrl_check_power(pctldev, child, pinmuxs, - npins, grpname); - if (ret < 0) - return ret; - - map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; - map[nmaps].data.mux.function = np->name; - map[nmaps].data.mux.group = grpname; - nmaps += 1; - - ret = pinctrl_generic_add_group(pctldev, grpname, - pins, npins, pinmuxs); - if (ret < 0) - return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, ret); - - ret = pinconf_generic_parse_dt_config(child, pctldev, - &map[nmaps].data.configs.configs, - &map[nmaps].data.configs.num_configs); - if (ret) - return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", - grpname); - - if (map[nmaps].data.configs.num_configs == 0) - continue; - - map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - map[nmaps].data.configs.group_or_pin = grpname; - nmaps += 1; - } - - ret = pinmux_generic_add_function(pctldev, np->name, - grpnames, ngroups, NULL); - if (ret < 0) { - pinctrl_utils_free_map(pctldev, map, nmaps); - return dev_err_probe(dev, ret, "error adding function %s\n", np->name); - } - - *maps = map; - *num_maps = nmaps; - - return 0; -} - static const struct pinctrl_ops spacemit_pctrl_ops = { .get_groups_count = pinctrl_generic_get_group_count, .get_group_name = pinctrl_generic_get_group_name, .get_group_pins = pinctrl_generic_get_group_pins, .pin_dbg_show = spacemit_pctrl_dbg_show, - .dt_node_to_map = spacemit_pctrl_dt_node_to_map, + .dt_node_to_map = pinctrl_generic_pinmux_dt_node_to_map, .dt_free_map = pinctrl_utils_free_map, }; @@ -605,8 +444,8 @@ static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, { struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct group_desc *group; - const struct spacemit_pin_mux_config *configs; unsigned int i, mux; + unsigned int *configs; void __iomem *reg; group = pinctrl_generic_get_group(pctldev, gsel); @@ -616,11 +455,17 @@ static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, configs = group->data; for (i = 0; i < group->grp.npins; i++) { - const struct spacemit_pin *spin = configs[i].pin; - u32 value = configs[i].config; + const struct spacemit_pin *spin; + u32 value = configs[i]; + + spin = spacemit_get_pin(pctrl, group->grp.pins[i]); + if (!spin) { + dev_err(pctrl->dev, "Invalid pin %u\n", group->grp.pins[i]); + return -EINVAL; + } reg = spacemit_pin_to_reg(pctrl, spin->pin); - mux = spacemit_dt_get_pin_mux(value); + mux = value; guard(raw_spinlock_irqsave)(&pctrl->lock); value = readl_relaxed(reg) & ~PAD_MUX; @@ -658,13 +503,14 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); int param = pinconf_to_config_param(*config); u32 value, arg = 0; - if (!pin) + if (!spin) return -EINVAL; - value = readl(spacemit_pin_to_reg(pctrl, pin)); + value = readl(spacemit_pin_to_reg(pctrl, spin->pin)); switch (param) { case PIN_CONFIG_SLEW_RATE: @@ -777,9 +623,8 @@ static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, return -EINVAL; } } else { - v &= ~PAD_SLEW_RATE; slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0; - v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate); + FIELD_MODIFY(PAD_SLEW_RATE, &v, slew_rate); } } @@ -795,7 +640,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, void __iomem *reg; unsigned int mux; - if (!pin) + if (!spin) return -EINVAL; reg = spacemit_pin_to_reg(pctrl, spin->pin); @@ -845,6 +690,11 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, if (ret) return ret; + for (i = 0; i < group->grp.npins; i++) { + if (!spacemit_get_pin(pctrl, group->grp.pins[i])) + return -EINVAL; + } + for (i = 0; i < group->grp.npins; i++) spacemit_pin_set_config(pctrl, group->grp.pins[i], value); diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index 1ec22010a3f9..5fcbea32089d 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -339,7 +339,7 @@ static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) if (plgpio->regs.eit == -1) supported_type = IRQ_TYPE_LEVEL_HIGH; else - supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + supported_type = IRQ_TYPE_EDGE_BOTH; if (!(trigger & supported_type)) return -EINVAL; diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c index fb624a051e26..4885648050bf 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1310.c +++ b/drivers/pinctrl/spear/pinctrl-spear1310.c @@ -11,7 +11,6 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c index 48f068cf5e24..f6b681cfe9e8 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1340.c +++ b/drivers/pinctrl/spear/pinctrl-spear1340.c @@ -11,7 +11,6 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c index 7530252ef7bc..4391185d1e46 100644 --- a/drivers/pinctrl/spear/pinctrl-spear300.c +++ b/drivers/pinctrl/spear/pinctrl-spear300.c @@ -11,7 +11,6 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c index c476e5478646..6418bb666bfb 100644 --- a/drivers/pinctrl/spear/pinctrl-spear310.c +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -11,7 +11,6 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c index 401477cfbf57..73a208977600 100644 --- a/drivers/pinctrl/spear/pinctrl-spear320.c +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -11,7 +11,6 @@ #include <linux/err.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-spear3xx.h" diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c index d14f382f2392..e6ca2701dbd1 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c @@ -5,7 +5,6 @@ */ #include <linux/module.h> -#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "pinctrl-sprd.h" diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c index 25cb98d9c54e..37da176cad49 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c @@ -10,7 +10,6 @@ #include <linux/clk.h> #include <linux/gpio/driver.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c index 3433b3c91692..fab18e895330 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c @@ -10,7 +10,6 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c index 44f84e4c29bf..77039012521a 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c @@ -9,7 +9,6 @@ #include <linux/bits.h> #include <linux/gpio/driver.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/spinlock.h> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c index e44480e71ea8..7fcb6cdc1e86 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c @@ -10,7 +10,6 @@ #include <linux/clk.h> #include <linux/gpio/driver.h> #include <linux/io.h> -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> @@ -845,6 +844,7 @@ int jh7110_pinctrl_probe(struct platform_device *pdev) struct jh7110_pinctrl *sfp; struct pinctrl_desc *jh7110_pinctrl_desc; struct reset_control *rst; + unsigned int num_saved_regs; struct clk *clk; int ret; @@ -857,16 +857,12 @@ int jh7110_pinctrl_probe(struct platform_device *pdev) return -EINVAL; } - sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); + num_saved_regs = IS_ENABLED(CONFIG_PM_SLEEP) ? info->nsaved_regs : 0; + sfp = devm_kzalloc(dev, struct_size(sfp, saved_regs, num_saved_regs), + GFP_KERNEL); if (!sfp) return -ENOMEM; - -#if IS_ENABLED(CONFIG_PM_SLEEP) - sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs, - sizeof(*sfp->saved_regs), GFP_KERNEL); - if (!sfp->saved_regs) - return -ENOMEM; -#endif + sfp->num_saved_regs = num_saved_regs; sfp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(sfp->base)) diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h index 2da2d6858008..12568be28527 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h @@ -21,7 +21,8 @@ struct jh7110_pinctrl { /* register read/write mutex */ struct mutex mutex; const struct jh7110_pinctrl_soc_info *info; - u32 *saved_regs; + unsigned int num_saved_regs; + u32 saved_regs[] __counted_by(num_saved_regs); }; struct jh7110_gpio_irq_reg { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c index 69cd2b4ebd7d..e27e4945def2 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -26,8 +26,7 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = static struct sunxi_pinctrl_desc a523_r_pinctrl_data = { .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map), .irq_bank_map = a523_r_irq_bank_map, - .irq_read_needs_mux = true, - .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV, .pin_base = PL_BASE, }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c index 7d2308c37d29..88d8acd5bc24 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c @@ -26,8 +26,7 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = static struct sunxi_pinctrl_desc a523_pinctrl_data = { .irq_banks = ARRAY_SIZE(a523_irq_bank_map), .irq_bank_map = a523_irq_bank_map, - .irq_read_needs_mux = true, - .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV, }; static int a523_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index d3042e0c9712..31cd142ce0f7 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -728,6 +728,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, { unsigned short bank; unsigned long flags; + bool inverted = false; u32 val, reg; int uV; @@ -766,6 +767,9 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, reg &= ~IO_BIAS_MASK; writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); return 0; + case BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV: + inverted = true; + fallthrough; case BIAS_VOLTAGE_PIO_POW_MODE_CTL: val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0; @@ -780,6 +784,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, fallthrough; case BIAS_VOLTAGE_PIO_POW_MODE_SEL: val = uV <= 1800000 ? 1 : 0; + if (inverted) + val = !val; raw_spin_lock_irqsave(&pctl->lock, flags); reg = readl(pctl->membase + pctl->pow_mod_sel_offset); @@ -837,6 +843,21 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, writel((readl(pctl->membase + reg) & ~mask) | config << shift, pctl->membase + reg); + /* + * A pin muxed to gpio_out directly through a pinmux node bypasses + * sunxi_pinctrl_gpio_set() and drives whatever its output latch + * holds. Now that the pin is in output mode the data register + * reads back the latch, so refresh the shadow to keep such pins + * driving their pre-existing level. + */ + if (config == SUN4I_FUNC_OUTPUT) { + u32 *shadow = &pctl->dat_shadow[pin / PINS_PER_BANK]; + + sunxi_data_reg(pctl, pin, ®, &shift, &mask); + *shadow = (*shadow & ~mask) | + (readl(pctl->membase + reg) & mask); + } + raw_spin_unlock_irqrestore(&pctl->lock, flags); } @@ -925,7 +946,7 @@ static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) return 0; out: - regulator_put(s_reg->regulator); + regulator_put(reg); return ret; } @@ -1017,21 +1038,29 @@ static int sunxi_pinctrl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); - u32 reg, shift, mask, val; + u32 *shadow = &pctl->dat_shadow[offset / PINS_PER_BANK]; + u32 reg, shift, mask; unsigned long flags; sunxi_data_reg(pctl, offset, ®, &shift, &mask); raw_spin_lock_irqsave(&pctl->lock, flags); - val = readl(pctl->membase + reg); - + /* + * Reading the data register returns the pin level, not the output + * latch, for pins muxed as inputs. A read-modify-write based on + * the register would therefore corrupt the latches of input-muxed + * pins in the same bank (e.g. an emulated open-drain I2C line + * released high), making them drive the wrong level once switched + * to output. Base the read-modify-write on a shadow copy of the + * latches instead. + */ if (value) - val |= mask; + *shadow |= mask; else - val &= ~mask; + *shadow &= ~mask; - writel(val, pctl->membase + reg); + writel(*shadow, pctl->membase + reg); raw_spin_unlock_irqrestore(&pctl->lock, flags); @@ -1572,7 +1601,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, struct pinctrl_pin_desc *pins; struct sunxi_pinctrl *pctl; struct pinmux_ops *pmxops; - int i, ret, last_pin, pin_idx; + int i, ret, last_pin, pin_idx, nbanks; struct clk *clk; pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); @@ -1610,6 +1639,37 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, if (!pctl->irq_array) return -ENOMEM; + /* + * The bus clock has to be enabled before the pinctrl device + * registers, as the pin hogs claimed from there access registers. + */ + ret = of_clk_get_parent_count(node); + clk = devm_clk_get_enabled(&pdev->dev, ret == 1 ? NULL : "apb"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + /* + * Seed the output latch shadow from the hardware so pins the + * bootloader left in output mode keep their state; see + * sunxi_pinctrl_gpio_set() for why a shadow is needed. This must + * happen before the pinctrl device registers, as pin hogs can mux + * pins to gpio_out and thereby update the shadow. + */ + last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; + nbanks = DIV_ROUND_UP(last_pin + 1 - pctl->desc->pin_base, + PINS_PER_BANK); + pctl->dat_shadow = devm_kcalloc(&pdev->dev, nbanks, + sizeof(*pctl->dat_shadow), GFP_KERNEL); + if (!pctl->dat_shadow) + return -ENOMEM; + + for (i = 0; i < nbanks; i++) { + u32 reg, shift, mask; + + sunxi_data_reg(pctl, i * PINS_PER_BANK, ®, &shift, &mask); + pctl->dat_shadow[i] = readl(pctl->membase + reg); + } + ret = sunxi_pinctrl_build_state(pdev); if (ret) { dev_err(&pdev->dev, "dt probe failed: %d\n", ret); @@ -1665,7 +1725,6 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, if (!pctl->chip) return -ENOMEM; - last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; pctl->chip->owner = THIS_MODULE; pctl->chip->request = gpiochip_generic_request; pctl->chip->free = gpiochip_generic_free; @@ -1699,13 +1758,6 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, goto gpiochip_error; } - ret = of_clk_get_parent_count(node); - clk = devm_clk_get_enabled(&pdev->dev, ret == 1 ? NULL : "apb"); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - goto gpiochip_error; - } - pctl->irq = devm_kcalloc(&pdev->dev, pctl->desc->irq_banks, sizeof(*pctl->irq), diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 0daf7600e2fb..8bd00c6ff628 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -85,6 +85,7 @@ #define IO_BIAS_MASK GENMASK(3, 0) #define SUN4I_FUNC_INPUT 0 +#define SUN4I_FUNC_OUTPUT 1 #define SUN4I_FUNC_IRQ 6 #define SUN4I_FUNC_DISABLED_OLD 7 #define SUN4I_FUNC_DISABLED_NEW 15 @@ -116,8 +117,10 @@ enum sunxi_desc_bias_voltage { * Bias voltage is set through PIO_POW_MOD_SEL_REG * and PIO_POW_MOD_CTL_REG register, as seen on * A100 and D1 SoC, for example. + * Some SoCs invert the encoding for 1.8V vs. 3.3V. */ BIAS_VOLTAGE_PIO_POW_MODE_CTL, + BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV, }; struct sunxi_desc_function { @@ -175,6 +178,12 @@ struct sunxi_pinctrl { int *irq; unsigned *irq_array; raw_spinlock_t lock; + /* + * Output latch shadow, one word per bank. Seeded lockless at + * probe before the pinctrl device registers, protected by @lock + * afterwards. + */ + u32 *dat_shadow; struct pinctrl_dev *pctl_dev; unsigned long flags; u32 bank_mem_size; diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig index 660d101ea367..39a93733efa2 100644 --- a/drivers/pinctrl/tegra/Kconfig +++ b/drivers/pinctrl/tegra/Kconfig @@ -1,43 +1,67 @@ # SPDX-License-Identifier: GPL-2.0-only config PINCTRL_TEGRA - bool + bool "NVIDIA Tegra pin controllers common" if COMPILE_TEST && !ARCH_TEGRA select PINMUX select PINCONF config PINCTRL_TEGRA20 - bool + bool "NVIDIA Tegra20 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA + depends on COMMON_CLK config PINCTRL_TEGRA30 - bool + bool "NVIDIA Tegra30 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA114 - bool + bool "NVIDIA Tegra114 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA124 - bool + bool "NVIDIA Tegra124 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA210 - bool + bool "NVIDIA Tegra210 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA186 - bool + bool "NVIDIA Tegra186 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA194 - bool + bool "NVIDIA Tegra194 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA config PINCTRL_TEGRA234 - bool + bool "NVIDIA Tegra234 pin controller" if COMPILE_TEST && !ARCH_TEGRA select PINCTRL_TEGRA +config PINCTRL_TEGRA238 + tristate "NVIDIA Tegra238 pinctrl driver" + depends on ARCH_TEGRA || COMPILE_TEST + default m if ARCH_TEGRA_238_SOC + select PINCTRL_TEGRA + help + Say Y or M here to enable support for the pinctrl driver for + NVIDIA Tegra238 SoC. This driver controls the pin multiplexing + and configuration for the MAIN and AON pin controllers found + on Tegra238. + +config PINCTRL_TEGRA264 + tristate "NVIDIA Tegra264 pinctrl driver" + depends on ARCH_TEGRA || COMPILE_TEST + default m if ARCH_TEGRA_264_SOC + select PINCTRL_TEGRA + help + Say Y or M here to enable support for the pinctrl driver for + NVIDIA Tegra264 SoC. This driver controls the pin multiplexing + and configuration for the MAIN, AON and UPHY pin controllers found + on Tegra264. + config PINCTRL_TEGRA_XUSB - def_bool y if ARCH_TEGRA + bool "NVIDIA Tegra XUSB pin controller" if COMPILE_TEST && !ARCH_TEGRA + default y if ARCH_TEGRA select GENERIC_PHY select PINCONF select PINMUX diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile index 82176526549e..71ade768bf9c 100644 --- a/drivers/pinctrl/tegra/Makefile +++ b/drivers/pinctrl/tegra/Makefile @@ -8,4 +8,6 @@ obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o obj-$(CONFIG_PINCTRL_TEGRA186) += pinctrl-tegra186.o obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o +obj-$(CONFIG_PINCTRL_TEGRA238) += pinctrl-tegra238.o +obj-$(CONFIG_PINCTRL_TEGRA264) += pinctrl-tegra264.o obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index bac2adeb5c63..3f58f7db525f 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -13,6 +13,7 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/seq_file.h> @@ -936,3 +937,4 @@ int tegra_pinctrl_probe(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_GPL(tegra_pinctrl_probe); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra234.c b/drivers/pinctrl/tegra/pinctrl-tegra234.c index 86c2b84e792d..fb9feae590f8 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra234.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra234.c @@ -5,7 +5,6 @@ * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved. */ -#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra238.c b/drivers/pinctrl/tegra/pinctrl-tegra238.c new file mode 100644 index 000000000000..40aba285944e --- /dev/null +++ b/drivers/pinctrl/tegra/pinctrl-tegra238.c @@ -0,0 +1,2079 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl data for the NVIDIA Tegra238 pinmux + * + * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-tegra.h" + +/* Define unique ID for each pins */ +enum { + TEGRA_PIN_GPU_PWR_REQ_PA0, + TEGRA_PIN_GP_PWM5_PA1, + TEGRA_PIN_GP_PWM6_PA2, + TEGRA_PIN_SPI3_SCK_PA3, + TEGRA_PIN_SPI3_MISO_PA4, + TEGRA_PIN_SPI3_MOSI_PA5, + TEGRA_PIN_SPI3_CS0_PA6, + TEGRA_PIN_SPI3_CS1_PA7, + TEGRA_PIN_SPI1_SCK_PB0, + TEGRA_PIN_SPI1_MISO_PB1, + TEGRA_PIN_SPI1_MOSI_PB2, + TEGRA_PIN_SPI1_CS0_PB3, + TEGRA_PIN_SPI1_CS1_PB4, + TEGRA_PIN_PWR_I2C_SCL_PC0, + TEGRA_PIN_PWR_I2C_SDA_PC1, + TEGRA_PIN_EXTPERIPH1_CLK_PC2, + TEGRA_PIN_EXTPERIPH2_CLK_PC3, + TEGRA_PIN_CAM_I2C_SCL_PC4, + TEGRA_PIN_CAM_I2C_SDA_PC5, + TEGRA_PIN_SOC_GPIO23_PC6, + TEGRA_PIN_SOC_GPIO24_PC7, + TEGRA_PIN_SOC_GPIO27_PD0, + TEGRA_PIN_SOC_GPIO55_PD1, + TEGRA_PIN_SOC_GPIO29_PD2, + TEGRA_PIN_SOC_GPIO33_PD3, + TEGRA_PIN_SOC_GPIO32_PD4, + TEGRA_PIN_SOC_GPIO35_PD5, + TEGRA_PIN_SOC_GPIO37_PD6, + TEGRA_PIN_SOC_GPIO56_PD7, + TEGRA_PIN_UART1_TX_PE0, + TEGRA_PIN_UART1_RX_PE1, + TEGRA_PIN_UART1_RTS_PE2, + TEGRA_PIN_UART1_CTS_PE3, + TEGRA_PIN_SOC_GPIO13_PF0, + TEGRA_PIN_SOC_GPIO14_PF1, + TEGRA_PIN_SOC_GPIO15_PF2, + TEGRA_PIN_SOC_GPIO16_PF3, + TEGRA_PIN_SOC_GPIO17_PF4, + TEGRA_PIN_SOC_GPIO18_PF5, + TEGRA_PIN_SOC_GPIO20_PF6, + TEGRA_PIN_SOC_GPIO21_PF7, + TEGRA_PIN_SOC_GPIO22_PG0, + TEGRA_PIN_SOC_GPIO06_PG1, + TEGRA_PIN_UART4_TX_PG2, + TEGRA_PIN_UART4_RX_PG3, + TEGRA_PIN_UART4_RTS_PG4, + TEGRA_PIN_UART4_CTS_PG5, + TEGRA_PIN_SOC_GPIO41_PG6, + TEGRA_PIN_SOC_GPIO42_PG7, + TEGRA_PIN_SOC_GPIO43_PH0, + TEGRA_PIN_SOC_GPIO44_PH1, + TEGRA_PIN_GEN1_I2C_SCL_PH2, + TEGRA_PIN_GEN1_I2C_SDA_PH3, + TEGRA_PIN_CPU_PWR_REQ_PH4, + TEGRA_PIN_SOC_GPIO07_PH5, + TEGRA_PIN_DAP3_CLK_PJ0, + TEGRA_PIN_DAP3_DOUT_PJ1, + TEGRA_PIN_DAP3_DIN_PJ2, + TEGRA_PIN_DAP3_FS_PJ3, + TEGRA_PIN_SOC_GPIO57_PJ4, + TEGRA_PIN_SOC_GPIO58_PJ5, + TEGRA_PIN_SOC_GPIO59_PJ6, + TEGRA_PIN_SOC_GPIO60_PJ7, + TEGRA_PIN_SOC_GPIO45_PK0, + TEGRA_PIN_SOC_GPIO46_PK1, + TEGRA_PIN_SOC_GPIO47_PK2, + TEGRA_PIN_SOC_GPIO48_PK3, + TEGRA_PIN_QSPI0_SCK_PL0, + TEGRA_PIN_QSPI0_IO0_PL1, + TEGRA_PIN_QSPI0_IO1_PL2, + TEGRA_PIN_QSPI0_CS_N_PL3, + TEGRA_PIN_SOC_GPIO152_PL4, + TEGRA_PIN_SOC_GPIO153_PL5, + TEGRA_PIN_SOC_GPIO154_PL6, + TEGRA_PIN_SOC_GPIO155_PL7, + TEGRA_PIN_SOC_GPIO156_PM0, + TEGRA_PIN_SOC_GPIO157_PM1, + TEGRA_PIN_SOC_GPIO158_PM2, + TEGRA_PIN_SOC_GPIO159_PM3, + TEGRA_PIN_SOC_GPIO160_PM4, + TEGRA_PIN_SOC_GPIO161_PM5, + TEGRA_PIN_SOC_GPIO162_PM6, + TEGRA_PIN_UART7_TX_PM7, + TEGRA_PIN_UART7_RX_PN0, + TEGRA_PIN_UART7_RTS_PN1, + TEGRA_PIN_UART7_CTS_PN2, + TEGRA_PIN_SOC_GPIO167_PP0, + TEGRA_PIN_SOC_GPIO168_PP1, + TEGRA_PIN_SOC_GPIO169_PP2, + TEGRA_PIN_SOC_GPIO170_PP3, + TEGRA_PIN_DAP4_SCLK_PP4, + TEGRA_PIN_DAP4_DOUT_PP5, + TEGRA_PIN_DAP4_DIN_PP6, + TEGRA_PIN_DAP4_FS_PP7, + TEGRA_PIN_SOC_GPIO171_PQ0, + TEGRA_PIN_SOC_GPIO172_PQ1, + TEGRA_PIN_SOC_GPIO173_PQ2, + TEGRA_PIN_SOC_GPIO61_PR0, + TEGRA_PIN_SOC_GPIO62_PR1, + TEGRA_PIN_SOC_GPIO63_PR2, + TEGRA_PIN_SOC_GPIO64_PR3, + TEGRA_PIN_SOC_GPIO65_PR4, + TEGRA_PIN_SOC_GPIO66_PR5, + TEGRA_PIN_SOC_GPIO67_PR6, + TEGRA_PIN_SOC_GPIO68_PR7, + TEGRA_PIN_GEN4_I2C_SCL_PS0, + TEGRA_PIN_GEN4_I2C_SDA_PS1, + TEGRA_PIN_SOC_GPIO75_PS2, + TEGRA_PIN_GEN7_I2C_SCL_PS3, + TEGRA_PIN_GEN7_I2C_SDA_PS4, + TEGRA_PIN_SOC_GPIO78_PS5, + TEGRA_PIN_GEN9_I2C_SCL_PS6, + TEGRA_PIN_GEN9_I2C_SDA_PS7, + TEGRA_PIN_SOC_GPIO81_PT0, + TEGRA_PIN_SOC_GPIO36_PT1, + TEGRA_PIN_SOC_GPIO53_PT2, + TEGRA_PIN_SOC_GPIO38_PT3, + TEGRA_PIN_SOC_GPIO40_PT4, + TEGRA_PIN_SOC_GPIO34_PT5, + TEGRA_PIN_USB_VBUS_EN0_PT6, + TEGRA_PIN_USB_VBUS_EN1_PT7, + TEGRA_PIN_SDMMC1_CLK_PU0, + TEGRA_PIN_SDMMC1_CMD_PU1, + TEGRA_PIN_SDMMC1_DAT0_PU2, + TEGRA_PIN_SDMMC1_DAT1_PU3, + TEGRA_PIN_SDMMC1_DAT2_PU4, + TEGRA_PIN_SDMMC1_DAT3_PU5, + TEGRA_PIN_UFS0_REF_CLK_PV0, + TEGRA_PIN_UFS0_RST_N_PV1, + TEGRA_PIN_PEX_L0_CLKREQ_N_PW0, + TEGRA_PIN_PEX_L0_RST_N_PW1, + TEGRA_PIN_PEX_L1_CLKREQ_N_PW2, + TEGRA_PIN_PEX_L1_RST_N_PW3, + TEGRA_PIN_PEX_L2_CLKREQ_N_PW4, + TEGRA_PIN_PEX_L2_RST_N_PW5, + TEGRA_PIN_PEX_L3_CLKREQ_N_PW6, + TEGRA_PIN_PEX_L3_RST_N_PW7, + TEGRA_PIN_PEX_WAKE_N_PX0, + TEGRA_PIN_DP_AUX_CH0_HPD_PX1, + TEGRA_PIN_SDMMC1_COMP, +}; + +enum { + TEGRA_PIN_BOOTV_CTL_N_PAA0, + TEGRA_PIN_SOC_GPIO00_PAA1, + TEGRA_PIN_VCOMP_ALERT_PAA2, + TEGRA_PIN_PWM1_PAA3, + TEGRA_PIN_BATT_OC_PAA4, + TEGRA_PIN_SOC_GPIO04_PAA5, + TEGRA_PIN_SOC_GPIO25_PAA6, + TEGRA_PIN_SOC_GPIO26_PAA7, + TEGRA_PIN_HDMI_CEC_PBB0, + TEGRA_PIN_SPI2_SCK_PCC0, + TEGRA_PIN_SPI2_MISO_PCC1, + TEGRA_PIN_SPI2_MOSI_PCC2, + TEGRA_PIN_SPI2_CS0_PCC3, + TEGRA_PIN_SPI2_CS1_PCC4, + TEGRA_PIN_UART3_TX_PCC5, + TEGRA_PIN_UART3_RX_PCC6, + TEGRA_PIN_GEN2_I2C_SCL_PCC7, + TEGRA_PIN_GEN2_I2C_SDA_PDD0, + TEGRA_PIN_GEN8_I2C_SCL_PDD1, + TEGRA_PIN_GEN8_I2C_SDA_PDD2, + TEGRA_PIN_TOUCH_CLK_PDD3, + TEGRA_PIN_DMIC1_CLK_PDD4, + TEGRA_PIN_DMIC1_DAT_PDD5, + TEGRA_PIN_SOC_GPIO19_PDD6, + TEGRA_PIN_PWM2_PDD7, + TEGRA_PIN_PWM3_PEE0, + TEGRA_PIN_PWM7_PEE1, + TEGRA_PIN_SOC_GPIO49_PEE2, + TEGRA_PIN_SOC_GPIO82_PEE3, + TEGRA_PIN_SOC_GPIO50_PEE4, + TEGRA_PIN_SOC_GPIO83_PEE5, + TEGRA_PIN_SOC_GPIO69_PFF0, + TEGRA_PIN_SOC_GPIO70_PFF1, + TEGRA_PIN_SOC_GPIO71_PFF2, + TEGRA_PIN_SOC_GPIO72_PFF3, + TEGRA_PIN_SOC_GPIO73_PFF4, + TEGRA_PIN_SOC_GPIO74_PFF5, + TEGRA_PIN_SOC_GPIO80_PFF6, + TEGRA_PIN_SOC_GPIO76_PFF7, + TEGRA_PIN_SOC_GPIO77_PGG0, + TEGRA_PIN_SOC_GPIO84_PGG1, + TEGRA_PIN_UART2_TX_PGG2, + TEGRA_PIN_UART2_RX_PGG3, + TEGRA_PIN_UART2_RTS_PGG4, + TEGRA_PIN_UART2_CTS_PGG5, + TEGRA_PIN_SOC_GPIO85_PGG6, + TEGRA_PIN_UART5_TX_PGG7, + TEGRA_PIN_UART5_RX_PHH0, + TEGRA_PIN_UART5_RTS_PHH1, + TEGRA_PIN_UART5_CTS_PHH2, + TEGRA_PIN_SOC_GPIO86_PHH3, +}; + +/* Table for pin descriptor */ +static const struct pinctrl_pin_desc tegra238_pins[] = { + PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PA0, "GPU_PWR_REQ_PA0"), + PINCTRL_PIN(TEGRA_PIN_GP_PWM5_PA1, "GP_PWM5_PA1"), + PINCTRL_PIN(TEGRA_PIN_GP_PWM6_PA2, "GP_PWM6_PA2"), + PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PA3, "SPI3_SCK_PA3"), + PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PA4, "SPI3_MISO_PA4"), + PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PA5, "SPI3_MOSI_PA5"), + PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PA6, "SPI3_CS0_PA6"), + PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PA7, "SPI3_CS1_PA7"), + PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PB0, "SPI1_SCK_PB0"), + PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PB1, "SPI1_MISO_PB1"), + PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PB2, "SPI1_MOSI_PB2"), + PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PB3, "SPI1_CS0_PB3"), + PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PB4, "SPI1_CS1_PB4"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PC0, "PWR_I2C_SCL_PC0"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PC1, "PWR_I2C_SDA_PC1"), + PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PC2, "EXTPERIPH1_CLK_PC2"), + PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PC3, "EXTPERIPH2_CLK_PC3"), + PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PC4, "CAM_I2C_SCL_PC4"), + PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PC5, "CAM_I2C_SDA_PC5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PC6, "SOC_GPIO23_PC6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PC7, "SOC_GPIO24_PC7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PD0, "SOC_GPIO27_PD0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PD1, "SOC_GPIO55_PD1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PD2, "SOC_GPIO29_PD2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PD3, "SOC_GPIO33_PD3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PD4, "SOC_GPIO32_PD4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO35_PD5, "SOC_GPIO35_PD5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO37_PD6, "SOC_GPIO37_PD6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO56_PD7, "SOC_GPIO56_PD7"), + PINCTRL_PIN(TEGRA_PIN_UART1_TX_PE0, "UART1_TX_PE0"), + PINCTRL_PIN(TEGRA_PIN_UART1_RX_PE1, "UART1_RX_PE1"), + PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PE2, "UART1_RTS_PE2"), + PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PE3, "UART1_CTS_PE3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PF0, "SOC_GPIO13_PF0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PF1, "SOC_GPIO14_PF1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO15_PF2, "SOC_GPIO15_PF2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO16_PF3, "SOC_GPIO16_PF3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO17_PF4, "SOC_GPIO17_PF4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO18_PF5, "SOC_GPIO18_PF5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PF6, "SOC_GPIO20_PF6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PF7, "SOC_GPIO21_PF7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PG0, "SOC_GPIO22_PG0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PG1, "SOC_GPIO06_PG1"), + PINCTRL_PIN(TEGRA_PIN_UART4_TX_PG2, "UART4_TX_PG2"), + PINCTRL_PIN(TEGRA_PIN_UART4_RX_PG3, "UART4_RX_PG3"), + PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PG4, "UART4_RTS_PG4"), + PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PG5, "UART4_CTS_PG5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PG6, "SOC_GPIO41_PG6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PG7, "SOC_GPIO42_PG7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PH0, "SOC_GPIO43_PH0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PH1, "SOC_GPIO44_PH1"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PH2, "GEN1_I2C_SCL_PH2"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PH3, "GEN1_I2C_SDA_PH3"), + PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH4, "CPU_PWR_REQ_PH4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PH5, "SOC_GPIO07_PH5"), + PINCTRL_PIN(TEGRA_PIN_DAP3_CLK_PJ0, "DAP3_CLK_PJ0"), + PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PJ1, "DAP3_DOUT_PJ1"), + PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PJ2, "DAP3_DIN_PJ2"), + PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PJ3, "DAP3_FS_PJ3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO57_PJ4, "SOC_GPIO57_PJ4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO58_PJ5, "SOC_GPIO58_PJ5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO59_PJ6, "SOC_GPIO59_PJ6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO60_PJ7, "SOC_GPIO60_PJ7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PK0, "SOC_GPIO45_PK0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO46_PK1, "SOC_GPIO46_PK1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO47_PK2, "SOC_GPIO47_PK2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO48_PK3, "SOC_GPIO48_PK3"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PL0, "QSPI0_SCK_PL0"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PL1, "QSPI0_IO0_PL1"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PL2, "QSPI0_IO1_PL2"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PL3, "QSPI0_CS_N_PL3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PL4, "SOC_GPIO152_PL4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PL5, "SOC_GPIO153_PL5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO154_PL6, "SOC_GPIO154_PL6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PL7, "SOC_GPIO155_PL7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO156_PM0, "SOC_GPIO156_PM0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO157_PM1, "SOC_GPIO157_PM1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO158_PM2, "SOC_GPIO158_PM2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO159_PM3, "SOC_GPIO159_PM3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO160_PM4, "SOC_GPIO160_PM4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO161_PM5, "SOC_GPIO161_PM5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO162_PM6, "SOC_GPIO162_PM6"), + PINCTRL_PIN(TEGRA_PIN_UART7_TX_PM7, "UART7_TX_PM7"), + PINCTRL_PIN(TEGRA_PIN_UART7_RX_PN0, "UART7_RX_PN0"), + PINCTRL_PIN(TEGRA_PIN_UART7_RTS_PN1, "UART7_RTS_PN1"), + PINCTRL_PIN(TEGRA_PIN_UART7_CTS_PN2, "UART7_CTS_PN2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO167_PP0, "SOC_GPIO167_PP0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO168_PP1, "SOC_GPIO168_PP1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO169_PP2, "SOC_GPIO169_PP2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PP3, "SOC_GPIO170_PP3"), + PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP4, "DAP4_SCLK_PP4"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP5, "DAP4_DOUT_PP5"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP6, "DAP4_DIN_PP6"), + PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP7, "DAP4_FS_PP7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PQ0, "SOC_GPIO171_PQ0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PQ1, "SOC_GPIO172_PQ1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PQ2, "SOC_GPIO173_PQ2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO61_PR0, "SOC_GPIO61_PR0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO62_PR1, "SOC_GPIO62_PR1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO63_PR2, "SOC_GPIO63_PR2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO64_PR3, "SOC_GPIO64_PR3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO65_PR4, "SOC_GPIO65_PR4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO66_PR5, "SOC_GPIO66_PR5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO67_PR6, "SOC_GPIO67_PR6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO68_PR7, "SOC_GPIO68_PR7"), + PINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SCL_PS0, "GEN4_I2C_SCL_PS0"), + PINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SDA_PS1, "GEN4_I2C_SDA_PS1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO75_PS2, "SOC_GPIO75_PS2"), + PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PS3, "GEN7_I2C_SCL_PS3"), + PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PS4, "GEN7_I2C_SDA_PS4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO78_PS5, "SOC_GPIO78_PS5"), + PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PS6, "GEN9_I2C_SCL_PS6"), + PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PS7, "GEN9_I2C_SDA_PS7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO81_PT0, "SOC_GPIO81_PT0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO36_PT1, "SOC_GPIO36_PT1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PT2, "SOC_GPIO53_PT2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO38_PT3, "SOC_GPIO38_PT3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PT4, "SOC_GPIO40_PT4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO34_PT5, "SOC_GPIO34_PT5"), + PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PT6, "USB_VBUS_EN0_PT6"), + PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PT7, "USB_VBUS_EN1_PT7"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PU0, "SDMMC1_CLK_PU0"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PU1, "SDMMC1_CMD_PU1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PU2, "SDMMC1_DAT0_PU2"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PU3, "SDMMC1_DAT1_PU3"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PU4, "SDMMC1_DAT2_PU4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PU5, "SDMMC1_DAT3_PU5"), + PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PV0, "UFS0_REF_CLK_PV0"), + PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PV1, "UFS0_RST_N_PV1"), + PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PW0, "PEX_L0_CLKREQ_N_PW0"), + PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PW1, "PEX_L0_RST_N_PW1"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PW2, "PEX_L1_CLKREQ_N_PW2"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PW3, "PEX_L1_RST_N_PW3"), + PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PW4, "PEX_L2_CLKREQ_N_PW4"), + PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PW5, "PEX_L2_RST_N_PW5"), + PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PW6, "PEX_L3_CLKREQ_N_PW6"), + PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PW7, "PEX_L3_RST_N_PW7"), + PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PX0, "PEX_WAKE_N_PX0"), + PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PX1, "DP_AUX_CH0_HPD_PX1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"), +}; + +static const struct pinctrl_pin_desc tegra238_aon_pins[] = { + PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA0, "BOOTV_CTL_N_PAA0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA1, "SOC_GPIO00_PAA1"), + PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA2, "VCOMP_ALERT_PAA2"), + PINCTRL_PIN(TEGRA_PIN_PWM1_PAA3, "PWM1_PAA3"), + PINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA4, "BATT_OC_PAA4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PAA5, "SOC_GPIO04_PAA5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PAA6, "SOC_GPIO25_PAA6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PAA7, "SOC_GPIO26_PAA7"), + PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PBB0, "HDMI_CEC_PBB0"), + PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"), + PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"), + PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PCC4, "SPI2_CS1_PCC4"), + PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"), + PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"), + PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"), + PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"), + PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PDD3, "TOUCH_CLK_PDD3"), + PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PDD4, "DMIC1_CLK_PDD4"), + PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PDD5, "DMIC1_DAT_PDD5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO19_PDD6, "SOC_GPIO19_PDD6"), + PINCTRL_PIN(TEGRA_PIN_PWM2_PDD7, "PWM2_PDD7"), + PINCTRL_PIN(TEGRA_PIN_PWM3_PEE0, "PWM3_PEE0"), + PINCTRL_PIN(TEGRA_PIN_PWM7_PEE1, "PWM7_PEE1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO49_PEE2, "SOC_GPIO49_PEE2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO82_PEE3, "SOC_GPIO82_PEE3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PEE4, "SOC_GPIO50_PEE4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO83_PEE5, "SOC_GPIO83_PEE5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO69_PFF0, "SOC_GPIO69_PFF0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO70_PFF1, "SOC_GPIO70_PFF1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO71_PFF2, "SOC_GPIO71_PFF2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO72_PFF3, "SOC_GPIO72_PFF3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO73_PFF4, "SOC_GPIO73_PFF4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO74_PFF5, "SOC_GPIO74_PFF5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO80_PFF6, "SOC_GPIO80_PFF6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO76_PFF7, "SOC_GPIO76_PFF7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO77_PGG0, "SOC_GPIO77_PGG0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO84_PGG1, "SOC_GPIO84_PGG1"), + PINCTRL_PIN(TEGRA_PIN_UART2_TX_PGG2, "UART2_TX_PGG2"), + PINCTRL_PIN(TEGRA_PIN_UART2_RX_PGG3, "UART2_RX_PGG3"), + PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PGG4, "UART2_RTS_PGG4"), + PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PGG5, "UART2_CTS_PGG5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO85_PGG6, "SOC_GPIO85_PGG6"), + PINCTRL_PIN(TEGRA_PIN_UART5_TX_PGG7, "UART5_TX_PGG7"), + PINCTRL_PIN(TEGRA_PIN_UART5_RX_PHH0, "UART5_RX_PHH0"), + PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PHH1, "UART5_RTS_PHH1"), + PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PHH2, "UART5_CTS_PHH2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO86_PHH3, "SOC_GPIO86_PHH3"), +}; + +static const unsigned int gpu_pwr_req_pa0_pins[] = { + TEGRA_PIN_GPU_PWR_REQ_PA0, +}; + +static const unsigned int gp_pwm5_pa1_pins[] = { + TEGRA_PIN_GP_PWM5_PA1, +}; + +static const unsigned int gp_pwm6_pa2_pins[] = { + TEGRA_PIN_GP_PWM6_PA2, +}; + +static const unsigned int spi3_sck_pa3_pins[] = { + TEGRA_PIN_SPI3_SCK_PA3, +}; + +static const unsigned int spi3_miso_pa4_pins[] = { + TEGRA_PIN_SPI3_MISO_PA4, +}; + +static const unsigned int spi3_mosi_pa5_pins[] = { + TEGRA_PIN_SPI3_MOSI_PA5, +}; + +static const unsigned int spi3_cs0_pa6_pins[] = { + TEGRA_PIN_SPI3_CS0_PA6, +}; + +static const unsigned int spi3_cs1_pa7_pins[] = { + TEGRA_PIN_SPI3_CS1_PA7, +}; + +static const unsigned int spi1_sck_pb0_pins[] = { + TEGRA_PIN_SPI1_SCK_PB0, +}; + +static const unsigned int spi1_miso_pb1_pins[] = { + TEGRA_PIN_SPI1_MISO_PB1, +}; + +static const unsigned int spi1_mosi_pb2_pins[] = { + TEGRA_PIN_SPI1_MOSI_PB2, +}; + +static const unsigned int spi1_cs0_pb3_pins[] = { + TEGRA_PIN_SPI1_CS0_PB3, +}; + +static const unsigned int spi1_cs1_pb4_pins[] = { + TEGRA_PIN_SPI1_CS1_PB4, +}; + +static const unsigned int pwr_i2c_scl_pc0_pins[] = { + TEGRA_PIN_PWR_I2C_SCL_PC0, +}; + +static const unsigned int pwr_i2c_sda_pc1_pins[] = { + TEGRA_PIN_PWR_I2C_SDA_PC1, +}; + +static const unsigned int extperiph1_clk_pc2_pins[] = { + TEGRA_PIN_EXTPERIPH1_CLK_PC2, +}; + +static const unsigned int extperiph2_clk_pc3_pins[] = { + TEGRA_PIN_EXTPERIPH2_CLK_PC3, +}; + +static const unsigned int cam_i2c_scl_pc4_pins[] = { + TEGRA_PIN_CAM_I2C_SCL_PC4, +}; + +static const unsigned int cam_i2c_sda_pc5_pins[] = { + TEGRA_PIN_CAM_I2C_SDA_PC5, +}; + +static const unsigned int soc_gpio23_pc6_pins[] = { + TEGRA_PIN_SOC_GPIO23_PC6, +}; + +static const unsigned int soc_gpio24_pc7_pins[] = { + TEGRA_PIN_SOC_GPIO24_PC7, +}; + +static const unsigned int soc_gpio27_pd0_pins[] = { + TEGRA_PIN_SOC_GPIO27_PD0, +}; + +static const unsigned int soc_gpio55_pd1_pins[] = { + TEGRA_PIN_SOC_GPIO55_PD1, +}; + +static const unsigned int soc_gpio29_pd2_pins[] = { + TEGRA_PIN_SOC_GPIO29_PD2, +}; + +static const unsigned int soc_gpio33_pd3_pins[] = { + TEGRA_PIN_SOC_GPIO33_PD3, +}; + +static const unsigned int soc_gpio32_pd4_pins[] = { + TEGRA_PIN_SOC_GPIO32_PD4, +}; + +static const unsigned int soc_gpio35_pd5_pins[] = { + TEGRA_PIN_SOC_GPIO35_PD5, +}; + +static const unsigned int soc_gpio37_pd6_pins[] = { + TEGRA_PIN_SOC_GPIO37_PD6, +}; + +static const unsigned int soc_gpio56_pd7_pins[] = { + TEGRA_PIN_SOC_GPIO56_PD7, +}; + +static const unsigned int uart1_tx_pe0_pins[] = { + TEGRA_PIN_UART1_TX_PE0, +}; + +static const unsigned int uart1_rx_pe1_pins[] = { + TEGRA_PIN_UART1_RX_PE1, +}; + +static const unsigned int uart1_rts_pe2_pins[] = { + TEGRA_PIN_UART1_RTS_PE2, +}; + +static const unsigned int uart1_cts_pe3_pins[] = { + TEGRA_PIN_UART1_CTS_PE3, +}; + +static const unsigned int soc_gpio13_pf0_pins[] = { + TEGRA_PIN_SOC_GPIO13_PF0, +}; + +static const unsigned int soc_gpio14_pf1_pins[] = { + TEGRA_PIN_SOC_GPIO14_PF1, +}; + +static const unsigned int soc_gpio15_pf2_pins[] = { + TEGRA_PIN_SOC_GPIO15_PF2, +}; + +static const unsigned int soc_gpio16_pf3_pins[] = { + TEGRA_PIN_SOC_GPIO16_PF3, +}; + +static const unsigned int soc_gpio17_pf4_pins[] = { + TEGRA_PIN_SOC_GPIO17_PF4, +}; + +static const unsigned int soc_gpio18_pf5_pins[] = { + TEGRA_PIN_SOC_GPIO18_PF5, +}; + +static const unsigned int soc_gpio20_pf6_pins[] = { + TEGRA_PIN_SOC_GPIO20_PF6, +}; + +static const unsigned int soc_gpio21_pf7_pins[] = { + TEGRA_PIN_SOC_GPIO21_PF7, +}; + +static const unsigned int soc_gpio22_pg0_pins[] = { + TEGRA_PIN_SOC_GPIO22_PG0, +}; + +static const unsigned int soc_gpio06_pg1_pins[] = { + TEGRA_PIN_SOC_GPIO06_PG1, +}; + +static const unsigned int uart4_tx_pg2_pins[] = { + TEGRA_PIN_UART4_TX_PG2, +}; + +static const unsigned int uart4_rx_pg3_pins[] = { + TEGRA_PIN_UART4_RX_PG3, +}; + +static const unsigned int uart4_rts_pg4_pins[] = { + TEGRA_PIN_UART4_RTS_PG4, +}; + +static const unsigned int uart4_cts_pg5_pins[] = { + TEGRA_PIN_UART4_CTS_PG5, +}; + +static const unsigned int soc_gpio41_pg6_pins[] = { + TEGRA_PIN_SOC_GPIO41_PG6, +}; + +static const unsigned int soc_gpio42_pg7_pins[] = { + TEGRA_PIN_SOC_GPIO42_PG7, +}; + +static const unsigned int soc_gpio43_ph0_pins[] = { + TEGRA_PIN_SOC_GPIO43_PH0, +}; + +static const unsigned int soc_gpio44_ph1_pins[] = { + TEGRA_PIN_SOC_GPIO44_PH1, +}; + +static const unsigned int gen1_i2c_scl_ph2_pins[] = { + TEGRA_PIN_GEN1_I2C_SCL_PH2, +}; + +static const unsigned int gen1_i2c_sda_ph3_pins[] = { + TEGRA_PIN_GEN1_I2C_SDA_PH3, +}; + +static const unsigned int cpu_pwr_req_ph4_pins[] = { + TEGRA_PIN_CPU_PWR_REQ_PH4, +}; + +static const unsigned int soc_gpio07_ph5_pins[] = { + TEGRA_PIN_SOC_GPIO07_PH5, +}; + +static const unsigned int dap3_clk_pj0_pins[] = { + TEGRA_PIN_DAP3_CLK_PJ0, +}; + +static const unsigned int dap3_dout_pj1_pins[] = { + TEGRA_PIN_DAP3_DOUT_PJ1, +}; + +static const unsigned int dap3_din_pj2_pins[] = { + TEGRA_PIN_DAP3_DIN_PJ2, +}; + +static const unsigned int dap3_fs_pj3_pins[] = { + TEGRA_PIN_DAP3_FS_PJ3, +}; + +static const unsigned int soc_gpio57_pj4_pins[] = { + TEGRA_PIN_SOC_GPIO57_PJ4, +}; + +static const unsigned int soc_gpio58_pj5_pins[] = { + TEGRA_PIN_SOC_GPIO58_PJ5, +}; + +static const unsigned int soc_gpio59_pj6_pins[] = { + TEGRA_PIN_SOC_GPIO59_PJ6, +}; + +static const unsigned int soc_gpio60_pj7_pins[] = { + TEGRA_PIN_SOC_GPIO60_PJ7, +}; + +static const unsigned int soc_gpio45_pk0_pins[] = { + TEGRA_PIN_SOC_GPIO45_PK0, +}; + +static const unsigned int soc_gpio46_pk1_pins[] = { + TEGRA_PIN_SOC_GPIO46_PK1, +}; + +static const unsigned int soc_gpio47_pk2_pins[] = { + TEGRA_PIN_SOC_GPIO47_PK2, +}; + +static const unsigned int soc_gpio48_pk3_pins[] = { + TEGRA_PIN_SOC_GPIO48_PK3, +}; + +static const unsigned int qspi0_sck_pl0_pins[] = { + TEGRA_PIN_QSPI0_SCK_PL0, +}; + +static const unsigned int qspi0_io0_pl1_pins[] = { + TEGRA_PIN_QSPI0_IO0_PL1, +}; + +static const unsigned int qspi0_io1_pl2_pins[] = { + TEGRA_PIN_QSPI0_IO1_PL2, +}; + +static const unsigned int qspi0_cs_n_pl3_pins[] = { + TEGRA_PIN_QSPI0_CS_N_PL3, +}; + +static const unsigned int soc_gpio152_pl4_pins[] = { + TEGRA_PIN_SOC_GPIO152_PL4, +}; + +static const unsigned int soc_gpio153_pl5_pins[] = { + TEGRA_PIN_SOC_GPIO153_PL5, +}; + +static const unsigned int soc_gpio154_pl6_pins[] = { + TEGRA_PIN_SOC_GPIO154_PL6, +}; + +static const unsigned int soc_gpio155_pl7_pins[] = { + TEGRA_PIN_SOC_GPIO155_PL7, +}; + +static const unsigned int soc_gpio156_pm0_pins[] = { + TEGRA_PIN_SOC_GPIO156_PM0, +}; + +static const unsigned int soc_gpio157_pm1_pins[] = { + TEGRA_PIN_SOC_GPIO157_PM1, +}; + +static const unsigned int soc_gpio158_pm2_pins[] = { + TEGRA_PIN_SOC_GPIO158_PM2, +}; + +static const unsigned int soc_gpio159_pm3_pins[] = { + TEGRA_PIN_SOC_GPIO159_PM3, +}; + +static const unsigned int soc_gpio160_pm4_pins[] = { + TEGRA_PIN_SOC_GPIO160_PM4, +}; + +static const unsigned int soc_gpio161_pm5_pins[] = { + TEGRA_PIN_SOC_GPIO161_PM5, +}; + +static const unsigned int soc_gpio162_pm6_pins[] = { + TEGRA_PIN_SOC_GPIO162_PM6, +}; + +static const unsigned int uart7_tx_pm7_pins[] = { + TEGRA_PIN_UART7_TX_PM7, +}; + +static const unsigned int uart7_rx_pn0_pins[] = { + TEGRA_PIN_UART7_RX_PN0, +}; + +static const unsigned int uart7_rts_pn1_pins[] = { + TEGRA_PIN_UART7_RTS_PN1, +}; + +static const unsigned int uart7_cts_pn2_pins[] = { + TEGRA_PIN_UART7_CTS_PN2, +}; + +static const unsigned int soc_gpio167_pp0_pins[] = { + TEGRA_PIN_SOC_GPIO167_PP0, +}; + +static const unsigned int soc_gpio168_pp1_pins[] = { + TEGRA_PIN_SOC_GPIO168_PP1, +}; + +static const unsigned int soc_gpio169_pp2_pins[] = { + TEGRA_PIN_SOC_GPIO169_PP2, +}; + +static const unsigned int soc_gpio170_pp3_pins[] = { + TEGRA_PIN_SOC_GPIO170_PP3, +}; + +static const unsigned int dap4_sclk_pp4_pins[] = { + TEGRA_PIN_DAP4_SCLK_PP4, +}; + +static const unsigned int dap4_dout_pp5_pins[] = { + TEGRA_PIN_DAP4_DOUT_PP5, +}; + +static const unsigned int dap4_din_pp6_pins[] = { + TEGRA_PIN_DAP4_DIN_PP6, +}; + +static const unsigned int dap4_fs_pp7_pins[] = { + TEGRA_PIN_DAP4_FS_PP7, +}; + +static const unsigned int soc_gpio171_pq0_pins[] = { + TEGRA_PIN_SOC_GPIO171_PQ0, +}; + +static const unsigned int soc_gpio172_pq1_pins[] = { + TEGRA_PIN_SOC_GPIO172_PQ1, +}; + +static const unsigned int soc_gpio173_pq2_pins[] = { + TEGRA_PIN_SOC_GPIO173_PQ2, +}; + +static const unsigned int soc_gpio61_pr0_pins[] = { + TEGRA_PIN_SOC_GPIO61_PR0, +}; + +static const unsigned int soc_gpio62_pr1_pins[] = { + TEGRA_PIN_SOC_GPIO62_PR1, +}; + +static const unsigned int soc_gpio63_pr2_pins[] = { + TEGRA_PIN_SOC_GPIO63_PR2, +}; + +static const unsigned int soc_gpio64_pr3_pins[] = { + TEGRA_PIN_SOC_GPIO64_PR3, +}; + +static const unsigned int soc_gpio65_pr4_pins[] = { + TEGRA_PIN_SOC_GPIO65_PR4, +}; + +static const unsigned int soc_gpio66_pr5_pins[] = { + TEGRA_PIN_SOC_GPIO66_PR5, +}; + +static const unsigned int soc_gpio67_pr6_pins[] = { + TEGRA_PIN_SOC_GPIO67_PR6, +}; + +static const unsigned int soc_gpio68_pr7_pins[] = { + TEGRA_PIN_SOC_GPIO68_PR7, +}; + +static const unsigned int gen4_i2c_scl_ps0_pins[] = { + TEGRA_PIN_GEN4_I2C_SCL_PS0, +}; + +static const unsigned int gen4_i2c_sda_ps1_pins[] = { + TEGRA_PIN_GEN4_I2C_SDA_PS1, +}; + +static const unsigned int soc_gpio75_ps2_pins[] = { + TEGRA_PIN_SOC_GPIO75_PS2, +}; + +static const unsigned int gen7_i2c_scl_ps3_pins[] = { + TEGRA_PIN_GEN7_I2C_SCL_PS3, +}; + +static const unsigned int gen7_i2c_sda_ps4_pins[] = { + TEGRA_PIN_GEN7_I2C_SDA_PS4, +}; + +static const unsigned int soc_gpio78_ps5_pins[] = { + TEGRA_PIN_SOC_GPIO78_PS5, +}; + +static const unsigned int gen9_i2c_scl_ps6_pins[] = { + TEGRA_PIN_GEN9_I2C_SCL_PS6, +}; + +static const unsigned int gen9_i2c_sda_ps7_pins[] = { + TEGRA_PIN_GEN9_I2C_SDA_PS7, +}; + +static const unsigned int soc_gpio81_pt0_pins[] = { + TEGRA_PIN_SOC_GPIO81_PT0, +}; + +static const unsigned int soc_gpio36_pt1_pins[] = { + TEGRA_PIN_SOC_GPIO36_PT1, +}; + +static const unsigned int soc_gpio53_pt2_pins[] = { + TEGRA_PIN_SOC_GPIO53_PT2, +}; + +static const unsigned int soc_gpio38_pt3_pins[] = { + TEGRA_PIN_SOC_GPIO38_PT3, +}; + +static const unsigned int soc_gpio40_pt4_pins[] = { + TEGRA_PIN_SOC_GPIO40_PT4, +}; + +static const unsigned int soc_gpio34_pt5_pins[] = { + TEGRA_PIN_SOC_GPIO34_PT5, +}; + +static const unsigned int usb_vbus_en0_pt6_pins[] = { + TEGRA_PIN_USB_VBUS_EN0_PT6, +}; + +static const unsigned int usb_vbus_en1_pt7_pins[] = { + TEGRA_PIN_USB_VBUS_EN1_PT7, +}; + +static const unsigned int sdmmc1_clk_pu0_pins[] = { + TEGRA_PIN_SDMMC1_CLK_PU0, +}; + +static const unsigned int sdmmc1_cmd_pu1_pins[] = { + TEGRA_PIN_SDMMC1_CMD_PU1, +}; + +static const unsigned int sdmmc1_dat0_pu2_pins[] = { + TEGRA_PIN_SDMMC1_DAT0_PU2, +}; + +static const unsigned int sdmmc1_dat1_pu3_pins[] = { + TEGRA_PIN_SDMMC1_DAT1_PU3, +}; + +static const unsigned int sdmmc1_dat2_pu4_pins[] = { + TEGRA_PIN_SDMMC1_DAT2_PU4, +}; + +static const unsigned int sdmmc1_dat3_pu5_pins[] = { + TEGRA_PIN_SDMMC1_DAT3_PU5, +}; + +static const unsigned int ufs0_ref_clk_pv0_pins[] = { + TEGRA_PIN_UFS0_REF_CLK_PV0, +}; + +static const unsigned int ufs0_rst_n_pv1_pins[] = { + TEGRA_PIN_UFS0_RST_N_PV1, +}; + +static const unsigned int pex_l0_clkreq_n_pw0_pins[] = { + TEGRA_PIN_PEX_L0_CLKREQ_N_PW0, +}; + +static const unsigned int pex_l0_rst_n_pw1_pins[] = { + TEGRA_PIN_PEX_L0_RST_N_PW1, +}; + +static const unsigned int pex_l1_clkreq_n_pw2_pins[] = { + TEGRA_PIN_PEX_L1_CLKREQ_N_PW2, +}; + +static const unsigned int pex_l1_rst_n_pw3_pins[] = { + TEGRA_PIN_PEX_L1_RST_N_PW3, +}; + +static const unsigned int pex_l2_clkreq_n_pw4_pins[] = { + TEGRA_PIN_PEX_L2_CLKREQ_N_PW4, +}; + +static const unsigned int pex_l2_rst_n_pw5_pins[] = { + TEGRA_PIN_PEX_L2_RST_N_PW5, +}; + +static const unsigned int pex_l3_clkreq_n_pw6_pins[] = { + TEGRA_PIN_PEX_L3_CLKREQ_N_PW6, +}; + +static const unsigned int pex_l3_rst_n_pw7_pins[] = { + TEGRA_PIN_PEX_L3_RST_N_PW7, +}; + +static const unsigned int pex_wake_n_px0_pins[] = { + TEGRA_PIN_PEX_WAKE_N_PX0, +}; + +static const unsigned int dp_aux_ch0_hpd_px1_pins[] = { + TEGRA_PIN_DP_AUX_CH0_HPD_PX1, +}; + +static const unsigned int bootv_ctl_n_paa0_pins[] = { + TEGRA_PIN_BOOTV_CTL_N_PAA0, +}; + +static const unsigned int soc_gpio00_paa1_pins[] = { + TEGRA_PIN_SOC_GPIO00_PAA1, +}; + +static const unsigned int vcomp_alert_paa2_pins[] = { + TEGRA_PIN_VCOMP_ALERT_PAA2, +}; + +static const unsigned int pwm1_paa3_pins[] = { + TEGRA_PIN_PWM1_PAA3, +}; + +static const unsigned int batt_oc_paa4_pins[] = { + TEGRA_PIN_BATT_OC_PAA4, +}; + +static const unsigned int soc_gpio04_paa5_pins[] = { + TEGRA_PIN_SOC_GPIO04_PAA5, +}; + +static const unsigned int soc_gpio25_paa6_pins[] = { + TEGRA_PIN_SOC_GPIO25_PAA6, +}; + +static const unsigned int soc_gpio26_paa7_pins[] = { + TEGRA_PIN_SOC_GPIO26_PAA7, +}; + +static const unsigned int hdmi_cec_pbb0_pins[] = { + TEGRA_PIN_HDMI_CEC_PBB0, +}; + +static const unsigned int spi2_sck_pcc0_pins[] = { + TEGRA_PIN_SPI2_SCK_PCC0, +}; + +static const unsigned int spi2_miso_pcc1_pins[] = { + TEGRA_PIN_SPI2_MISO_PCC1, +}; + +static const unsigned int spi2_mosi_pcc2_pins[] = { + TEGRA_PIN_SPI2_MOSI_PCC2, +}; + +static const unsigned int spi2_cs0_pcc3_pins[] = { + TEGRA_PIN_SPI2_CS0_PCC3, +}; + +static const unsigned int spi2_cs1_pcc4_pins[] = { + TEGRA_PIN_SPI2_CS1_PCC4, +}; + +static const unsigned int uart3_tx_pcc5_pins[] = { + TEGRA_PIN_UART3_TX_PCC5, +}; + +static const unsigned int uart3_rx_pcc6_pins[] = { + TEGRA_PIN_UART3_RX_PCC6, +}; + +static const unsigned int gen2_i2c_scl_pcc7_pins[] = { + TEGRA_PIN_GEN2_I2C_SCL_PCC7, +}; + +static const unsigned int gen2_i2c_sda_pdd0_pins[] = { + TEGRA_PIN_GEN2_I2C_SDA_PDD0, +}; + +static const unsigned int gen8_i2c_scl_pdd1_pins[] = { + TEGRA_PIN_GEN8_I2C_SCL_PDD1, +}; + +static const unsigned int gen8_i2c_sda_pdd2_pins[] = { + TEGRA_PIN_GEN8_I2C_SDA_PDD2, +}; + +static const unsigned int touch_clk_pdd3_pins[] = { + TEGRA_PIN_TOUCH_CLK_PDD3, +}; + +static const unsigned int dmic1_clk_pdd4_pins[] = { + TEGRA_PIN_DMIC1_CLK_PDD4, +}; + +static const unsigned int dmic1_dat_pdd5_pins[] = { + TEGRA_PIN_DMIC1_DAT_PDD5, +}; + +static const unsigned int soc_gpio19_pdd6_pins[] = { + TEGRA_PIN_SOC_GPIO19_PDD6, +}; + +static const unsigned int pwm2_pdd7_pins[] = { + TEGRA_PIN_PWM2_PDD7, +}; + +static const unsigned int pwm3_pee0_pins[] = { + TEGRA_PIN_PWM3_PEE0, +}; + +static const unsigned int pwm7_pee1_pins[] = { + TEGRA_PIN_PWM7_PEE1, +}; + +static const unsigned int soc_gpio49_pee2_pins[] = { + TEGRA_PIN_SOC_GPIO49_PEE2, +}; + +static const unsigned int soc_gpio82_pee3_pins[] = { + TEGRA_PIN_SOC_GPIO82_PEE3, +}; + +static const unsigned int soc_gpio50_pee4_pins[] = { + TEGRA_PIN_SOC_GPIO50_PEE4, +}; + +static const unsigned int soc_gpio83_pee5_pins[] = { + TEGRA_PIN_SOC_GPIO83_PEE5, +}; + +static const unsigned int soc_gpio69_pff0_pins[] = { + TEGRA_PIN_SOC_GPIO69_PFF0, +}; + +static const unsigned int soc_gpio70_pff1_pins[] = { + TEGRA_PIN_SOC_GPIO70_PFF1, +}; + +static const unsigned int soc_gpio71_pff2_pins[] = { + TEGRA_PIN_SOC_GPIO71_PFF2, +}; + +static const unsigned int soc_gpio72_pff3_pins[] = { + TEGRA_PIN_SOC_GPIO72_PFF3, +}; + +static const unsigned int soc_gpio73_pff4_pins[] = { + TEGRA_PIN_SOC_GPIO73_PFF4, +}; + +static const unsigned int soc_gpio74_pff5_pins[] = { + TEGRA_PIN_SOC_GPIO74_PFF5, +}; + +static const unsigned int soc_gpio80_pff6_pins[] = { + TEGRA_PIN_SOC_GPIO80_PFF6, +}; + +static const unsigned int soc_gpio76_pff7_pins[] = { + TEGRA_PIN_SOC_GPIO76_PFF7, +}; + +static const unsigned int soc_gpio77_pgg0_pins[] = { + TEGRA_PIN_SOC_GPIO77_PGG0, +}; + +static const unsigned int soc_gpio84_pgg1_pins[] = { + TEGRA_PIN_SOC_GPIO84_PGG1, +}; + +static const unsigned int uart2_tx_pgg2_pins[] = { + TEGRA_PIN_UART2_TX_PGG2, +}; + +static const unsigned int uart2_rx_pgg3_pins[] = { + TEGRA_PIN_UART2_RX_PGG3, +}; + +static const unsigned int uart2_rts_pgg4_pins[] = { + TEGRA_PIN_UART2_RTS_PGG4, +}; + +static const unsigned int uart2_cts_pgg5_pins[] = { + TEGRA_PIN_UART2_CTS_PGG5, +}; + +static const unsigned int soc_gpio85_pgg6_pins[] = { + TEGRA_PIN_SOC_GPIO85_PGG6, +}; + +static const unsigned int uart5_tx_pgg7_pins[] = { + TEGRA_PIN_UART5_TX_PGG7, +}; + +static const unsigned int uart5_rx_phh0_pins[] = { + TEGRA_PIN_UART5_RX_PHH0, +}; + +static const unsigned int uart5_rts_phh1_pins[] = { + TEGRA_PIN_UART5_RTS_PHH1, +}; + +static const unsigned int uart5_cts_phh2_pins[] = { + TEGRA_PIN_UART5_CTS_PHH2, +}; + +static const unsigned int soc_gpio86_phh3_pins[] = { + TEGRA_PIN_SOC_GPIO86_PHH3, +}; + +static const unsigned int sdmmc1_comp_pins[] = { + TEGRA_PIN_SDMMC1_COMP, +}; + +/* Define unique ID for each function */ +enum tegra_mux_dt { + TEGRA_MUX_DCA_VSYNC, + TEGRA_MUX_DCA_HSYNC, + TEGRA_MUX_DISPLAYA, + TEGRA_MUX_RSVD0, + TEGRA_MUX_I2C7_CLK, + TEGRA_MUX_I2C7_DAT, + TEGRA_MUX_I2C4_DAT, + TEGRA_MUX_I2C4_CLK, + TEGRA_MUX_I2C9_DAT, + TEGRA_MUX_I2C9_CLK, + TEGRA_MUX_USB_VBUS_EN0, + TEGRA_MUX_USB_VBUS_EN1, + TEGRA_MUX_SPI3_DIN, + TEGRA_MUX_SPI1_CS0, + TEGRA_MUX_SPI3_CS0, + TEGRA_MUX_SPI1_DIN, + TEGRA_MUX_SPI3_CS1, + TEGRA_MUX_SPI1_SCK, + TEGRA_MUX_SPI3_SCK, + TEGRA_MUX_SPI1_CS1, + TEGRA_MUX_SPI1_DOUT, + TEGRA_MUX_SPI3_DOUT, + TEGRA_MUX_GP_PWM5, + TEGRA_MUX_GP_PWM6, + TEGRA_MUX_EXTPERIPH2_CLK, + TEGRA_MUX_EXTPERIPH1_CLK, + TEGRA_MUX_I2C3_DAT, + TEGRA_MUX_I2C3_CLK, + TEGRA_MUX_EXTPERIPH4_CLK, + TEGRA_MUX_EXTPERIPH3_CLK, + TEGRA_MUX_DMIC2_DAT, + TEGRA_MUX_DMIC2_CLK, + TEGRA_MUX_UARTA_CTS, + TEGRA_MUX_UARTA_RTS, + TEGRA_MUX_UARTA_RXD, + TEGRA_MUX_UARTA_TXD, + TEGRA_MUX_I2C5_CLK, + TEGRA_MUX_I2C5_DAT, + TEGRA_MUX_UARTD_CTS, + TEGRA_MUX_UARTD_RTS, + TEGRA_MUX_UARTD_RXD, + TEGRA_MUX_UARTD_TXD, + TEGRA_MUX_I2C1_CLK, + TEGRA_MUX_I2C1_DAT, + TEGRA_MUX_SDMMC1_CD, + TEGRA_MUX_I2S2_SCLK, + TEGRA_MUX_I2S2_SDATA_OUT, + TEGRA_MUX_I2S2_SDATA_IN, + TEGRA_MUX_I2S2_LRCK, + TEGRA_MUX_I2S4_SCLK, + TEGRA_MUX_I2S4_SDATA_OUT, + TEGRA_MUX_I2S4_SDATA_IN, + TEGRA_MUX_I2S4_LRCK, + TEGRA_MUX_I2S1_SCLK, + TEGRA_MUX_I2S1_SDATA_OUT, + TEGRA_MUX_I2S1_SDATA_IN, + TEGRA_MUX_I2S1_LRCK, + TEGRA_MUX_AUD_MCLK, + TEGRA_MUX_I2S3_LRCK, + TEGRA_MUX_I2S3_SCLK, + TEGRA_MUX_I2S3_SDATA_IN, + TEGRA_MUX_I2S3_SDATA_OUT, + TEGRA_MUX_PE2_CLKREQ_L, + TEGRA_MUX_PE1_CLKREQ_L, + TEGRA_MUX_PE1_RST_L, + TEGRA_MUX_PE0_CLKREQ_L, + TEGRA_MUX_PE0_RST_L, + TEGRA_MUX_PE2_RST_L, + TEGRA_MUX_PE3_CLKREQ_L, + TEGRA_MUX_PE3_RST_L, + TEGRA_MUX_DP_AUX_CH0_HPD, + TEGRA_MUX_QSPI0_IO0, + TEGRA_MUX_QSPI0_IO1, + TEGRA_MUX_QSPI0_SCK, + TEGRA_MUX_QSPI0_CS_N, + TEGRA_MUX_UARTG_CTS, + TEGRA_MUX_UARTG_RTS, + TEGRA_MUX_UARTG_TXD, + TEGRA_MUX_UARTG_RXD, + TEGRA_MUX_SDMMC1_CLK, + TEGRA_MUX_SDMMC1_CMD, + TEGRA_MUX_SDMMC1_COMP, + TEGRA_MUX_SDMMC1_DAT3, + TEGRA_MUX_SDMMC1_DAT2, + TEGRA_MUX_SDMMC1_DAT1, + TEGRA_MUX_SDMMC1_DAT0, + TEGRA_MUX_UFS0, + TEGRA_MUX_SOC_THERM_OC1, + TEGRA_MUX_HDMI_CEC, + TEGRA_MUX_GP_PWM4, + TEGRA_MUX_UARTC_RXD, + TEGRA_MUX_UARTC_TXD, + TEGRA_MUX_I2C8_DAT, + TEGRA_MUX_I2C8_CLK, + TEGRA_MUX_SPI2_DOUT, + TEGRA_MUX_I2C2_CLK, + TEGRA_MUX_SPI2_CS0, + TEGRA_MUX_I2C2_DAT, + TEGRA_MUX_SPI2_SCK, + TEGRA_MUX_SPI2_DIN, + TEGRA_MUX_PPC_MODE_1, + TEGRA_MUX_PPC_READY, + TEGRA_MUX_PPC_MODE_2, + TEGRA_MUX_PPC_CC, + TEGRA_MUX_PPC_MODE_0, + TEGRA_MUX_PPC_INT_N, + TEGRA_MUX_UARTE_TXD, + TEGRA_MUX_UARTE_RXD, + TEGRA_MUX_UARTB_TXD, + TEGRA_MUX_UARTB_RXD, + TEGRA_MUX_UARTB_CTS, + TEGRA_MUX_UARTB_RTS, + TEGRA_MUX_UARTE_CTS, + TEGRA_MUX_UARTE_RTS, + TEGRA_MUX_GP_PWM7, + TEGRA_MUX_GP_PWM2, + TEGRA_MUX_GP_PWM3, + TEGRA_MUX_GP_PWM1, + TEGRA_MUX_SPI2_CS1, + TEGRA_MUX_DMIC1_CLK, + TEGRA_MUX_DMIC1_DAT, + TEGRA_MUX_RSVD1, + TEGRA_MUX_DCB_HSYNC, + TEGRA_MUX_DCB_VSYNC, + TEGRA_MUX_SOC_THERM_OC4, + TEGRA_MUX_GP_PWM8, + TEGRA_MUX_NV_THERM_FAN_TACH0, + TEGRA_MUX_WDT_RESET_OUTA, + TEGRA_MUX_CCLA_LA_TRIGGER_MUX, + TEGRA_MUX_DSPK1_DAT, + TEGRA_MUX_DSPK1_CLK, + TEGRA_MUX_NV_THERM_FAN_TACH1, + TEGRA_MUX_DSPK0_DAT, + TEGRA_MUX_DSPK0_CLK, + TEGRA_MUX_I2S5_SCLK, + TEGRA_MUX_I2S6_LRCK, + TEGRA_MUX_I2S6_SDATA_IN, + TEGRA_MUX_I2S6_SCLK, + TEGRA_MUX_I2S6_SDATA_OUT, + TEGRA_MUX_I2S5_LRCK, + TEGRA_MUX_I2S5_SDATA_OUT, + TEGRA_MUX_I2S5_SDATA_IN, + TEGRA_MUX_SDMMC1_PE3_RST_L, + TEGRA_MUX_SDMMC1_PE3_CLKREQ_L, + TEGRA_MUX_TOUCH_CLK, + TEGRA_MUX_PPC_I2C_DAT, + TEGRA_MUX_WDT_RESET_OUTB, + TEGRA_MUX_SPI5_CS1, + TEGRA_MUX_PPC_RST_N, + TEGRA_MUX_PPC_I2C_CLK, + TEGRA_MUX_SPI4_CS1, + TEGRA_MUX_SOC_THERM_OC3, + TEGRA_MUX_SPI5_SCK, + TEGRA_MUX_SPI5_MISO, + TEGRA_MUX_SPI4_SCK, + TEGRA_MUX_SPI4_MISO, + TEGRA_MUX_SPI4_CS0, + TEGRA_MUX_SPI4_MOSI, + TEGRA_MUX_SPI5_CS0, + TEGRA_MUX_SPI5_MOSI, + TEGRA_MUX_LED_BLINK, + TEGRA_MUX_RSVD2, + TEGRA_MUX_DMIC3_CLK, + TEGRA_MUX_DMIC3_DAT, + TEGRA_MUX_DMIC4_CLK, + TEGRA_MUX_DMIC4_DAT, + TEGRA_MUX_TSC_EDGE_OUT0, + TEGRA_MUX_TSC_EDGE_OUT3, + TEGRA_MUX_TSC_EDGE_OUT1, + TEGRA_MUX_TSC_EDGE_OUT2, + TEGRA_MUX_DMIC5_CLK, + TEGRA_MUX_DMIC5_DAT, + TEGRA_MUX_RSVD3, + TEGRA_MUX_SDMMC1_WP, + TEGRA_MUX_TSC_EDGE_OUT0A, + TEGRA_MUX_TSC_EDGE_OUT0D, + TEGRA_MUX_TSC_EDGE_OUT0B, + TEGRA_MUX_TSC_EDGE_OUT0C, + TEGRA_MUX_SOC_THERM_OC2, +}; + +/* Make list of each function name */ +#define TEGRA_PIN_FUNCTION(lid) #lid + +static const char * const tegra238_functions[] = { + TEGRA_PIN_FUNCTION(dca_vsync), + TEGRA_PIN_FUNCTION(dca_hsync), + TEGRA_PIN_FUNCTION(displaya), + TEGRA_PIN_FUNCTION(rsvd0), + TEGRA_PIN_FUNCTION(i2c7_clk), + TEGRA_PIN_FUNCTION(i2c7_dat), + TEGRA_PIN_FUNCTION(i2c4_dat), + TEGRA_PIN_FUNCTION(i2c4_clk), + TEGRA_PIN_FUNCTION(i2c9_dat), + TEGRA_PIN_FUNCTION(i2c9_clk), + TEGRA_PIN_FUNCTION(usb_vbus_en0), + TEGRA_PIN_FUNCTION(usb_vbus_en1), + TEGRA_PIN_FUNCTION(spi3_din), + TEGRA_PIN_FUNCTION(spi1_cs0), + TEGRA_PIN_FUNCTION(spi3_cs0), + TEGRA_PIN_FUNCTION(spi1_din), + TEGRA_PIN_FUNCTION(spi3_cs1), + TEGRA_PIN_FUNCTION(spi1_sck), + TEGRA_PIN_FUNCTION(spi3_sck), + TEGRA_PIN_FUNCTION(spi1_cs1), + TEGRA_PIN_FUNCTION(spi1_dout), + TEGRA_PIN_FUNCTION(spi3_dout), + TEGRA_PIN_FUNCTION(gp_pwm5), + TEGRA_PIN_FUNCTION(gp_pwm6), + TEGRA_PIN_FUNCTION(extperiph2_clk), + TEGRA_PIN_FUNCTION(extperiph1_clk), + TEGRA_PIN_FUNCTION(i2c3_dat), + TEGRA_PIN_FUNCTION(i2c3_clk), + TEGRA_PIN_FUNCTION(extperiph4_clk), + TEGRA_PIN_FUNCTION(extperiph3_clk), + TEGRA_PIN_FUNCTION(dmic2_dat), + TEGRA_PIN_FUNCTION(dmic2_clk), + TEGRA_PIN_FUNCTION(uarta_cts), + TEGRA_PIN_FUNCTION(uarta_rts), + TEGRA_PIN_FUNCTION(uarta_rxd), + TEGRA_PIN_FUNCTION(uarta_txd), + TEGRA_PIN_FUNCTION(i2c5_clk), + TEGRA_PIN_FUNCTION(i2c5_dat), + TEGRA_PIN_FUNCTION(uartd_cts), + TEGRA_PIN_FUNCTION(uartd_rts), + TEGRA_PIN_FUNCTION(uartd_rxd), + TEGRA_PIN_FUNCTION(uartd_txd), + TEGRA_PIN_FUNCTION(i2c1_clk), + TEGRA_PIN_FUNCTION(i2c1_dat), + TEGRA_PIN_FUNCTION(sdmmc1_cd), + TEGRA_PIN_FUNCTION(i2s2_sclk), + TEGRA_PIN_FUNCTION(i2s2_sdata_out), + TEGRA_PIN_FUNCTION(i2s2_sdata_in), + TEGRA_PIN_FUNCTION(i2s2_lrck), + TEGRA_PIN_FUNCTION(i2s4_sclk), + TEGRA_PIN_FUNCTION(i2s4_sdata_out), + TEGRA_PIN_FUNCTION(i2s4_sdata_in), + TEGRA_PIN_FUNCTION(i2s4_lrck), + TEGRA_PIN_FUNCTION(i2s1_sclk), + TEGRA_PIN_FUNCTION(i2s1_sdata_out), + TEGRA_PIN_FUNCTION(i2s1_sdata_in), + TEGRA_PIN_FUNCTION(i2s1_lrck), + TEGRA_PIN_FUNCTION(aud_mclk), + TEGRA_PIN_FUNCTION(i2s3_lrck), + TEGRA_PIN_FUNCTION(i2s3_sclk), + TEGRA_PIN_FUNCTION(i2s3_sdata_in), + TEGRA_PIN_FUNCTION(i2s3_sdata_out), + TEGRA_PIN_FUNCTION(pe2_clkreq_l), + TEGRA_PIN_FUNCTION(pe1_clkreq_l), + TEGRA_PIN_FUNCTION(pe1_rst_l), + TEGRA_PIN_FUNCTION(pe0_clkreq_l), + TEGRA_PIN_FUNCTION(pe0_rst_l), + TEGRA_PIN_FUNCTION(pe2_rst_l), + TEGRA_PIN_FUNCTION(pe3_clkreq_l), + TEGRA_PIN_FUNCTION(pe3_rst_l), + TEGRA_PIN_FUNCTION(dp_aux_ch0_hpd), + TEGRA_PIN_FUNCTION(qspi0_io0), + TEGRA_PIN_FUNCTION(qspi0_io1), + TEGRA_PIN_FUNCTION(qspi0_sck), + TEGRA_PIN_FUNCTION(qspi0_cs_n), + TEGRA_PIN_FUNCTION(uartg_cts), + TEGRA_PIN_FUNCTION(uartg_rts), + TEGRA_PIN_FUNCTION(uartg_txd), + TEGRA_PIN_FUNCTION(uartg_rxd), + TEGRA_PIN_FUNCTION(sdmmc1_clk), + TEGRA_PIN_FUNCTION(sdmmc1_cmd), + TEGRA_PIN_FUNCTION(sdmmc1_comp), + TEGRA_PIN_FUNCTION(sdmmc1_dat3), + TEGRA_PIN_FUNCTION(sdmmc1_dat2), + TEGRA_PIN_FUNCTION(sdmmc1_dat1), + TEGRA_PIN_FUNCTION(sdmmc1_dat0), + TEGRA_PIN_FUNCTION(ufs0), + TEGRA_PIN_FUNCTION(soc_therm_oc1), + TEGRA_PIN_FUNCTION(hdmi_cec), + TEGRA_PIN_FUNCTION(gp_pwm4), + TEGRA_PIN_FUNCTION(uartc_rxd), + TEGRA_PIN_FUNCTION(uartc_txd), + TEGRA_PIN_FUNCTION(i2c8_dat), + TEGRA_PIN_FUNCTION(i2c8_clk), + TEGRA_PIN_FUNCTION(spi2_dout), + TEGRA_PIN_FUNCTION(i2c2_clk), + TEGRA_PIN_FUNCTION(spi2_cs0), + TEGRA_PIN_FUNCTION(i2c2_dat), + TEGRA_PIN_FUNCTION(spi2_sck), + TEGRA_PIN_FUNCTION(spi2_din), + TEGRA_PIN_FUNCTION(ppc_mode_1), + TEGRA_PIN_FUNCTION(ppc_ready), + TEGRA_PIN_FUNCTION(ppc_mode_2), + TEGRA_PIN_FUNCTION(ppc_cc), + TEGRA_PIN_FUNCTION(ppc_mode_0), + TEGRA_PIN_FUNCTION(ppc_int_n), + TEGRA_PIN_FUNCTION(uarte_txd), + TEGRA_PIN_FUNCTION(uarte_rxd), + TEGRA_PIN_FUNCTION(uartb_txd), + TEGRA_PIN_FUNCTION(uartb_rxd), + TEGRA_PIN_FUNCTION(uartb_cts), + TEGRA_PIN_FUNCTION(uartb_rts), + TEGRA_PIN_FUNCTION(uarte_cts), + TEGRA_PIN_FUNCTION(uarte_rts), + TEGRA_PIN_FUNCTION(gp_pwm7), + TEGRA_PIN_FUNCTION(gp_pwm2), + TEGRA_PIN_FUNCTION(gp_pwm3), + TEGRA_PIN_FUNCTION(gp_pwm1), + TEGRA_PIN_FUNCTION(spi2_cs1), + TEGRA_PIN_FUNCTION(dmic1_clk), + TEGRA_PIN_FUNCTION(dmic1_dat), + TEGRA_PIN_FUNCTION(rsvd1), + TEGRA_PIN_FUNCTION(dcb_hsync), + TEGRA_PIN_FUNCTION(dcb_vsync), + TEGRA_PIN_FUNCTION(soc_therm_oc4), + TEGRA_PIN_FUNCTION(gp_pwm8), + TEGRA_PIN_FUNCTION(nv_therm_fan_tach0), + TEGRA_PIN_FUNCTION(wdt_reset_outa), + TEGRA_PIN_FUNCTION(ccla_la_trigger_mux), + TEGRA_PIN_FUNCTION(dspk1_dat), + TEGRA_PIN_FUNCTION(dspk1_clk), + TEGRA_PIN_FUNCTION(nv_therm_fan_tach1), + TEGRA_PIN_FUNCTION(dspk0_dat), + TEGRA_PIN_FUNCTION(dspk0_clk), + TEGRA_PIN_FUNCTION(i2s5_sclk), + TEGRA_PIN_FUNCTION(i2s6_lrck), + TEGRA_PIN_FUNCTION(i2s6_sdata_in), + TEGRA_PIN_FUNCTION(i2s6_sclk), + TEGRA_PIN_FUNCTION(i2s6_sdata_out), + TEGRA_PIN_FUNCTION(i2s5_lrck), + TEGRA_PIN_FUNCTION(i2s5_sdata_out), + TEGRA_PIN_FUNCTION(i2s5_sdata_in), + TEGRA_PIN_FUNCTION(sdmmc1_pe3_rst_l), + TEGRA_PIN_FUNCTION(sdmmc1_pe3_clkreq_l), + TEGRA_PIN_FUNCTION(touch_clk), + TEGRA_PIN_FUNCTION(ppc_i2c_dat), + TEGRA_PIN_FUNCTION(wdt_reset_outb), + TEGRA_PIN_FUNCTION(spi5_cs1), + TEGRA_PIN_FUNCTION(ppc_rst_n), + TEGRA_PIN_FUNCTION(ppc_i2c_clk), + TEGRA_PIN_FUNCTION(spi4_cs1), + TEGRA_PIN_FUNCTION(soc_therm_oc3), + TEGRA_PIN_FUNCTION(spi5_sck), + TEGRA_PIN_FUNCTION(spi5_miso), + TEGRA_PIN_FUNCTION(spi4_sck), + TEGRA_PIN_FUNCTION(spi4_miso), + TEGRA_PIN_FUNCTION(spi4_cs0), + TEGRA_PIN_FUNCTION(spi4_mosi), + TEGRA_PIN_FUNCTION(spi5_cs0), + TEGRA_PIN_FUNCTION(spi5_mosi), + TEGRA_PIN_FUNCTION(led_blink), + TEGRA_PIN_FUNCTION(rsvd2), + TEGRA_PIN_FUNCTION(dmic3_clk), + TEGRA_PIN_FUNCTION(dmic3_dat), + TEGRA_PIN_FUNCTION(dmic4_clk), + TEGRA_PIN_FUNCTION(dmic4_dat), + TEGRA_PIN_FUNCTION(tsc_edge_out0), + TEGRA_PIN_FUNCTION(tsc_edge_out3), + TEGRA_PIN_FUNCTION(tsc_edge_out1), + TEGRA_PIN_FUNCTION(tsc_edge_out2), + TEGRA_PIN_FUNCTION(dmic5_clk), + TEGRA_PIN_FUNCTION(dmic5_dat), + TEGRA_PIN_FUNCTION(rsvd3), + TEGRA_PIN_FUNCTION(sdmmc1_wp), + TEGRA_PIN_FUNCTION(tsc_edge_out0a), + TEGRA_PIN_FUNCTION(tsc_edge_out0d), + TEGRA_PIN_FUNCTION(tsc_edge_out0b), + TEGRA_PIN_FUNCTION(tsc_edge_out0c), + TEGRA_PIN_FUNCTION(soc_therm_oc2), +}; + +#define PINGROUP_REG_Y(r) ((r)) +#define PINGROUP_REG_N(r) -1 + +#define DRV_PINGROUP_Y(r) ((r)) + +#define DRV_PINGROUP_ENTRY_N \ + .drv_reg = -1, \ + .drv_bank = -1, \ + .drvdn_bit = -1, \ + .drvup_bit = -1, \ + .slwr_bit = -1, \ + .slwf_bit = -1 + +#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \ + drvup_w, slwr_b, slwr_w, slwf_b, \ + slwf_w, bank) \ + .drv_reg = DRV_PINGROUP_Y(r), \ + .drv_bank = bank, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w + +#define PIN_PINGROUP_ENTRY_N \ + .mux_reg = -1, \ + .pupd_reg = -1, \ + .tri_reg = -1, \ + .einput_bit = -1, \ + .e_io_hv_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .parked_bit = -1, \ + .lpmd_bit = -1, \ + .drvtype_bit = -1, \ + .lpdr_bit = -1, \ + .pbias_buf_bit = -1, \ + .preemp_bit = -1, \ + .rfu_in_bit = -1 + +#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \ + e_lpdr, e_pbias_buf, gpio_sfio_sel, \ + schmitt_b) \ + .mux_reg = PINGROUP_REG_Y(r), \ + .lpmd_bit = -1, \ + .lock_bit = -1, \ + .hsm_bit = -1, \ + .mux_bank = bank, \ + .mux_bit = 0, \ + .pupd_reg = PINGROUP_REG_##pupd(r), \ + .pupd_bank = bank, \ + .pupd_bit = 2, \ + .tri_reg = PINGROUP_REG_Y(r), \ + .tri_bank = bank, \ + .tri_bit = 4, \ + .einput_bit = e_input, \ + .sfsel_bit = gpio_sfio_sel, \ + .schmitt_bit = schmitt_b, \ + .drvtype_bit = 13, \ + .lpdr_bit = e_lpdr, + +#define drive_soc_gpio36_pt1 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio53_pt2 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio38_pt3 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio40_pt4 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio75_ps2 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio81_pt0 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio78_ps5 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio34_pt5 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen7_i2c_scl_ps3 DRV_PINGROUP_ENTRY_Y(0x100a4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen7_i2c_sda_ps4 DRV_PINGROUP_ENTRY_Y(0x100ac, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen4_i2c_sda_ps1 DRV_PINGROUP_ENTRY_Y(0x100b4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen4_i2c_scl_ps0 DRV_PINGROUP_ENTRY_Y(0x100bc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen9_i2c_sda_ps7 DRV_PINGROUP_ENTRY_Y(0x100c4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen9_i2c_scl_ps6 DRV_PINGROUP_ENTRY_Y(0x100cc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_usb_vbus_en0_pt6 DRV_PINGROUP_ENTRY_Y(0x100d4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_usb_vbus_en1_pt7 DRV_PINGROUP_ENTRY_Y(0x100dc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio61_pr0 DRV_PINGROUP_ENTRY_Y(0x1f004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio62_pr1 DRV_PINGROUP_ENTRY_Y(0x1f00c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio63_pr2 DRV_PINGROUP_ENTRY_Y(0x1f014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio64_pr3 DRV_PINGROUP_ENTRY_Y(0x1f01c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio65_pr4 DRV_PINGROUP_ENTRY_Y(0x1f024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio66_pr5 DRV_PINGROUP_ENTRY_Y(0x1f02c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio67_pr6 DRV_PINGROUP_ENTRY_Y(0x1f034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio68_pr7 DRV_PINGROUP_ENTRY_Y(0x1f03c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi3_miso_pa4 DRV_PINGROUP_ENTRY_Y(0xd004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi1_cs0_pb3 DRV_PINGROUP_ENTRY_Y(0xd00c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi3_cs0_pa6 DRV_PINGROUP_ENTRY_Y(0xd014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi1_miso_pb1 DRV_PINGROUP_ENTRY_Y(0xd01c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi3_cs1_pa7 DRV_PINGROUP_ENTRY_Y(0xd024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi1_sck_pb0 DRV_PINGROUP_ENTRY_Y(0xd02c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi3_sck_pa3 DRV_PINGROUP_ENTRY_Y(0xd034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi1_cs1_pb4 DRV_PINGROUP_ENTRY_Y(0xd03c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi1_mosi_pb2 DRV_PINGROUP_ENTRY_Y(0xd044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi3_mosi_pa5 DRV_PINGROUP_ENTRY_Y(0xd04c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gpu_pwr_req_pa0 DRV_PINGROUP_ENTRY_Y(0xd054, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gp_pwm5_pa1 DRV_PINGROUP_ENTRY_Y(0xd05c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gp_pwm6_pa2 DRV_PINGROUP_ENTRY_Y(0xd064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_extperiph2_clk_pc3 DRV_PINGROUP_ENTRY_Y(0x4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_extperiph1_clk_pc2 DRV_PINGROUP_ENTRY_Y(0xc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_cam_i2c_sda_pc5 DRV_PINGROUP_ENTRY_Y(0x14, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_cam_i2c_scl_pc4 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio23_pc6 DRV_PINGROUP_ENTRY_Y(0x24, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio24_pc7 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio27_pd0 DRV_PINGROUP_ENTRY_Y(0x44, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio29_pd2 DRV_PINGROUP_ENTRY_Y(0x54, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio32_pd4 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio33_pd3 DRV_PINGROUP_ENTRY_Y(0x74, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio35_pd5 DRV_PINGROUP_ENTRY_Y(0x7c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio37_pd6 DRV_PINGROUP_ENTRY_Y(0x84, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio56_pd7 DRV_PINGROUP_ENTRY_Y(0x8c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio55_pd1 DRV_PINGROUP_ENTRY_Y(0x94, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart1_cts_pe3 DRV_PINGROUP_ENTRY_Y(0x9c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart1_rts_pe2 DRV_PINGROUP_ENTRY_Y(0xa4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart1_rx_pe1 DRV_PINGROUP_ENTRY_Y(0xac, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart1_tx_pe0 DRV_PINGROUP_ENTRY_Y(0xb4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_scl_pc0 DRV_PINGROUP_ENTRY_Y(0xbc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_sda_pc1 DRV_PINGROUP_ENTRY_Y(0xc4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_cpu_pwr_req_ph4 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart4_cts_pg5 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart4_rts_pg4 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart4_rx_pg3 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart4_tx_pg2 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen1_i2c_scl_ph2 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen1_i2c_sda_ph3 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio20_pf6 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio21_pf7 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio22_pg0 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio13_pf0 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio14_pf1 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio15_pf2 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio16_pf3 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio17_pf4 DRV_PINGROUP_ENTRY_Y(0x4074, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio18_pf5 DRV_PINGROUP_ENTRY_Y(0x407c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio41_pg6 DRV_PINGROUP_ENTRY_Y(0x408c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio42_pg7 DRV_PINGROUP_ENTRY_Y(0x4094, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio43_ph0 DRV_PINGROUP_ENTRY_Y(0x409c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio44_ph1 DRV_PINGROUP_ENTRY_Y(0x40a4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio06_pg1 DRV_PINGROUP_ENTRY_Y(0x40ac, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio07_ph5 DRV_PINGROUP_ENTRY_Y(0x40b4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap4_sclk_pp4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap4_dout_pp5 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap4_din_pp6 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap4_fs_pp7 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio167_pp0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio168_pp1 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio169_pp2 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio170_pp3 DRV_PINGROUP_ENTRY_Y(0x205c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio171_pq0 DRV_PINGROUP_ENTRY_Y(0x2064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio172_pq1 DRV_PINGROUP_ENTRY_Y(0x206c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio173_pq2 DRV_PINGROUP_ENTRY_Y(0x2074, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio45_pk0 DRV_PINGROUP_ENTRY_Y(0x18004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio46_pk1 DRV_PINGROUP_ENTRY_Y(0x1800c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio47_pk2 DRV_PINGROUP_ENTRY_Y(0x18014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio48_pk3 DRV_PINGROUP_ENTRY_Y(0x1801c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio57_pj4 DRV_PINGROUP_ENTRY_Y(0x18024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio58_pj5 DRV_PINGROUP_ENTRY_Y(0x1802c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio59_pj6 DRV_PINGROUP_ENTRY_Y(0x18034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio60_pj7 DRV_PINGROUP_ENTRY_Y(0x1803c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap3_fs_pj3 DRV_PINGROUP_ENTRY_Y(0x18064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap3_clk_pj0 DRV_PINGROUP_ENTRY_Y(0x1806c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap3_din_pj2 DRV_PINGROUP_ENTRY_Y(0x18074, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dap3_dout_pj1 DRV_PINGROUP_ENTRY_Y(0x1807c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l2_clkreq_n_pw4 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_wake_n_px0 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l1_clkreq_n_pw2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l1_rst_n_pw3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l0_clkreq_n_pw0 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l0_rst_n_pw1 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l2_rst_n_pw5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l3_clkreq_n_pw6 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l3_rst_n_pw7 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dp_aux_ch0_hpd_px1 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_qspi0_io0_pl1 DRV_PINGROUP_ENTRY_Y(0xb004, 12, 5, 24, 5, -1, -1, -1, -1, 0) +#define drive_qspi0_io1_pl2 DRV_PINGROUP_ENTRY_Y(0xb00c, 12, 5, 24, 5, -1, -1, -1, -1, 0) +#define drive_qspi0_sck_pl0 DRV_PINGROUP_ENTRY_Y(0xb014, 12, 5, 24, 5, -1, -1, -1, -1, 0) +#define drive_qspi0_cs_n_pl3 DRV_PINGROUP_ENTRY_Y(0xb01c, 12, 5, 24, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio156_pm0 DRV_PINGROUP_ENTRY_Y(0xb024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio155_pl7 DRV_PINGROUP_ENTRY_Y(0xb02c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio160_pm4 DRV_PINGROUP_ENTRY_Y(0xb034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio154_pl6 DRV_PINGROUP_ENTRY_Y(0xb03c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio152_pl4 DRV_PINGROUP_ENTRY_Y(0xb044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio153_pl5 DRV_PINGROUP_ENTRY_Y(0xb04c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio161_pm5 DRV_PINGROUP_ENTRY_Y(0xb054, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio162_pm6 DRV_PINGROUP_ENTRY_Y(0xb05c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio159_pm3 DRV_PINGROUP_ENTRY_Y(0xb064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio157_pm1 DRV_PINGROUP_ENTRY_Y(0xb06c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio158_pm2 DRV_PINGROUP_ENTRY_Y(0xb074, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart7_cts_pn2 DRV_PINGROUP_ENTRY_Y(0xb07c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart7_rts_pn1 DRV_PINGROUP_ENTRY_Y(0xb084, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart7_tx_pm7 DRV_PINGROUP_ENTRY_Y(0xb08c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart7_rx_pn0 DRV_PINGROUP_ENTRY_Y(0xb094, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_sdmmc1_clk_pu0 DRV_PINGROUP_ENTRY_Y(0x8004, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_cmd_pu1 DRV_PINGROUP_ENTRY_Y(0x800c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat3_pu5 DRV_PINGROUP_ENTRY_Y(0x801c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat2_pu4 DRV_PINGROUP_ENTRY_Y(0x8024, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat1_pu3 DRV_PINGROUP_ENTRY_Y(0x802c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat0_pu2 DRV_PINGROUP_ENTRY_Y(0x8034, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_ufs0_rst_n_pv1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 5, 24, 5, -1, -1, -1, -1, 0) +#define drive_ufs0_ref_clk_pv0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 5, 24, 5, -1, -1, -1, -1, 0) +#define drive_batt_oc_paa4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_bootv_ctl_n_paa0 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_vcomp_alert_paa2 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_hdmi_cec_pbb0 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_touch_clk_pdd3 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x1094, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x109c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x10a4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x10ac, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x10b4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x10bc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio49_pee2 DRV_PINGROUP_ENTRY_Y(0x10c4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio50_pee4 DRV_PINGROUP_ENTRY_Y(0x10cc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio82_pee3 DRV_PINGROUP_ENTRY_Y(0x10d4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio71_pff2 DRV_PINGROUP_ENTRY_Y(0x10dc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio76_pff7 DRV_PINGROUP_ENTRY_Y(0x10e4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio74_pff5 DRV_PINGROUP_ENTRY_Y(0x10ec, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio00_paa1 DRV_PINGROUP_ENTRY_Y(0x10f4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio19_pdd6 DRV_PINGROUP_ENTRY_Y(0x10fc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio86_phh3 DRV_PINGROUP_ENTRY_Y(0x1104, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio72_pff3 DRV_PINGROUP_ENTRY_Y(0x110c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio77_pgg0 DRV_PINGROUP_ENTRY_Y(0x1114, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio80_pff6 DRV_PINGROUP_ENTRY_Y(0x111c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio84_pgg1 DRV_PINGROUP_ENTRY_Y(0x1124, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio83_pee5 DRV_PINGROUP_ENTRY_Y(0x112c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio73_pff4 DRV_PINGROUP_ENTRY_Y(0x1134, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio70_pff1 DRV_PINGROUP_ENTRY_Y(0x113c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio04_paa5 DRV_PINGROUP_ENTRY_Y(0x1144, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio85_pgg6 DRV_PINGROUP_ENTRY_Y(0x114c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio69_pff0 DRV_PINGROUP_ENTRY_Y(0x1154, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio25_paa6 DRV_PINGROUP_ENTRY_Y(0x115c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_gpio26_paa7 DRV_PINGROUP_ENTRY_Y(0x1164, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart5_tx_pgg7 DRV_PINGROUP_ENTRY_Y(0x116c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart5_rx_phh0 DRV_PINGROUP_ENTRY_Y(0x1174, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart2_tx_pgg2 DRV_PINGROUP_ENTRY_Y(0x117c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart2_rx_pgg3 DRV_PINGROUP_ENTRY_Y(0x1184, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart2_cts_pgg5 DRV_PINGROUP_ENTRY_Y(0x118c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart2_rts_pgg4 DRV_PINGROUP_ENTRY_Y(0x1194, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart5_cts_phh2 DRV_PINGROUP_ENTRY_Y(0x119c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart5_rts_phh1 DRV_PINGROUP_ENTRY_Y(0x11a4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwm7_pee1 DRV_PINGROUP_ENTRY_Y(0x11ac, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwm2_pdd7 DRV_PINGROUP_ENTRY_Y(0x11b4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwm3_pee0 DRV_PINGROUP_ENTRY_Y(0x11bc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwm1_paa3 DRV_PINGROUP_ENTRY_Y(0x11c4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_cs1_pcc4 DRV_PINGROUP_ENTRY_Y(0x11cc, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dmic1_clk_pdd4 DRV_PINGROUP_ENTRY_Y(0x11d4, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_dmic1_dat_pdd5 DRV_PINGROUP_ENTRY_Y(0x11dc, 12, 5, 20, 5, -1, -1, -1, -1, 0) + +#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N + +#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \ + gpio_sfio_sel, schmitt_b) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \ + e_input, e_lpdr, e_pbias_buf, \ + gpio_sfio_sel, schmitt_b) \ + drive_##pg_name, \ + } + +static const struct tegra_pingroup tegra238_groups[] = { + PINGROUP(soc_gpio36_pt1, DCA_VSYNC, RSVD1, RSVD2, RSVD3, 0x10000, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio53_pt2, DCA_HSYNC, RSVD1, RSVD2, RSVD3, 0x10008, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio38_pt3, DISPLAYA, DCB_HSYNC, RSVD2, RSVD3, 0x10018, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio40_pt4, RSVD0, DCB_VSYNC, RSVD2, RSVD3, 0x10028, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio75_ps2, RSVD0, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio81_pt0, RSVD0, RSVD1, RSVD2, RSVD3, 0x10038, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio78_ps5, RSVD0, RSVD1, RSVD2, RSVD3, 0x10040, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio34_pt5, RSVD0, RSVD1, RSVD2, RSVD3, 0x10048, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen7_i2c_scl_ps3, I2C7_CLK, RSVD1, RSVD2, RSVD3, 0x100a0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen7_i2c_sda_ps4, I2C7_DAT, RSVD1, RSVD2, RSVD3, 0x100a8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen4_i2c_sda_ps1, I2C4_DAT, RSVD1, RSVD2, RSVD3, 0x100b0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen4_i2c_scl_ps0, I2C4_CLK, RSVD1, RSVD2, RSVD3, 0x100b8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen9_i2c_sda_ps7, I2C9_DAT, RSVD1, RSVD2, RSVD3, 0x100c0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen9_i2c_scl_ps6, I2C9_CLK, RSVD1, RSVD2, RSVD3, 0x100c8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(usb_vbus_en0_pt6, USB_VBUS_EN0, RSVD1, RSVD2, RSVD3, 0x100d0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(usb_vbus_en1_pt7, USB_VBUS_EN1, RSVD1, RSVD2, RSVD3, 0x100d8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio61_pr0, RSVD0, SOC_THERM_OC4, RSVD2, RSVD3, 0x1f000, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio62_pr1, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f008, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio63_pr2, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f010, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio64_pr3, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f018, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio65_pr4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f020, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio66_pr5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f028, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio67_pr6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f030, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio68_pr7, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f038, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi3_miso_pa4, SPI3_DIN, RSVD1, RSVD2, RSVD3, 0xd000, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi1_cs0_pb3, SPI1_CS0, RSVD1, RSVD2, RSVD3, 0xd008, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi3_cs0_pa6, SPI3_CS0, RSVD1, RSVD2, RSVD3, 0xd010, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi1_miso_pb1, SPI1_DIN, RSVD1, RSVD2, RSVD3, 0xd018, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi3_cs1_pa7, SPI3_CS1, RSVD1, RSVD2, RSVD3, 0xd020, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi1_sck_pb0, SPI1_SCK, RSVD1, RSVD2, RSVD3, 0xd028, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi3_sck_pa3, SPI3_SCK, RSVD1, RSVD2, RSVD3, 0xd030, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi1_cs1_pb4, SPI1_CS1, RSVD1, RSVD2, RSVD3, 0xd038, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi1_mosi_pb2, SPI1_DOUT, RSVD1, RSVD2, RSVD3, 0xd040, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi3_mosi_pa5, SPI3_DOUT, RSVD1, RSVD2, RSVD3, 0xd048, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(gpu_pwr_req_pa0, RSVD0, RSVD1, RSVD2, RSVD3, 0xd050, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(gp_pwm5_pa1, GP_PWM5, RSVD1, RSVD2, RSVD3, 0xd058, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gp_pwm6_pa2, GP_PWM6, RSVD1, RSVD2, RSVD3, 0xd060, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(extperiph2_clk_pc3, EXTPERIPH2_CLK, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(extperiph1_clk_pc2, EXTPERIPH1_CLK, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(cam_i2c_sda_pc5, I2C3_DAT, RSVD1, RSVD2, RSVD3, 0x0010, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(cam_i2c_scl_pc4, I2C3_CLK, RSVD1, RSVD2, RSVD3, 0x0018, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio23_pc6, RSVD0, RSVD1, RSVD2, RSVD3, 0x0020, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio24_pc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x0028, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio27_pd0, RSVD0, GP_PWM8, RSVD2, RSVD3, 0x0040, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio29_pd2, RSVD0, NV_THERM_FAN_TACH0, RSVD2, RSVD3, 0x0050, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio32_pd4, EXTPERIPH4_CLK, RSVD1, RSVD2, RSVD3, 0x0068, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio33_pd3, EXTPERIPH3_CLK, RSVD1, RSVD2, RSVD3, 0x0070, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio35_pd5, RSVD0, RSVD1, RSVD2, RSVD3, 0x0078, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio37_pd6, DMIC2_DAT, RSVD1, RSVD2, RSVD3, 0x0080, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio56_pd7, DMIC2_CLK, RSVD1, RSVD2, RSVD3, 0x0088, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio55_pd1, RSVD0, WDT_RESET_OUTA, RSVD2, RSVD3, 0x0090, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart1_cts_pe3, UARTA_CTS, RSVD1, RSVD2, RSVD3, 0x0098, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart1_rts_pe2, UARTA_RTS, RSVD1, RSVD2, RSVD3, 0x00a0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart1_rx_pe1, UARTA_RXD, RSVD1, RSVD2, RSVD3, 0x00a8, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart1_tx_pe0, UARTA_TXD, RSVD1, RSVD2, RSVD3, 0x00b0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(pwr_i2c_scl_pc0, I2C5_CLK, RSVD1, RSVD2, RSVD3, 0x00b8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pwr_i2c_sda_pc1, I2C5_DAT, RSVD1, RSVD2, RSVD3, 0x00c0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(cpu_pwr_req_ph4, RSVD0, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart4_cts_pg5, UARTD_CTS, RSVD1, RSVD2, RSVD3, 0x4008, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart4_rts_pg4, UARTD_RTS, RSVD1, RSVD2, RSVD3, 0x4010, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart4_rx_pg3, UARTD_RXD, RSVD1, RSVD2, RSVD3, 0x4018, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart4_tx_pg2, UARTD_TXD, RSVD1, RSVD2, RSVD3, 0x4020, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(gen1_i2c_scl_ph2, I2C1_CLK, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen1_i2c_sda_ph3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio20_pf6, SDMMC1_CD, RSVD1, RSVD2, RSVD3, 0x4038, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio21_pf7, RSVD0, RSVD1, RSVD2, RSVD3, 0x4040, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio22_pg0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4048, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio13_pf0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio14_pf1, RSVD0, RSVD1, RSVD2, RSVD3, 0x4058, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio15_pf2, RSVD0, RSVD1, RSVD2, RSVD3, 0x4060, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio16_pf3, RSVD0, RSVD1, RSVD2, RSVD3, 0x4068, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio17_pf4, RSVD0, CCLA_LA_TRIGGER_MUX, RSVD2, RSVD3, 0x4070, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio18_pf5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4078, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio41_pg6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x4088, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio42_pg7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x4090, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio43_ph0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x4098, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio44_ph1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x40a0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio06_pg1, RSVD0, RSVD1, RSVD2, RSVD3, 0x40a8, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio07_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x40b0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap4_sclk_pp4, I2S4_SCLK, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap4_dout_pp5, I2S4_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap4_din_pp6, I2S4_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap4_fs_pp7, I2S4_LRCK, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio167_pp0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio168_pp1, RSVD0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio169_pp2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio170_pp3, RSVD0, RSVD1, RSVD2, RSVD3, 0x2058, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio171_pq0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2060, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio172_pq1, RSVD0, RSVD1, RSVD2, RSVD3, 0x2068, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio173_pq2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2070, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio45_pk0, I2S1_SCLK, DSPK1_DAT, DMIC3_CLK, RSVD3, 0x18000, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio46_pk1, I2S1_SDATA_OUT, DSPK1_CLK, DMIC3_DAT, RSVD3, 0x18008, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio47_pk2, I2S1_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x18010, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio48_pk3, I2S1_LRCK, RSVD1, RSVD2, RSVD3, 0x18018, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio57_pj4, RSVD0, RSVD1, RSVD2, SDMMC1_WP, 0x18020, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio58_pj5, RSVD0, RSVD1, RSVD2, RSVD3, 0x18028, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio59_pj6, AUD_MCLK, RSVD1, RSVD2, RSVD3, 0x18030, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio60_pj7, RSVD0, NV_THERM_FAN_TACH1, RSVD2, RSVD3, 0x18038, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap3_fs_pj3, I2S3_LRCK, RSVD1, RSVD2, RSVD3, 0x18060, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap3_clk_pj0, I2S3_SCLK, DSPK0_DAT, DMIC4_CLK, RSVD3, 0x18068, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap3_din_pj2, I2S3_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x18070, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dap3_dout_pj1, I2S3_SDATA_OUT, DSPK0_CLK, DMIC4_DAT, RSVD3, 0x18078, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l2_clkreq_n_pw4, PE2_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_wake_n_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l1_clkreq_n_pw2, PE1_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l1_rst_n_pw3, PE1_RST_L, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l0_clkreq_n_pw0, PE0_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l0_rst_n_pw1, PE0_RST_L, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l2_rst_n_pw5, PE2_RST_L, RSVD1, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l3_clkreq_n_pw6, PE3_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pex_l3_rst_n_pw7, PE3_RST_L, RSVD1, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(dp_aux_ch0_hpd_px1, DP_AUX_CH0_HPD, RSVD1, RSVD2, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(qspi0_io0_pl1, QSPI0_IO0, RSVD1, RSVD2, RSVD3, 0xb000, 0, Y, -1, 5, 6, -1, -1, 10, 12), + PINGROUP(qspi0_io1_pl2, QSPI0_IO1, RSVD1, RSVD2, RSVD3, 0xb008, 0, Y, -1, 5, 6, -1, -1, 10, 12), + PINGROUP(qspi0_sck_pl0, QSPI0_SCK, RSVD1, RSVD2, RSVD3, 0xb010, 0, Y, -1, 5, 6, -1, -1, 10, 12), + PINGROUP(qspi0_cs_n_pl3, QSPI0_CS_N, RSVD1, RSVD2, RSVD3, 0xb018, 0, Y, -1, 5, 6, -1, -1, 10, 12), + PINGROUP(soc_gpio156_pm0, RSVD0, I2S5_SCLK, RSVD2, RSVD3, 0xb020, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio155_pl7, RSVD0, I2S6_LRCK, RSVD2, RSVD3, 0xb028, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio160_pm4, RSVD0, RSVD1, RSVD2, RSVD3, 0xb030, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio154_pl6, RSVD0, I2S6_SDATA_IN, RSVD2, RSVD3, 0xb038, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio152_pl4, RSVD0, I2S6_SCLK, RSVD2, RSVD3, 0xb040, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio153_pl5, RSVD0, I2S6_SDATA_OUT, RSVD2, RSVD3, 0xb048, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio161_pm5, RSVD0, RSVD1, RSVD2, RSVD3, 0xb050, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio162_pm6, RSVD0, RSVD1, RSVD2, RSVD3, 0xb058, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio159_pm3, RSVD0, I2S5_LRCK, RSVD2, RSVD3, 0xb060, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio157_pm1, RSVD0, I2S5_SDATA_OUT, RSVD2, RSVD3, 0xb068, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio158_pm2, RSVD0, I2S5_SDATA_IN, RSVD2, RSVD3, 0xb070, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart7_cts_pn2, UARTG_CTS, RSVD1, RSVD2, RSVD3, 0xb078, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart7_rts_pn1, UARTG_RTS, RSVD1, RSVD2, RSVD3, 0xb080, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart7_tx_pm7, UARTG_TXD, RSVD1, RSVD2, RSVD3, 0xb088, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart7_rx_pn0, UARTG_RXD, RSVD1, RSVD2, RSVD3, 0xb090, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(sdmmc1_clk_pu0, SDMMC1_CLK, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, -1, 5, 6, -1, 9, 10, 12), + PINGROUP(sdmmc1_cmd_pu1, SDMMC1_CMD, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, -1, 5, 6, -1, 9, 10, 12), + PINGROUP(sdmmc1_comp, SDMMC1_COMP, RSVD1, RSVD2, RSVD3, 0x8010, 0, N, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc1_dat3_pu5, SDMMC1_DAT3, SDMMC1_PE3_RST_L, RSVD2, RSVD3, 0x8018, 0, Y, -1, 5, 6, -1, 9, 10, 12), + PINGROUP(sdmmc1_dat2_pu4, SDMMC1_DAT2, SDMMC1_PE3_CLKREQ_L, RSVD2, RSVD3, 0x8020, 0, Y, -1, 5, 6, -1, 9, 10, 12), + PINGROUP(sdmmc1_dat1_pu3, SDMMC1_DAT1, RSVD1, RSVD2, RSVD3, 0x8028, 0, Y, -1, 5, 6, -1, 9, 10, 12), + PINGROUP(sdmmc1_dat0_pu2, SDMMC1_DAT0, RSVD1, RSVD2, RSVD3, 0x8030, 0, Y, -1, 5, 6, -1, 9, 10, 12), + PINGROUP(ufs0_rst_n_pv1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, 5, 6, -1, -1, 10, 12), + PINGROUP(ufs0_ref_clk_pv0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, 5, 6, -1, -1, 10, 12), + +}; + +static const struct tegra_pingroup tegra238_aon_groups[] = { + PINGROUP(bootv_ctl_n_paa0, RSVD0, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio00_paa1, RSVD0, RSVD1, RSVD2, RSVD3, 0x10f0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(vcomp_alert_paa2, SOC_THERM_OC1, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pwm1_paa3, GP_PWM1, RSVD1, RSVD2, RSVD3, 0x11c0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(batt_oc_paa4, SOC_THERM_OC2, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio04_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1140, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio25_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1158, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio26_paa7, RSVD0, SOC_THERM_OC3, RSVD2, RSVD3, 0x1160, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(hdmi_cec_pbb0, HDMI_CEC, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(spi2_sck_pcc0, SPI2_SCK, RSVD1, RSVD2, RSVD3, 0x10b0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi2_miso_pcc1, SPI2_DIN, RSVD1, RSVD2, RSVD3, 0x10b8, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi2_mosi_pcc2, SPI2_DOUT, RSVD1, RSVD2, RSVD3, 0x1090, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi2_cs0_pcc3, SPI2_CS0, RSVD1, RSVD2, RSVD3, 0x10a0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(spi2_cs1_pcc4, SPI2_CS1, RSVD1, RSVD2, RSVD3, 0x11c8, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(uart3_tx_pcc5, UARTC_TXD, RSVD1, RSVD2, RSVD3, 0x1078, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart3_rx_pcc6, UARTC_RXD, RSVD1, RSVD2, RSVD3, 0x1070, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen2_i2c_scl_pcc7, I2C2_CLK, RSVD1, RSVD2, RSVD3, 0x1098, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen2_i2c_sda_pdd0, I2C2_DAT, RSVD1, RSVD2, RSVD3, 0x10a8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen8_i2c_scl_pdd1, I2C8_CLK, RSVD1, RSVD2, RSVD3, 0x1088, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(gen8_i2c_sda_pdd2, I2C8_DAT, RSVD1, RSVD2, RSVD3, 0x1080, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(touch_clk_pdd3, GP_PWM4, TOUCH_CLK, RSVD2, RSVD3, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(dmic1_clk_pdd4, DMIC1_CLK, RSVD1, DMIC5_CLK, RSVD3, 0x11d0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(dmic1_dat_pdd5, DMIC1_DAT, RSVD1, DMIC5_DAT, RSVD3, 0x11d8, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio19_pdd6, RSVD0, WDT_RESET_OUTB, RSVD2, RSVD3, 0x10f8, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio49_pee2, RSVD0, RSVD1, RSVD2, RSVD3, 0x10c0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio50_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x10c8, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio82_pee3, RSVD0, RSVD1, RSVD2, RSVD3, 0x10d0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio71_pff2, PPC_MODE_1, RSVD1, RSVD2, RSVD3, 0x10d8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio76_pff7, RSVD0, RSVD1, TSC_EDGE_OUT0, TSC_EDGE_OUT0A, 0x10e0, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio74_pff5, PPC_READY, PPC_I2C_DAT, RSVD2, RSVD3, 0x10e8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio86_phh3, RSVD0, SPI5_CS1, TSC_EDGE_OUT3, TSC_EDGE_OUT0D, 0x1100, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio72_pff3, PPC_MODE_2, RSVD1, RSVD2, RSVD3, 0x1108, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio77_pgg0, RSVD0, RSVD1, TSC_EDGE_OUT1, TSC_EDGE_OUT0B, 0x1110, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio80_pff6, RSVD0, PPC_RST_N, RSVD2, RSVD3, 0x1118, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio84_pgg1, RSVD0, RSVD1, TSC_EDGE_OUT2, TSC_EDGE_OUT0C, 0x1120, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio83_pee5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1128, 0, Y, -1, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio73_pff4, PPC_CC, PPC_I2C_CLK, RSVD2, RSVD3, 0x1130, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio70_pff1, PPC_MODE_0, RSVD1, RSVD2, RSVD3, 0x1138, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio85_pgg6, RSVD0, SPI4_CS1, RSVD2, RSVD3, 0x1148, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(soc_gpio69_pff0, PPC_INT_N, RSVD1, RSVD2, RSVD3, 0x1150, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart5_tx_pgg7, UARTE_TXD, SPI5_SCK, RSVD2, RSVD3, 0x1168, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart5_rx_phh0, UARTE_RXD, SPI5_MISO, RSVD2, RSVD3, 0x1170, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart2_tx_pgg2, UARTB_TXD, SPI4_SCK, RSVD2, RSVD3, 0x1178, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart2_rx_pgg3, UARTB_RXD, SPI4_MISO, RSVD2, RSVD3, 0x1180, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart2_cts_pgg5, UARTB_CTS, SPI4_CS0, RSVD2, RSVD3, 0x1188, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart2_rts_pgg4, UARTB_RTS, SPI4_MOSI, RSVD2, RSVD3, 0x1190, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart5_cts_phh2, UARTE_CTS, SPI5_CS0, RSVD2, RSVD3, 0x1198, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(uart5_rts_phh1, UARTE_RTS, SPI5_MOSI, RSVD2, RSVD3, 0x11a0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pwm2_pdd7, GP_PWM2, LED_BLINK, RSVD2, RSVD3, 0x11b0, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pwm3_pee0, GP_PWM3, RSVD1, RSVD2, RSVD3, 0x11b8, 0, Y, 5, 7, 6, 8, -1, 10, 12), + PINGROUP(pwm7_pee1, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x11a8, 0, Y, 5, 7, 6, 8, -1, 10, 12), +}; + +static const struct tegra_pinctrl_soc_data tegra238_pinctrl_aon = { + .pins = tegra238_aon_pins, + .npins = ARRAY_SIZE(tegra238_aon_pins), + .functions = tegra238_functions, + .nfunctions = ARRAY_SIZE(tegra238_functions), + .groups = tegra238_aon_groups, + .ngroups = ARRAY_SIZE(tegra238_aon_groups), + .hsm_in_mux = false, + .schmitt_in_mux = true, + .drvtype_in_mux = true, + .sfsel_in_mux = true, +}; + +static const struct tegra_pinctrl_soc_data tegra238_pinctrl = { + .pins = tegra238_pins, + .npins = ARRAY_SIZE(tegra238_pins), + .functions = tegra238_functions, + .nfunctions = ARRAY_SIZE(tegra238_functions), + .groups = tegra238_groups, + .ngroups = ARRAY_SIZE(tegra238_groups), + .hsm_in_mux = false, + .schmitt_in_mux = true, + .drvtype_in_mux = true, + .sfsel_in_mux = true, +}; + +static int tegra238_pinctrl_probe(struct platform_device *pdev) +{ + const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev); + + return tegra_pinctrl_probe(pdev, soc); +} + +static const struct of_device_id tegra238_pinctrl_of_match[] = { + { .compatible = "nvidia,tegra238-pinmux", .data = &tegra238_pinctrl }, + { .compatible = "nvidia,tegra238-pinmux-aon", .data = &tegra238_pinctrl_aon }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra238_pinctrl_of_match); + +static struct platform_driver tegra238_pinctrl_driver = { + .driver = { + .name = "tegra238-pinctrl", + .of_match_table = tegra238_pinctrl_of_match, + }, + .probe = tegra238_pinctrl_probe, +}; + +static int __init tegra238_pinctrl_init(void) +{ + return platform_driver_register(&tegra238_pinctrl_driver); +} +module_init(tegra238_pinctrl_init); + +static void __exit tegra238_pinctrl_exit(void) +{ + platform_driver_unregister(&tegra238_pinctrl_driver); +} +module_exit(tegra238_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("NVIDIA Corporation"); +MODULE_DESCRIPTION("NVIDIA Tegra238 pinctrl driver"); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra264.c b/drivers/pinctrl/tegra/pinctrl-tegra264.c new file mode 100644 index 000000000000..f8afb0bdb68a --- /dev/null +++ b/drivers/pinctrl/tegra/pinctrl-tegra264.c @@ -0,0 +1,2215 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl data for the NVIDIA Tegra264 pinmux + * + * Copyright (c) 2024-2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-tegra.h" + +/* Define unique ID for each pins */ +enum { + TEGRA_PIN_PEX_L4_CLKREQ_N_PD0, + TEGRA_PIN_PEX_L4_RST_N_PD1, + TEGRA_PIN_PEX_L5_CLKREQ_N_PD2, + TEGRA_PIN_PEX_L5_RST_N_PD3, + TEGRA_PIN_ETH0_MDIO_PD4, + TEGRA_PIN_ETH0_MDC_PD5, + TEGRA_PIN_ETH3_MDIO_PD6, + TEGRA_PIN_ETH3_MDC_PD7, + TEGRA_PIN_ETH1_MDIO_PE0, + TEGRA_PIN_ETH1_MDC_PE1, + TEGRA_PIN_ETH2_MDIO_PE2, + TEGRA_PIN_ETH2_MDC_PE3, + TEGRA_PIN_PEX_L1_CLKREQ_N_PB0, + TEGRA_PIN_PEX_L1_RST_N_PB1, + TEGRA_PIN_PEX_L2_CLKREQ_N_PB2, + TEGRA_PIN_PEX_L2_RST_N_PB3, + TEGRA_PIN_PEX_L3_CLKREQ_N_PB4, + TEGRA_PIN_PEX_L3_RST_N_PB5, + TEGRA_PIN_SOC_GPIO113_PB6, + TEGRA_PIN_SOC_GPIO114_PB7, + TEGRA_PIN_SGMII0_SMA_MDIO_PC0, + TEGRA_PIN_SGMII0_SMA_MDC_PC1, + TEGRA_PIN_PEX_WAKE_N_PC2, + TEGRA_PIN_PWM1_PA0, + TEGRA_PIN_PWM6_PA1, + TEGRA_PIN_PWM7_PA2, + TEGRA_PIN_PWM8_PA3, + TEGRA_PIN_UFS0_REF_CLK_PA4, + TEGRA_PIN_UFS0_RST_N_PA5, +}; + +enum { + TEGRA_PIN_SOC_GPIO250_PF0, + TEGRA_PIN_SOC_GPIO251_PF1, + TEGRA_PIN_SOC_GPIO252_PF2, + TEGRA_PIN_DP_AUX_CH0_HPD_PF3, + TEGRA_PIN_DP_AUX_CH1_HPD_PF4, + TEGRA_PIN_DP_AUX_CH2_HPD_PF5, + TEGRA_PIN_DP_AUX_CH3_HPD_PF6, + TEGRA_PIN_PWM2_PF7, + TEGRA_PIN_PWM3_PG0, + TEGRA_PIN_GEN7_I2C_SCL_PG1, + TEGRA_PIN_GEN7_I2C_SDA_PG2, + TEGRA_PIN_GEN9_I2C_SCL_PG3, + TEGRA_PIN_GEN9_I2C_SDA_PG4, + TEGRA_PIN_SDMMC1_CLK_PX0, + TEGRA_PIN_SDMMC1_CMD_PX1, + TEGRA_PIN_SDMMC1_DAT0_PX2, + TEGRA_PIN_SDMMC1_DAT1_PX3, + TEGRA_PIN_SDMMC1_DAT2_PX4, + TEGRA_PIN_SDMMC1_DAT3_PX5, + TEGRA_PIN_SDMMC1_COMP, + TEGRA_PIN_SOC_GPIO124_PL0, + TEGRA_PIN_SOC_GPIO125_PL1, + TEGRA_PIN_FAN_TACH0_PL2, + TEGRA_PIN_SOC_GPIO127_PL3, + TEGRA_PIN_SOC_GPIO128_PL4, + TEGRA_PIN_SOC_GPIO129_PL5, + TEGRA_PIN_SOC_GPIO130_PL6, + TEGRA_PIN_SOC_GPIO131_PL7, + TEGRA_PIN_GP_PWM9_PM0, + TEGRA_PIN_SOC_GPIO133_PM1, + TEGRA_PIN_UART9_TX_PM2, + TEGRA_PIN_UART9_RX_PM3, + TEGRA_PIN_UART9_RTS_N_PM4, + TEGRA_PIN_UART9_CTS_N_PM5, + TEGRA_PIN_SOC_GPIO170_PU0, + TEGRA_PIN_SOC_GPIO171_PU1, + TEGRA_PIN_SOC_GPIO172_PU2, + TEGRA_PIN_SOC_GPIO173_PU3, + TEGRA_PIN_SOC_GPIO174_PU4, + TEGRA_PIN_SOC_GPIO175_PU5, + TEGRA_PIN_SOC_GPIO176_PU6, + TEGRA_PIN_SOC_GPIO177_PU7, + TEGRA_PIN_SOC_GPIO178_PV0, + TEGRA_PIN_PWM10_PV1, + TEGRA_PIN_UART4_TX_PV2, + TEGRA_PIN_UART4_RX_PV3, + TEGRA_PIN_UART4_RTS_N_PV4, + TEGRA_PIN_UART4_CTS_N_PV5, + TEGRA_PIN_DAP2_CLK_PV6, + TEGRA_PIN_DAP2_DIN_PW0, + TEGRA_PIN_DAP2_DOUT_PV7, + TEGRA_PIN_DAP2_FS_PW1, + TEGRA_PIN_GEN1_I2C_SCL_PW2, + TEGRA_PIN_GEN1_I2C_SDA_PW3, + TEGRA_PIN_GEN0_I2C_SCL_PW4, + TEGRA_PIN_GEN0_I2C_SDA_PW5, + TEGRA_PIN_PWR_I2C_SCL_PW6, + TEGRA_PIN_PWR_I2C_SDA_PW7, + TEGRA_PIN_SOC_GPIO138_PP0, + TEGRA_PIN_SOC_GPIO139_PP1, + TEGRA_PIN_DAP6_SCLK_PP2, + TEGRA_PIN_DAP6_DOUT_PP3, + TEGRA_PIN_DAP6_DIN_PP4, + TEGRA_PIN_DAP6_FS_PP5, + TEGRA_PIN_DAP4_SCLK_PP6, + TEGRA_PIN_DAP4_DOUT_PP7, + TEGRA_PIN_DAP4_DIN_PQ0, + TEGRA_PIN_DAP4_FS_PQ1, + TEGRA_PIN_SPI5_SCK_PQ2, + TEGRA_PIN_SPI5_MISO_PQ3, + TEGRA_PIN_SPI5_MOSI_PQ4, + TEGRA_PIN_SPI5_CS0_PQ5, + TEGRA_PIN_SOC_GPIO152_PQ6, + TEGRA_PIN_SOC_GPIO153_PQ7, + TEGRA_PIN_AUD_MCLK_PR0, + TEGRA_PIN_SOC_GPIO155_PR1, + TEGRA_PIN_DAP1_SCLK_PR2, + TEGRA_PIN_DAP1_OUT_PR3, + TEGRA_PIN_DAP1_IN_PR4, + TEGRA_PIN_DAP1_FS_PR5, + TEGRA_PIN_GEN11_I2C_SCL_PR6, + TEGRA_PIN_GEN11_I2C_SDA_PR7, + TEGRA_PIN_SOC_GPIO350_PS0, + TEGRA_PIN_SOC_GPIO351_PS1, + TEGRA_PIN_QSPI0_SCK_PT0, + TEGRA_PIN_QSPI0_CS_N_PT1, + TEGRA_PIN_QSPI0_IO0_PT2, + TEGRA_PIN_QSPI0_IO1_PT3, + TEGRA_PIN_QSPI0_IO2_PT4, + TEGRA_PIN_QSPI0_IO3_PT5, + TEGRA_PIN_SOC_GPIO192_PT6, + TEGRA_PIN_SOC_GPIO270_PY0, + TEGRA_PIN_SOC_GPIO271_PY1, + TEGRA_PIN_SOC_GPIO272_PY2, + TEGRA_PIN_SOC_GPIO273_PY3, + TEGRA_PIN_SOC_GPIO274_PY4, + TEGRA_PIN_SOC_GPIO275_PY5, + TEGRA_PIN_SOC_GPIO276_PY6, + TEGRA_PIN_SOC_GPIO277_PY7, + TEGRA_PIN_SOC_GPIO278_PZ0, + TEGRA_PIN_SOC_GPIO279_PZ1, + TEGRA_PIN_XHALT_TRIG_PZ2, + TEGRA_PIN_SOC_GPIO281_PZ3, + TEGRA_PIN_SOC_GPIO282_PZ4, + TEGRA_PIN_SOC_GPIO283_PZ5, + TEGRA_PIN_SOC_GPIO284_PZ6, + TEGRA_PIN_SOC_GPIO285_PZ7, + TEGRA_PIN_SOC_GPIO286_PAL0, + TEGRA_PIN_SOC_GPIO287_PAL1, + TEGRA_PIN_SOC_GPIO288_PAL2, + TEGRA_PIN_CPU_PWR_REQ_PH0, + TEGRA_PIN_GPU_PWR_REQ_PH1, + TEGRA_PIN_UART10_TX_PH2, + TEGRA_PIN_UART10_RX_PH3, + TEGRA_PIN_UART10_RTS_N_PH4, + TEGRA_PIN_UART10_CTS_N_PH5, + TEGRA_PIN_SPI3_SCK_PH6, + TEGRA_PIN_SPI3_MISO_PH7, + TEGRA_PIN_SPI3_MOSI_PJ0, + TEGRA_PIN_SPI3_CS0_PJ1, + TEGRA_PIN_SPI3_CS3_PJ2, + TEGRA_PIN_UART5_TX_PJ3, + TEGRA_PIN_UART5_RX_PJ4, + TEGRA_PIN_UART5_RTS_N_PJ5, + TEGRA_PIN_UART5_CTS_N_PJ6, + TEGRA_PIN_SPI1_SCK_PJ7, + TEGRA_PIN_SPI1_MISO_PK0, + TEGRA_PIN_SPI1_MOSI_PK1, + TEGRA_PIN_SPI1_CS0_PK2, + TEGRA_PIN_SPI1_CS1_PK3, + TEGRA_PIN_EXTPERIPH1_CLK_PK4, + TEGRA_PIN_EXTPERIPH2_CLK_PK5, + TEGRA_PIN_GEN12_I2C_SCL_PK6, + TEGRA_PIN_GEN12_I2C_SDA_PK7, +}; + +enum { + TEGRA_PIN_SOC_GPIO00_PAA0, + TEGRA_PIN_VCOMP_ALERT_PAA1, + TEGRA_PIN_AO_RETENTION_N_PAA2, + TEGRA_PIN_BATT_OC_PAA3, + TEGRA_PIN_BOOTV_CTL_N_PAA4, + TEGRA_PIN_POWER_ON_PAA5, + TEGRA_PIN_HDMI_CEC_PAA6, + TEGRA_PIN_SOC_GPIO07_PAA7, + TEGRA_PIN_SOC_GPIO08_PBB0, + TEGRA_PIN_SOC_GPIO09_PBB1, + TEGRA_PIN_GEN2_I2C_SCL_PCC0, + TEGRA_PIN_GEN2_I2C_SDA_PCC1, + TEGRA_PIN_GEN3_I2C_SCL_PCC2, + TEGRA_PIN_GEN3_I2C_SDA_PCC3, + TEGRA_PIN_GP_PWM4_PCC4, + TEGRA_PIN_UART0_TX_PCC5, + TEGRA_PIN_UART0_RX_PCC6, + TEGRA_PIN_SPI2_SCK_PCC7, + TEGRA_PIN_SPI2_MISO_PDD0, + TEGRA_PIN_SPI2_MOSI_PDD1, + TEGRA_PIN_SPI2_CS0_N_PDD2, + TEGRA_PIN_SOC_GPIO21_PDD3, + TEGRA_PIN_SOC_GPIO22_PDD4, + TEGRA_PIN_SOC_GPIO23_PDD5, + TEGRA_PIN_SOC_GPIO24_PDD6, + TEGRA_PIN_SOC_GPIO25_PDD7, + TEGRA_PIN_SOC_GPIO26_PEE0, + TEGRA_PIN_SOC_GPIO27_PEE1, + TEGRA_PIN_SOC_GPIO28_PEE2, + TEGRA_PIN_SOC_GPIO29_PEE3, +}; + +static const struct pinctrl_pin_desc tegra264_uphy_pins[] = { + PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PD0, "PEX_L4_CLKREQ_N_PD0"), + PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PD1, "PEX_L4_RST_N_PD1"), + PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PD2, "PEX_L5_CLKREQ_N_PD2"), + PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PD3, "PEX_L5_RST_N_PD3"), + PINCTRL_PIN(TEGRA_PIN_ETH0_MDIO_PD4, "ETH0_MDIO_PD4"), + PINCTRL_PIN(TEGRA_PIN_ETH0_MDC_PD5, "ETH0_MDC_PD5"), + PINCTRL_PIN(TEGRA_PIN_ETH3_MDIO_PD6, "ETH3_MDIO_PD6"), + PINCTRL_PIN(TEGRA_PIN_ETH3_MDC_PD7, "ETH3_MDC_PD7"), + PINCTRL_PIN(TEGRA_PIN_ETH1_MDIO_PE0, "ETH1_MDIO_PE0"), + PINCTRL_PIN(TEGRA_PIN_ETH1_MDC_PE1, "ETH1_MDC_PE1"), + PINCTRL_PIN(TEGRA_PIN_ETH2_MDIO_PE2, "ETH2_MDIO_PE2"), + PINCTRL_PIN(TEGRA_PIN_ETH2_MDC_PE3, "ETH2_MDC_PE3"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PB0, "PEX_L1_CLKREQ_N_PB0"), + PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PB1, "PEX_L1_RST_N_PB1"), + PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PB2, "PEX_L2_CLKREQ_N_PB2"), + PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PB3, "PEX_L2_RST_N_PB3"), + PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PB4, "PEX_L3_CLKREQ_N_PB4"), + PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PB5, "PEX_L3_RST_N_PB5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO113_PB6, "SOC_GPIO113_PB6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO114_PB7, "SOC_GPIO114_PB7"), + PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDIO_PC0, "SGMII0_SMA_MDIO_PC0"), + PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDC_PC1, "SGMII0_SMA_MDC_PC1"), + PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PC2, "PEX_WAKE_N_PC2"), + PINCTRL_PIN(TEGRA_PIN_PWM1_PA0, "PWM1_PA0"), + PINCTRL_PIN(TEGRA_PIN_PWM6_PA1, "PWM6_PA1"), + PINCTRL_PIN(TEGRA_PIN_PWM7_PA2, "PWM7_PA2"), + PINCTRL_PIN(TEGRA_PIN_PWM8_PA3, "PWM8_PA3"), + PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PA4, "UFS0_REF_CLK_PA4"), + PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PA5, "UFS0_RST_N_PA5"), +}; + +static const struct pinctrl_pin_desc tegra264_main_pins[] = { + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO250_PF0, "SOC_GPIO250_PF0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO251_PF1, "SOC_GPIO251_PF1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO252_PF2, "SOC_GPIO252_PF2"), + PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PF3, "DP_AUX_CH0_HPD_PF3"), + PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PF4, "DP_AUX_CH1_HPD_PF4"), + PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PF5, "DP_AUX_CH2_HPD_PF5"), + PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PF6, "DP_AUX_CH3_HPD_PF6"), + PINCTRL_PIN(TEGRA_PIN_PWM2_PF7, "PWM2_PF7"), + PINCTRL_PIN(TEGRA_PIN_PWM3_PG0, "PWM3_PG0"), + PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PG1, "GEN7_I2C_SCL_PG1"), + PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PG2, "GEN7_I2C_SDA_PG2"), + PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PG3, "GEN9_I2C_SCL_PG3"), + PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PG4, "GEN9_I2C_SDA_PG4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PX0, "SDMMC1_CLK_PX0"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PX1, "SDMMC1_CMD_PX1"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PX2, "SDMMC1_DAT0_PX2"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PX3, "SDMMC1_DAT1_PX3"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PX4, "SDMMC1_DAT2_PX4"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PX5, "SDMMC1_DAT3_PX5"), + PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"), + PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH0, "CPU_PWR_REQ_PH0"), + PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH1, "GPU_PWR_REQ_PH1"), + PINCTRL_PIN(TEGRA_PIN_UART10_TX_PH2, "UART10_TX_PH2"), + PINCTRL_PIN(TEGRA_PIN_UART10_RX_PH3, "UART10_RX_PH3"), + PINCTRL_PIN(TEGRA_PIN_UART10_RTS_N_PH4, "UART10_RTS_N_PH4"), + PINCTRL_PIN(TEGRA_PIN_UART10_CTS_N_PH5, "UART10_CTS_N_PH5"), + PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PH6, "SPI3_SCK_PH6"), + PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PH7, "SPI3_MISO_PH7"), + PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PJ0, "SPI3_MOSI_PJ0"), + PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PJ1, "SPI3_CS0_PJ1"), + PINCTRL_PIN(TEGRA_PIN_SPI3_CS3_PJ2, "SPI3_CS3_PJ2"), + PINCTRL_PIN(TEGRA_PIN_UART5_TX_PJ3, "UART5_TX_PJ3"), + PINCTRL_PIN(TEGRA_PIN_UART5_RX_PJ4, "UART5_RX_PJ4"), + PINCTRL_PIN(TEGRA_PIN_UART5_RTS_N_PJ5, "UART5_RTS_N_PJ5"), + PINCTRL_PIN(TEGRA_PIN_UART5_CTS_N_PJ6, "UART5_CTS_N_PJ6"), + PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PJ7, "SPI1_SCK_PJ7"), + PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PK0, "SPI1_MISO_PK0"), + PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PK1, "SPI1_MOSI_PK1"), + PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PK2, "SPI1_CS0_PK2"), + PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PK3, "SPI1_CS1_PK3"), + PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PK4, "EXTPERIPH1_CLK_PK4"), + PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PK5, "EXTPERIPH2_CLK_PK5"), + PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SCL_PK6, "GEN12_I2C_SCL_PK6"), + PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SDA_PK7, "GEN12_I2C_SDA_PK7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO124_PL0, "SOC_GPIO124_PL0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO125_PL1, "SOC_GPIO125_PL1"), + PINCTRL_PIN(TEGRA_PIN_FAN_TACH0_PL2, "FAN_TACH0_PL2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO127_PL3, "SOC_GPIO127_PL3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO128_PL4, "SOC_GPIO128_PL4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO129_PL5, "SOC_GPIO129_PL5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO130_PL6, "SOC_GPIO130_PL6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO131_PL7, "SOC_GPIO131_PL7"), + PINCTRL_PIN(TEGRA_PIN_GP_PWM9_PM0, "GP_PWM9_PM0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO133_PM1, "SOC_GPIO133_PM1"), + PINCTRL_PIN(TEGRA_PIN_UART9_TX_PM2, "UART9_TX_PM2"), + PINCTRL_PIN(TEGRA_PIN_UART9_RX_PM3, "UART9_RX_PM3"), + PINCTRL_PIN(TEGRA_PIN_UART9_RTS_N_PM4, "UART9_RTS_N_PM4"), + PINCTRL_PIN(TEGRA_PIN_UART9_CTS_N_PM5, "UART9_CTS_N_PM5"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PT0, "QSPI0_SCK_PT0"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PT1, "QSPI0_CS_N_PT1"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PT2, "QSPI0_IO0_PT2"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PT3, "QSPI0_IO1_PT3"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PT4, "QSPI0_IO2_PT4"), + PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PT5, "QSPI0_IO3_PT5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO192_PT6, "SOC_GPIO192_PT6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PU0, "SOC_GPIO170_PU0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PU1, "SOC_GPIO171_PU1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PU2, "SOC_GPIO172_PU2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PU3, "SOC_GPIO173_PU3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO174_PU4, "SOC_GPIO174_PU4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO175_PU5, "SOC_GPIO175_PU5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO176_PU6, "SOC_GPIO176_PU6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO177_PU7, "SOC_GPIO177_PU7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO178_PV0, "SOC_GPIO178_PV0"), + PINCTRL_PIN(TEGRA_PIN_PWM10_PV1, "PWM10_PV1"), + PINCTRL_PIN(TEGRA_PIN_UART4_TX_PV2, "UART4_TX_PV2"), + PINCTRL_PIN(TEGRA_PIN_UART4_RX_PV3, "UART4_RX_PV3"), + PINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, "UART4_RTS_N_PV4"), + PINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, "UART4_CTS_N_PV5"), + PINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, "DAP2_CLK_PV6"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PW0, "DAP2_DIN_PW0"), + PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PV7, "DAP2_DOUT_PV7"), + PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, "DAP2_FS_PW1"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, "GEN1_I2C_SCL_PW2"), + PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, "GEN1_I2C_SDA_PW3"), + PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SCL_PW4, "GEN0_I2C_SCL_PW4"), + PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SDA_PW5, "GEN0_I2C_SDA_PW5"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PW6, "PWR_I2C_SCL_PW6"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PW7, "PWR_I2C_SDA_PW7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO270_PY0, "SOC_GPIO270_PY0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO271_PY1, "SOC_GPIO271_PY1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO272_PY2, "SOC_GPIO272_PY2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO273_PY3, "SOC_GPIO273_PY3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO274_PY4, "SOC_GPIO274_PY4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO275_PY5, "SOC_GPIO275_PY5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO276_PY6, "SOC_GPIO276_PY6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO277_PY7, "SOC_GPIO277_PY7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO278_PZ0, "SOC_GPIO278_PZ0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO279_PZ1, "SOC_GPIO279_PZ1"), + PINCTRL_PIN(TEGRA_PIN_XHALT_TRIG_PZ2, "XHALT_TRIG_PZ2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO281_PZ3, "SOC_GPIO281_PZ3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO282_PZ4, "SOC_GPIO282_PZ4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO283_PZ5, "SOC_GPIO283_PZ5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO284_PZ6, "SOC_GPIO284_PZ6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO285_PZ7, "SOC_GPIO285_PZ7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO286_PAL0, "SOC_GPIO286_PAL0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO287_PAL1, "SOC_GPIO287_PAL1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO288_PAL2, "SOC_GPIO288_PAL2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO138_PP0, "SOC_GPIO138_PP0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO139_PP1, "SOC_GPIO139_PP1"), + PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PP2, "DAP6_SCLK_PP2"), + PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PP3, "DAP6_DOUT_PP3"), + PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PP4, "DAP6_DIN_PP4"), + PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PP5, "DAP6_FS_PP5"), + PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP6, "DAP4_SCLK_PP6"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP7, "DAP4_DOUT_PP7"), + PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PQ0, "DAP4_DIN_PQ0"), + PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PQ1, "DAP4_FS_PQ1"), + PINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PQ2, "SPI5_SCK_PQ2"), + PINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PQ3, "SPI5_MISO_PQ3"), + PINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PQ4, "SPI5_MOSI_PQ4"), + PINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PQ5, "SPI5_CS0_PQ5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PQ6, "SOC_GPIO152_PQ6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PQ7, "SOC_GPIO153_PQ7"), + PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PR0, "AUD_MCLK_PR0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PR1, "SOC_GPIO155_PR1"), + PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PR2, "DAP1_SCLK_PR2"), + PINCTRL_PIN(TEGRA_PIN_DAP1_OUT_PR3, "DAP1_OUT_PR3"), + PINCTRL_PIN(TEGRA_PIN_DAP1_IN_PR4, "DAP1_IN_PR4"), + PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PR5, "DAP1_FS_PR5"), + PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SCL_PR6, "GEN11_I2C_SCL_PR6"), + PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SDA_PR7, "GEN11_I2C_SDA_PR7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO350_PS0, "SOC_GPIO350_PS0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO351_PS1, "SOC_GPIO351_PS1"), + +}; + +static const struct pinctrl_pin_desc tegra264_aon_pins[] = { + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA0, "SOC_GPIO00_PAA0"), + PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA1, "VCOMP_ALERT_PAA1"), + PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PAA2, "AO_RETENTION_N_PAA2"), + PINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA3, "BATT_OC_PAA3"), + PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA4, "BOOTV_CTL_N_PAA4"), + PINCTRL_PIN(TEGRA_PIN_POWER_ON_PAA5, "POWER_ON_PAA5"), + PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PAA6, "HDMI_CEC_PAA6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PAA7, "SOC_GPIO07_PAA7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PBB0, "SOC_GPIO08_PBB0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PBB1, "SOC_GPIO09_PBB1"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC0, "GEN2_I2C_SCL_PCC0"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PCC1, "GEN2_I2C_SDA_PCC1"), + PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PCC2, "GEN3_I2C_SCL_PCC2"), + PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PCC3, "GEN3_I2C_SDA_PCC3"), + PINCTRL_PIN(TEGRA_PIN_GP_PWM4_PCC4, "GP_PWM4_PCC4"), + PINCTRL_PIN(TEGRA_PIN_UART0_TX_PCC5, "UART0_TX_PCC5"), + PINCTRL_PIN(TEGRA_PIN_UART0_RX_PCC6, "UART0_RX_PCC6"), + PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC7, "SPI2_SCK_PCC7"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PDD0, "SPI2_MISO_PDD0"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PDD1, "SPI2_MOSI_PDD1"), + PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PDD2, "SPI2_CS0_N_PDD2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PDD3, "SOC_GPIO21_PDD3"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PDD4, "SOC_GPIO22_PDD4"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PDD5, "SOC_GPIO23_PDD5"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PDD6, "SOC_GPIO24_PDD6"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PDD7, "SOC_GPIO25_PDD7"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE0, "SOC_GPIO26_PEE0"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE1, "SOC_GPIO27_PEE1"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PEE2, "SOC_GPIO28_PEE2"), + PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PEE3, "SOC_GPIO29_PEE3"), +}; + +static const unsigned int soc_gpio250_pf0_pins[] = { + TEGRA_PIN_SOC_GPIO250_PF0, +}; + +static const unsigned int soc_gpio251_pf1_pins[] = { + TEGRA_PIN_SOC_GPIO251_PF1, +}; + +static const unsigned int soc_gpio252_pf2_pins[] = { + TEGRA_PIN_SOC_GPIO252_PF2, +}; + +static const unsigned int dp_aux_ch0_hpd_pf3_pins[] = { + TEGRA_PIN_DP_AUX_CH0_HPD_PF3, +}; + +static const unsigned int dp_aux_ch1_hpd_pf4_pins[] = { + TEGRA_PIN_DP_AUX_CH1_HPD_PF4, +}; + +static const unsigned int dp_aux_ch2_hpd_pf5_pins[] = { + TEGRA_PIN_DP_AUX_CH2_HPD_PF5, +}; + +static const unsigned int dp_aux_ch3_hpd_pf6_pins[] = { + TEGRA_PIN_DP_AUX_CH3_HPD_PF6, +}; + +static const unsigned int pwm2_pf7_pins[] = { + TEGRA_PIN_PWM2_PF7, +}; + +static const unsigned int pwm3_pg0_pins[] = { + TEGRA_PIN_PWM3_PG0, +}; + +static const unsigned int gen7_i2c_scl_pg1_pins[] = { + TEGRA_PIN_GEN7_I2C_SCL_PG1, +}; + +static const unsigned int gen7_i2c_sda_pg2_pins[] = { + TEGRA_PIN_GEN7_I2C_SDA_PG2, +}; + +static const unsigned int gen9_i2c_scl_pg3_pins[] = { + TEGRA_PIN_GEN9_I2C_SCL_PG3, +}; + +static const unsigned int gen9_i2c_sda_pg4_pins[] = { + TEGRA_PIN_GEN9_I2C_SDA_PG4, +}; + +static const unsigned int pwm1_pa0_pins[] = { + TEGRA_PIN_PWM1_PA0, +}; + +static const unsigned int pwm6_pa1_pins[] = { + TEGRA_PIN_PWM6_PA1, +}; + +static const unsigned int pwm7_pa2_pins[] = { + TEGRA_PIN_PWM7_PA2, +}; + +static const unsigned int pwm8_pa3_pins[] = { + TEGRA_PIN_PWM8_PA3, +}; + +static const unsigned int ufs0_ref_clk_pa4_pins[] = { + TEGRA_PIN_UFS0_REF_CLK_PA4, +}; + +static const unsigned int ufs0_rst_n_pa5_pins[] = { + TEGRA_PIN_UFS0_RST_N_PA5, +}; + +static const unsigned int pex_l1_clkreq_n_pb0_pins[] = { + TEGRA_PIN_PEX_L1_CLKREQ_N_PB0, +}; + +static const unsigned int pex_l1_rst_n_pb1_pins[] = { + TEGRA_PIN_PEX_L1_RST_N_PB1, +}; + +static const unsigned int pex_l2_clkreq_n_pb2_pins[] = { + TEGRA_PIN_PEX_L2_CLKREQ_N_PB2, +}; + +static const unsigned int pex_l2_rst_n_pb3_pins[] = { + TEGRA_PIN_PEX_L2_RST_N_PB3, +}; + +static const unsigned int pex_l3_clkreq_n_pb4_pins[] = { + TEGRA_PIN_PEX_L3_CLKREQ_N_PB4, +}; + +static const unsigned int pex_l3_rst_n_pb5_pins[] = { + TEGRA_PIN_PEX_L3_RST_N_PB5, +}; + +static const unsigned int soc_gpio113_pb6_pins[] = { + TEGRA_PIN_SOC_GPIO113_PB6, +}; + +static const unsigned int soc_gpio114_pb7_pins[] = { + TEGRA_PIN_SOC_GPIO114_PB7, +}; + +static const unsigned int sgmii0_sma_mdio_pc0_pins[] = { + TEGRA_PIN_SGMII0_SMA_MDIO_PC0, +}; + +static const unsigned int sgmii0_sma_mdc_pc1_pins[] = { + TEGRA_PIN_SGMII0_SMA_MDC_PC1, +}; + +static const unsigned int pex_wake_n_pc2_pins[] = { + TEGRA_PIN_PEX_WAKE_N_PC2, +}; + +static const unsigned int pex_l4_clkreq_n_pd0_pins[] = { + TEGRA_PIN_PEX_L4_CLKREQ_N_PD0, +}; + +static const unsigned int pex_l4_rst_n_pd1_pins[] = { + TEGRA_PIN_PEX_L4_RST_N_PD1, +}; + +static const unsigned int pex_l5_clkreq_n_pd2_pins[] = { + TEGRA_PIN_PEX_L5_CLKREQ_N_PD2, +}; + +static const unsigned int pex_l5_rst_n_pd3_pins[] = { + TEGRA_PIN_PEX_L5_RST_N_PD3, +}; + +static const unsigned int eth0_mdio_pd4_pins[] = { + TEGRA_PIN_ETH0_MDIO_PD4, +}; + +static const unsigned int eth0_mdc_pd5_pins[] = { + TEGRA_PIN_ETH0_MDC_PD5, +}; + +static const unsigned int eth3_mdio_pd6_pins[] = { + TEGRA_PIN_ETH3_MDIO_PD6, +}; + +static const unsigned int eth3_mdc_pd7_pins[] = { + TEGRA_PIN_ETH3_MDC_PD7, +}; + +static const unsigned int eth1_mdio_pe0_pins[] = { + TEGRA_PIN_ETH1_MDIO_PE0, +}; + +static const unsigned int eth1_mdc_pe1_pins[] = { + TEGRA_PIN_ETH1_MDC_PE1, +}; + +static const unsigned int eth2_mdio_pe2_pins[] = { + TEGRA_PIN_ETH2_MDIO_PE2, +}; + +static const unsigned int eth2_mdc_pe3_pins[] = { + TEGRA_PIN_ETH2_MDC_PE3, +}; + +static const unsigned int sdmmc1_clk_px0_pins[] = { + TEGRA_PIN_SDMMC1_CLK_PX0, +}; + +static const unsigned int sdmmc1_cmd_px1_pins[] = { + TEGRA_PIN_SDMMC1_CMD_PX1, +}; + +static const unsigned int sdmmc1_dat0_px2_pins[] = { + TEGRA_PIN_SDMMC1_DAT0_PX2, +}; + +static const unsigned int sdmmc1_dat1_px3_pins[] = { + TEGRA_PIN_SDMMC1_DAT1_PX3, +}; + +static const unsigned int sdmmc1_dat2_px4_pins[] = { + TEGRA_PIN_SDMMC1_DAT2_PX4, +}; + +static const unsigned int sdmmc1_dat3_px5_pins[] = { + TEGRA_PIN_SDMMC1_DAT3_PX5, +}; + +static const unsigned int sdmmc1_comp_pins[] = { + TEGRA_PIN_SDMMC1_COMP, +}; + +static const unsigned int cpu_pwr_req_ph0_pins[] = { + TEGRA_PIN_CPU_PWR_REQ_PH0, +}; + +static const unsigned int gpu_pwr_req_ph1_pins[] = { + TEGRA_PIN_GPU_PWR_REQ_PH1, +}; + +static const unsigned int uart10_tx_ph2_pins[] = { + TEGRA_PIN_UART10_TX_PH2, +}; + +static const unsigned int uart10_rx_ph3_pins[] = { + TEGRA_PIN_UART10_RX_PH3, +}; + +static const unsigned int uart10_rts_n_ph4_pins[] = { + TEGRA_PIN_UART10_RTS_N_PH4, +}; + +static const unsigned int uart10_cts_n_ph5_pins[] = { + TEGRA_PIN_UART10_CTS_N_PH5, +}; + +static const unsigned int spi3_sck_ph6_pins[] = { + TEGRA_PIN_SPI3_SCK_PH6, +}; + +static const unsigned int spi3_miso_ph7_pins[] = { + TEGRA_PIN_SPI3_MISO_PH7, +}; + +static const unsigned int spi3_mosi_pj0_pins[] = { + TEGRA_PIN_SPI3_MOSI_PJ0, +}; + +static const unsigned int spi3_cs0_pj1_pins[] = { + TEGRA_PIN_SPI3_CS0_PJ1, +}; + +static const unsigned int spi3_cs3_pj2_pins[] = { + TEGRA_PIN_SPI3_CS3_PJ2, +}; + +static const unsigned int uart5_tx_pj3_pins[] = { + TEGRA_PIN_UART5_TX_PJ3, +}; + +static const unsigned int uart5_rx_pj4_pins[] = { + TEGRA_PIN_UART5_RX_PJ4, +}; + +static const unsigned int uart5_rts_n_pj5_pins[] = { + TEGRA_PIN_UART5_RTS_N_PJ5, +}; + +static const unsigned int uart5_cts_n_pj6_pins[] = { + TEGRA_PIN_UART5_CTS_N_PJ6, +}; + +static const unsigned int spi1_sck_pj7_pins[] = { + TEGRA_PIN_SPI1_SCK_PJ7, +}; + +static const unsigned int spi1_miso_pk0_pins[] = { + TEGRA_PIN_SPI1_MISO_PK0, +}; + +static const unsigned int spi1_mosi_pk1_pins[] = { + TEGRA_PIN_SPI1_MOSI_PK1, +}; + +static const unsigned int spi1_cs0_pk2_pins[] = { + TEGRA_PIN_SPI1_CS0_PK2, +}; + +static const unsigned int spi1_cs1_pk3_pins[] = { + TEGRA_PIN_SPI1_CS1_PK3, +}; + +static const unsigned int extperiph1_clk_pk4_pins[] = { + TEGRA_PIN_EXTPERIPH1_CLK_PK4, +}; + +static const unsigned int extperiph2_clk_pk5_pins[] = { + TEGRA_PIN_EXTPERIPH2_CLK_PK5, +}; + +static const unsigned int gen12_i2c_scl_pk6_pins[] = { + TEGRA_PIN_GEN12_I2C_SCL_PK6, +}; + +static const unsigned int gen12_i2c_sda_pk7_pins[] = { + TEGRA_PIN_GEN12_I2C_SDA_PK7, +}; + +static const unsigned int soc_gpio124_pl0_pins[] = { + TEGRA_PIN_SOC_GPIO124_PL0, +}; + +static const unsigned int soc_gpio125_pl1_pins[] = { + TEGRA_PIN_SOC_GPIO125_PL1, +}; + +static const unsigned int fan_tach0_pl2_pins[] = { + TEGRA_PIN_FAN_TACH0_PL2, +}; + +static const unsigned int soc_gpio127_pl3_pins[] = { + TEGRA_PIN_SOC_GPIO127_PL3, +}; + +static const unsigned int soc_gpio128_pl4_pins[] = { + TEGRA_PIN_SOC_GPIO128_PL4, +}; + +static const unsigned int soc_gpio129_pl5_pins[] = { + TEGRA_PIN_SOC_GPIO129_PL5, +}; + +static const unsigned int soc_gpio130_pl6_pins[] = { + TEGRA_PIN_SOC_GPIO130_PL6, +}; + +static const unsigned int soc_gpio131_pl7_pins[] = { + TEGRA_PIN_SOC_GPIO131_PL7, +}; + +static const unsigned int gp_pwm9_pm0_pins[] = { + TEGRA_PIN_GP_PWM9_PM0, +}; + +static const unsigned int soc_gpio133_pm1_pins[] = { + TEGRA_PIN_SOC_GPIO133_PM1, +}; + +static const unsigned int uart9_tx_pm2_pins[] = { + TEGRA_PIN_UART9_TX_PM2, +}; + +static const unsigned int uart9_rx_pm3_pins[] = { + TEGRA_PIN_UART9_RX_PM3, +}; + +static const unsigned int uart9_rts_n_pm4_pins[] = { + TEGRA_PIN_UART9_RTS_N_PM4, +}; + +static const unsigned int uart9_cts_n_pm5_pins[] = { + TEGRA_PIN_UART9_CTS_N_PM5, +}; + +static const unsigned int soc_gpio170_pu0_pins[] = { + TEGRA_PIN_SOC_GPIO170_PU0, +}; + +static const unsigned int soc_gpio171_pu1_pins[] = { + TEGRA_PIN_SOC_GPIO171_PU1, +}; + +static const unsigned int soc_gpio172_pu2_pins[] = { + TEGRA_PIN_SOC_GPIO172_PU2, +}; + +static const unsigned int soc_gpio173_pu3_pins[] = { + TEGRA_PIN_SOC_GPIO173_PU3, +}; + +static const unsigned int soc_gpio174_pu4_pins[] = { + TEGRA_PIN_SOC_GPIO174_PU4, +}; + +static const unsigned int soc_gpio175_pu5_pins[] = { + TEGRA_PIN_SOC_GPIO175_PU5, +}; + +static const unsigned int soc_gpio176_pu6_pins[] = { + TEGRA_PIN_SOC_GPIO176_PU6, +}; + +static const unsigned int soc_gpio177_pu7_pins[] = { + TEGRA_PIN_SOC_GPIO177_PU7, +}; + +static const unsigned int soc_gpio178_pv0_pins[] = { + TEGRA_PIN_SOC_GPIO178_PV0, +}; + +static const unsigned int pwm10_pv1_pins[] = { + TEGRA_PIN_PWM10_PV1, +}; + +static const unsigned int uart4_tx_pv2_pins[] = { + TEGRA_PIN_UART4_TX_PV2, +}; + +static const unsigned int uart4_rx_pv3_pins[] = { + TEGRA_PIN_UART4_RX_PV3, +}; + +static const unsigned int uart4_rts_n_pv4_pins[] = { + TEGRA_PIN_UART4_RTS_N_PV4, +}; + +static const unsigned int uart4_cts_n_pv5_pins[] = { + TEGRA_PIN_UART4_CTS_N_PV5, +}; + +static const unsigned int dap2_clk_pv6_pins[] = { + TEGRA_PIN_DAP2_CLK_PV6, +}; + +static const unsigned int dap2_din_pw0_pins[] = { + TEGRA_PIN_DAP2_DIN_PW0, +}; + +static const unsigned int dap2_dout_pv7_pins[] = { + TEGRA_PIN_DAP2_DOUT_PV7, +}; + +static const unsigned int dap2_fs_pw1_pins[] = { + TEGRA_PIN_DAP2_FS_PW1, +}; + +static const unsigned int gen1_i2c_scl_pw2_pins[] = { + TEGRA_PIN_GEN1_I2C_SCL_PW2, +}; + +static const unsigned int gen1_i2c_sda_pw3_pins[] = { + TEGRA_PIN_GEN1_I2C_SDA_PW3, +}; + +static const unsigned int gen0_i2c_scl_pw4_pins[] = { + TEGRA_PIN_GEN0_I2C_SCL_PW4, +}; + +static const unsigned int gen0_i2c_sda_pw5_pins[] = { + TEGRA_PIN_GEN0_I2C_SDA_PW5, +}; + +static const unsigned int pwr_i2c_scl_pw6_pins[] = { + TEGRA_PIN_PWR_I2C_SCL_PW6, +}; + +static const unsigned int pwr_i2c_sda_pw7_pins[] = { + TEGRA_PIN_PWR_I2C_SDA_PW7, +}; + +static const unsigned int qspi0_sck_pt0_pins[] = { + TEGRA_PIN_QSPI0_SCK_PT0, +}; + +static const unsigned int qspi0_cs_n_pt1_pins[] = { + TEGRA_PIN_QSPI0_CS_N_PT1, +}; + +static const unsigned int qspi0_io0_pt2_pins[] = { + TEGRA_PIN_QSPI0_IO0_PT2, +}; + +static const unsigned int qspi0_io1_pt3_pins[] = { + TEGRA_PIN_QSPI0_IO1_PT3, +}; + +static const unsigned int qspi0_io2_pt4_pins[] = { + TEGRA_PIN_QSPI0_IO2_PT4, +}; + +static const unsigned int qspi0_io3_pt5_pins[] = { + TEGRA_PIN_QSPI0_IO3_PT5, +}; + +static const unsigned int soc_gpio192_pt6_pins[] = { + TEGRA_PIN_SOC_GPIO192_PT6, +}; + +static const unsigned int soc_gpio138_pp0_pins[] = { + TEGRA_PIN_SOC_GPIO138_PP0, +}; + +static const unsigned int soc_gpio139_pp1_pins[] = { + TEGRA_PIN_SOC_GPIO139_PP1, +}; + +static const unsigned int dap6_sclk_pp2_pins[] = { + TEGRA_PIN_DAP6_SCLK_PP2, +}; + +static const unsigned int dap6_dout_pp3_pins[] = { + TEGRA_PIN_DAP6_DOUT_PP3, +}; + +static const unsigned int dap6_din_pp4_pins[] = { + TEGRA_PIN_DAP6_DIN_PP4, +}; + +static const unsigned int dap6_fs_pp5_pins[] = { + TEGRA_PIN_DAP6_FS_PP5, +}; + +static const unsigned int dap4_sclk_pp6_pins[] = { + TEGRA_PIN_DAP4_SCLK_PP6, +}; + +static const unsigned int dap4_dout_pp7_pins[] = { + TEGRA_PIN_DAP4_DOUT_PP7, +}; + +static const unsigned int dap4_din_pq0_pins[] = { + TEGRA_PIN_DAP4_DIN_PQ0, +}; + +static const unsigned int dap4_fs_pq1_pins[] = { + TEGRA_PIN_DAP4_FS_PQ1, +}; + +static const unsigned int spi5_sck_pq2_pins[] = { + TEGRA_PIN_SPI5_SCK_PQ2, +}; + +static const unsigned int spi5_miso_pq3_pins[] = { + TEGRA_PIN_SPI5_MISO_PQ3, +}; + +static const unsigned int spi5_mosi_pq4_pins[] = { + TEGRA_PIN_SPI5_MOSI_PQ4, +}; + +static const unsigned int spi5_cs0_pq5_pins[] = { + TEGRA_PIN_SPI5_CS0_PQ5, +}; + +static const unsigned int soc_gpio152_pq6_pins[] = { + TEGRA_PIN_SOC_GPIO152_PQ6, +}; + +static const unsigned int soc_gpio153_pq7_pins[] = { + TEGRA_PIN_SOC_GPIO153_PQ7, +}; + +static const unsigned int aud_mclk_pr0_pins[] = { + TEGRA_PIN_AUD_MCLK_PR0, +}; + +static const unsigned int soc_gpio155_pr1_pins[] = { + TEGRA_PIN_SOC_GPIO155_PR1, +}; + +static const unsigned int dap1_sclk_pr2_pins[] = { + TEGRA_PIN_DAP1_SCLK_PR2, +}; + +static const unsigned int dap1_out_pr3_pins[] = { + TEGRA_PIN_DAP1_OUT_PR3, +}; + +static const unsigned int dap1_in_pr4_pins[] = { + TEGRA_PIN_DAP1_IN_PR4, +}; + +static const unsigned int dap1_fs_pr5_pins[] = { + TEGRA_PIN_DAP1_FS_PR5, +}; + +static const unsigned int gen11_i2c_scl_pr6_pins[] = { + TEGRA_PIN_GEN11_I2C_SCL_PR6, +}; + +static const unsigned int gen11_i2c_sda_pr7_pins[] = { + TEGRA_PIN_GEN11_I2C_SDA_PR7, +}; + +static const unsigned int soc_gpio350_ps0_pins[] = { + TEGRA_PIN_SOC_GPIO350_PS0, +}; + +static const unsigned int soc_gpio351_ps1_pins[] = { + TEGRA_PIN_SOC_GPIO351_PS1, +}; + +static const unsigned int soc_gpio270_py0_pins[] = { + TEGRA_PIN_SOC_GPIO270_PY0, +}; + +static const unsigned int soc_gpio271_py1_pins[] = { + TEGRA_PIN_SOC_GPIO271_PY1, +}; + +static const unsigned int soc_gpio272_py2_pins[] = { + TEGRA_PIN_SOC_GPIO272_PY2, +}; + +static const unsigned int soc_gpio273_py3_pins[] = { + TEGRA_PIN_SOC_GPIO273_PY3, +}; + +static const unsigned int soc_gpio274_py4_pins[] = { + TEGRA_PIN_SOC_GPIO274_PY4, +}; + +static const unsigned int soc_gpio275_py5_pins[] = { + TEGRA_PIN_SOC_GPIO275_PY5, +}; + +static const unsigned int soc_gpio276_py6_pins[] = { + TEGRA_PIN_SOC_GPIO276_PY6, +}; + +static const unsigned int soc_gpio277_py7_pins[] = { + TEGRA_PIN_SOC_GPIO277_PY7, +}; + +static const unsigned int soc_gpio278_pz0_pins[] = { + TEGRA_PIN_SOC_GPIO278_PZ0, +}; + +static const unsigned int soc_gpio279_pz1_pins[] = { + TEGRA_PIN_SOC_GPIO279_PZ1, +}; + +static const unsigned int xhalt_trig_pz2_pins[] = { + TEGRA_PIN_XHALT_TRIG_PZ2, +}; + +static const unsigned int soc_gpio281_pz3_pins[] = { + TEGRA_PIN_SOC_GPIO281_PZ3, +}; + +static const unsigned int soc_gpio282_pz4_pins[] = { + TEGRA_PIN_SOC_GPIO282_PZ4, +}; + +static const unsigned int soc_gpio283_pz5_pins[] = { + TEGRA_PIN_SOC_GPIO283_PZ5, +}; + +static const unsigned int soc_gpio284_pz6_pins[] = { + TEGRA_PIN_SOC_GPIO284_PZ6, +}; + +static const unsigned int soc_gpio285_pz7_pins[] = { + TEGRA_PIN_SOC_GPIO285_PZ7, +}; + +static const unsigned int soc_gpio286_pal0_pins[] = { + TEGRA_PIN_SOC_GPIO286_PAL0, +}; + +static const unsigned int soc_gpio287_pal1_pins[] = { + TEGRA_PIN_SOC_GPIO287_PAL1, +}; + +static const unsigned int soc_gpio288_pal2_pins[] = { + TEGRA_PIN_SOC_GPIO288_PAL2, +}; + +static const unsigned int soc_gpio00_paa0_pins[] = { + TEGRA_PIN_SOC_GPIO00_PAA0, +}; + +static const unsigned int vcomp_alert_paa1_pins[] = { + TEGRA_PIN_VCOMP_ALERT_PAA1, +}; + +static const unsigned int ao_retention_n_paa2_pins[] = { + TEGRA_PIN_AO_RETENTION_N_PAA2, +}; + +static const unsigned int batt_oc_paa3_pins[] = { + TEGRA_PIN_BATT_OC_PAA3, +}; + +static const unsigned int bootv_ctl_n_paa4_pins[] = { + TEGRA_PIN_BOOTV_CTL_N_PAA4, +}; + +static const unsigned int power_on_paa5_pins[] = { + TEGRA_PIN_POWER_ON_PAA5, +}; + +static const unsigned int hdmi_cec_paa6_pins[] = { + TEGRA_PIN_HDMI_CEC_PAA6, +}; + +static const unsigned int soc_gpio07_paa7_pins[] = { + TEGRA_PIN_SOC_GPIO07_PAA7, +}; + +static const unsigned int soc_gpio08_pbb0_pins[] = { + TEGRA_PIN_SOC_GPIO08_PBB0, +}; + +static const unsigned int soc_gpio09_pbb1_pins[] = { + TEGRA_PIN_SOC_GPIO09_PBB1, +}; + +static const unsigned int gen2_i2c_scl_pcc0_pins[] = { + TEGRA_PIN_GEN2_I2C_SCL_PCC0, +}; + +static const unsigned int gen2_i2c_sda_pcc1_pins[] = { + TEGRA_PIN_GEN2_I2C_SDA_PCC1, +}; + +static const unsigned int gen3_i2c_scl_pcc2_pins[] = { + TEGRA_PIN_GEN3_I2C_SCL_PCC2, +}; + +static const unsigned int gen3_i2c_sda_pcc3_pins[] = { + TEGRA_PIN_GEN3_I2C_SDA_PCC3, +}; + +static const unsigned int gp_pwm4_pcc4_pins[] = { + TEGRA_PIN_GP_PWM4_PCC4, +}; + +static const unsigned int uart0_tx_pcc5_pins[] = { + TEGRA_PIN_UART0_TX_PCC5, +}; + +static const unsigned int uart0_rx_pcc6_pins[] = { + TEGRA_PIN_UART0_RX_PCC6, +}; + +static const unsigned int spi2_sck_pcc7_pins[] = { + TEGRA_PIN_SPI2_SCK_PCC7, +}; + +static const unsigned int spi2_miso_pdd0_pins[] = { + TEGRA_PIN_SPI2_MISO_PDD0, +}; + +static const unsigned int spi2_mosi_pdd1_pins[] = { + TEGRA_PIN_SPI2_MOSI_PDD1, +}; + +static const unsigned int spi2_cs0_n_pdd2_pins[] = { + TEGRA_PIN_SPI2_CS0_N_PDD2, +}; + +static const unsigned int soc_gpio21_pdd3_pins[] = { + TEGRA_PIN_SOC_GPIO21_PDD3, +}; + +static const unsigned int soc_gpio22_pdd4_pins[] = { + TEGRA_PIN_SOC_GPIO22_PDD4, +}; + +static const unsigned int soc_gpio23_pdd5_pins[] = { + TEGRA_PIN_SOC_GPIO23_PDD5, +}; + +static const unsigned int soc_gpio24_pdd6_pins[] = { + TEGRA_PIN_SOC_GPIO24_PDD6, +}; + +static const unsigned int soc_gpio25_pdd7_pins[] = { + TEGRA_PIN_SOC_GPIO25_PDD7, +}; + +static const unsigned int soc_gpio26_pee0_pins[] = { + TEGRA_PIN_SOC_GPIO26_PEE0, +}; + +static const unsigned int soc_gpio27_pee1_pins[] = { + TEGRA_PIN_SOC_GPIO27_PEE1, +}; + +static const unsigned int soc_gpio28_pee2_pins[] = { + TEGRA_PIN_SOC_GPIO28_PEE2, +}; + +static const unsigned int soc_gpio29_pee3_pins[] = { + TEGRA_PIN_SOC_GPIO29_PEE3, +}; + +enum tegra_mux_dt { + TEGRA_MUX_DCA_VSYNC, + TEGRA_MUX_DCA_HSYNC, + TEGRA_MUX_RSVD0, + TEGRA_MUX_DP_AUX_CH0_HPD, + TEGRA_MUX_DP_AUX_CH1_HPD, + TEGRA_MUX_DP_AUX_CH2_HPD, + TEGRA_MUX_DP_AUX_CH3_HPD, + TEGRA_MUX_GP_PWM2, + TEGRA_MUX_GP_PWM3, + TEGRA_MUX_I2C7_CLK, + TEGRA_MUX_I2C7_DAT, + TEGRA_MUX_I2C9_CLK, + TEGRA_MUX_I2C9_DAT, + TEGRA_MUX_UARTK_CTS, + TEGRA_MUX_UARTK_RTS, + TEGRA_MUX_UARTK_RXD, + TEGRA_MUX_UARTK_TXD, + TEGRA_MUX_SPI3_CS0, + TEGRA_MUX_SPI3_CS3, + TEGRA_MUX_SPI3_DIN, + TEGRA_MUX_SPI3_DOUT, + TEGRA_MUX_SPI3_SCK, + TEGRA_MUX_UARTF_CTS, + TEGRA_MUX_UARTF_RTS, + TEGRA_MUX_UARTF_RXD, + TEGRA_MUX_UARTF_TXD, + TEGRA_MUX_SPI1_CS0, + TEGRA_MUX_SPI1_CS1, + TEGRA_MUX_SPI1_DIN, + TEGRA_MUX_SPI1_DOUT, + TEGRA_MUX_SPI1_SCK, + TEGRA_MUX_EXTPERIPH2_CLK, + TEGRA_MUX_EXTPERIPH1_CLK, + TEGRA_MUX_I2C12_CLK, + TEGRA_MUX_I2C12_DAT, + TEGRA_MUX_NV_THERM_FAN_TACH0, + TEGRA_MUX_GP_PWM9, + TEGRA_MUX_UARTJ_CTS, + TEGRA_MUX_UARTJ_RTS, + TEGRA_MUX_UARTJ_RXD, + TEGRA_MUX_UARTJ_TXD, + TEGRA_MUX_I2C0_CLK, + TEGRA_MUX_I2C0_DAT, + TEGRA_MUX_I2C1_CLK, + TEGRA_MUX_I2C1_DAT, + TEGRA_MUX_I2S2_LRCK, + TEGRA_MUX_I2S2_SCLK, + TEGRA_MUX_I2S2_SDATA_OUT, + TEGRA_MUX_I2S2_SDATA_IN, + TEGRA_MUX_GP_PWM10, + TEGRA_MUX_UARTE_CTS, + TEGRA_MUX_UARTE_RTS, + TEGRA_MUX_UARTE_RXD, + TEGRA_MUX_UARTE_TXD, + TEGRA_MUX_I2C5_DAT, + TEGRA_MUX_I2C5_CLK, + TEGRA_MUX_I2S6_SDATA_IN, + TEGRA_MUX_I2S6_SDATA_OUT, + TEGRA_MUX_I2S6_LRCK, + TEGRA_MUX_I2S6_SCLK, + TEGRA_MUX_I2S4_SDATA_OUT, + TEGRA_MUX_I2S4_SCLK, + TEGRA_MUX_I2S4_SDATA_IN, + TEGRA_MUX_I2S4_LRCK, + TEGRA_MUX_SPI5_CS0, + TEGRA_MUX_SPI5_DIN, + TEGRA_MUX_SPI5_DOUT, + TEGRA_MUX_SPI5_SCK, + TEGRA_MUX_AUD_MCLK, + TEGRA_MUX_I2S1_SCLK, + TEGRA_MUX_I2S1_SDATA_IN, + TEGRA_MUX_I2S1_SDATA_OUT, + TEGRA_MUX_I2S1_LRCK, + TEGRA_MUX_I2C11_CLK, + TEGRA_MUX_I2C11_DAT, + TEGRA_MUX_XHALT_TRIG, + TEGRA_MUX_GP_PWM1, + TEGRA_MUX_GP_PWM6, + TEGRA_MUX_GP_PWM7, + TEGRA_MUX_GP_PWM8, + TEGRA_MUX_UFS0, + TEGRA_MUX_PE1_CLKREQ_L, + TEGRA_MUX_PE1_RST_L, + TEGRA_MUX_PE2_RST_L, + TEGRA_MUX_PE2_CLKREQ_L, + TEGRA_MUX_PE3_CLKREQ_L, + TEGRA_MUX_PE3_RST_L, + TEGRA_MUX_SGMII0_SMA_MDIO, + TEGRA_MUX_SGMII0_SMA_MDC, + TEGRA_MUX_USB_VBUS_EN0, + TEGRA_MUX_USB_VBUS_EN1, + TEGRA_MUX_ETH1_MDIO, + TEGRA_MUX_PE4_CLKREQ_L, + TEGRA_MUX_PE4_RST_L, + TEGRA_MUX_PE5_CLKREQ_L, + TEGRA_MUX_PE5_RST_L, + TEGRA_MUX_ETH0_MDIO, + TEGRA_MUX_ETH0_MDC, + TEGRA_MUX_ETH1_MDC, + TEGRA_MUX_ETH2_MDIO, + TEGRA_MUX_ETH2_MDC, + TEGRA_MUX_ETH3_MDIO, + TEGRA_MUX_ETH3_MDC, + TEGRA_MUX_QSPI0_CS_N, + TEGRA_MUX_QSPI0_IO0, + TEGRA_MUX_QSPI0_IO1, + TEGRA_MUX_QSPI0_IO2, + TEGRA_MUX_QSPI0_IO3, + TEGRA_MUX_QSPI0_SCK, + TEGRA_MUX_SDMMC1_CLK, + TEGRA_MUX_SDMMC1_CMD, + TEGRA_MUX_SDMMC1_COMP, + TEGRA_MUX_SDMMC1_DAT3, + TEGRA_MUX_SDMMC1_DAT2, + TEGRA_MUX_SDMMC1_DAT1, + TEGRA_MUX_SDMMC1_DAT0, + TEGRA_MUX_QSPI3_SCK, + TEGRA_MUX_QSPI3_CS0, + TEGRA_MUX_QSPI3_IO0, + TEGRA_MUX_QSPI3_IO1, + TEGRA_MUX_DCB_VSYNC, + TEGRA_MUX_DCB_HSYNC, + TEGRA_MUX_DSA_LSPII, + TEGRA_MUX_DCE_VSYNC, + TEGRA_MUX_DCE_HSYNC, + TEGRA_MUX_DCH_VSYNC, + TEGRA_MUX_DCH_HSYNC, + TEGRA_MUX_BL_EN, + TEGRA_MUX_BL_PWM_DIM0, + TEGRA_MUX_RSVD1, + TEGRA_MUX_SOC_THERM_OC3, + TEGRA_MUX_I2S5_SCLK, + TEGRA_MUX_I2S5_SDATA_IN, + TEGRA_MUX_EXTPERIPH3_CLK, + TEGRA_MUX_EXTPERIPH4_CLK, + TEGRA_MUX_I2S5_SDATA_OUT, + TEGRA_MUX_I2S5_LRCK, + TEGRA_MUX_SDMMC1_CD, + TEGRA_MUX_I2S7_SDATA_IN, + TEGRA_MUX_SPI4_SCK, + TEGRA_MUX_SPI4_DIN, + TEGRA_MUX_SPI4_DOUT, + TEGRA_MUX_SPI4_CS0, + TEGRA_MUX_SPI4_CS1, + TEGRA_MUX_GP_PWM5, + TEGRA_MUX_I2C14_CLK, + TEGRA_MUX_I2C14_DAT, + TEGRA_MUX_I2S8_SCLK, + TEGRA_MUX_I2S8_SDATA_OUT, + TEGRA_MUX_I2S8_LRCK, + TEGRA_MUX_I2S8_SDATA_IN, + TEGRA_MUX_I2C16_CLK, + TEGRA_MUX_I2C16_DAT, + TEGRA_MUX_I2S3_SCLK, + TEGRA_MUX_I2S3_SDATA_OUT, + TEGRA_MUX_I2S3_SDATA_IN, + TEGRA_MUX_I2S3_LRCK, + TEGRA_MUX_PM_TRIG1, + TEGRA_MUX_PM_TRIG0, + TEGRA_MUX_QSPI2_SCK, + TEGRA_MUX_QSPI2_CS0, + TEGRA_MUX_QSPI2_IO0, + TEGRA_MUX_QSPI2_IO1, + TEGRA_MUX_DCC_VSYNC, + TEGRA_MUX_DCC_HSYNC, + TEGRA_MUX_RSVD2, + TEGRA_MUX_DCF_VSYNC, + TEGRA_MUX_DCF_HSYNC, + TEGRA_MUX_SOUNDWIRE1_CLK, + TEGRA_MUX_SOUNDWIRE1_DAT0, + TEGRA_MUX_SOUNDWIRE1_DAT1, + TEGRA_MUX_SOUNDWIRE1_DAT2, + TEGRA_MUX_DMIC2_CLK, + TEGRA_MUX_DMIC2_DAT, + TEGRA_MUX_NV_THERM_FAN_TACH1, + TEGRA_MUX_I2C15_CLK, + TEGRA_MUX_I2C15_DAT, + TEGRA_MUX_I2S7_LRCK, + TEGRA_MUX_CCLA_LA_TRIGGER_MUX, + TEGRA_MUX_I2S7_SCLK, + TEGRA_MUX_I2S7_SDATA_OUT, + TEGRA_MUX_DMIC1_DAT, + TEGRA_MUX_DMIC1_CLK, + TEGRA_MUX_DCD_VSYNC, + TEGRA_MUX_DCD_HSYNC, + TEGRA_MUX_RSVD3, + TEGRA_MUX_DCG_VSYNC, + TEGRA_MUX_DCG_HSYNC, + TEGRA_MUX_DSPK1_CLK, + TEGRA_MUX_DSPK1_DAT, + TEGRA_MUX_SOC_THERM_OC2, + TEGRA_MUX_ISTCTRL_IST_DONE_N, + TEGRA_MUX_SOC_THERM_OC1, + TEGRA_MUX_TSC_EDGE_OUT0C, + TEGRA_MUX_TSC_EDGE_OUT0D, + TEGRA_MUX_TSC_EDGE_OUT0A, + TEGRA_MUX_TSC_EDGE_OUT0B, + TEGRA_MUX_TOUCH_CLK, + TEGRA_MUX_HDMI_CEC, + TEGRA_MUX_I2C2_CLK, + TEGRA_MUX_I2C2_DAT, + TEGRA_MUX_I2C3_CLK, + TEGRA_MUX_I2C3_DAT, + TEGRA_MUX_GP_PWM4, + TEGRA_MUX_UARTA_TXD, + TEGRA_MUX_UARTA_RXD, + TEGRA_MUX_SPI2_SCK, + TEGRA_MUX_SPI2_DIN, + TEGRA_MUX_SPI2_DOUT, + TEGRA_MUX_SPI2_CS0, + TEGRA_MUX_TSC_SYNC1, + TEGRA_MUX_TSC_EDGE_OUT3, + TEGRA_MUX_TSC_EDGE_OUT0, + TEGRA_MUX_TSC_EDGE_OUT1, + TEGRA_MUX_TSC_SYNC0, + TEGRA_MUX_SOUNDWIRE0_CLK, + TEGRA_MUX_SOUNDWIRE0_DAT0, + TEGRA_MUX_L0L1_RST_OUT_N, + TEGRA_MUX_L2_RST_OUT_N, + TEGRA_MUX_UARTL_TXD, + TEGRA_MUX_UARTL_RXD, + TEGRA_MUX_I2S9_SCLK, + TEGRA_MUX_I2S9_SDATA_OUT, + TEGRA_MUX_I2S9_SDATA_IN, + TEGRA_MUX_I2S9_LRCK, + TEGRA_MUX_DMIC5_DAT, + TEGRA_MUX_DMIC5_CLK, + TEGRA_MUX_TSC_EDGE_OUT2, +}; + +/* Make list of each function name */ +#define TEGRA_PIN_FUNCTION(lid) #lid + +static const char * const tegra264_functions[] = { + TEGRA_PIN_FUNCTION(dca_vsync), + TEGRA_PIN_FUNCTION(dca_hsync), + TEGRA_PIN_FUNCTION(rsvd0), + TEGRA_PIN_FUNCTION(dp_aux_ch0_hpd), + TEGRA_PIN_FUNCTION(dp_aux_ch1_hpd), + TEGRA_PIN_FUNCTION(dp_aux_ch2_hpd), + TEGRA_PIN_FUNCTION(dp_aux_ch3_hpd), + TEGRA_PIN_FUNCTION(gp_pwm2), + TEGRA_PIN_FUNCTION(gp_pwm3), + TEGRA_PIN_FUNCTION(i2c7_clk), + TEGRA_PIN_FUNCTION(i2c7_dat), + TEGRA_PIN_FUNCTION(i2c9_clk), + TEGRA_PIN_FUNCTION(i2c9_dat), + TEGRA_PIN_FUNCTION(uartk_cts), + TEGRA_PIN_FUNCTION(uartk_rts), + TEGRA_PIN_FUNCTION(uartk_rxd), + TEGRA_PIN_FUNCTION(uartk_txd), + TEGRA_PIN_FUNCTION(spi3_cs0), + TEGRA_PIN_FUNCTION(spi3_cs3), + TEGRA_PIN_FUNCTION(spi3_din), + TEGRA_PIN_FUNCTION(spi3_dout), + TEGRA_PIN_FUNCTION(spi3_sck), + TEGRA_PIN_FUNCTION(uartf_cts), + TEGRA_PIN_FUNCTION(uartf_rts), + TEGRA_PIN_FUNCTION(uartf_rxd), + TEGRA_PIN_FUNCTION(uartf_txd), + TEGRA_PIN_FUNCTION(spi1_cs0), + TEGRA_PIN_FUNCTION(spi1_cs1), + TEGRA_PIN_FUNCTION(spi1_din), + TEGRA_PIN_FUNCTION(spi1_dout), + TEGRA_PIN_FUNCTION(spi1_sck), + TEGRA_PIN_FUNCTION(extperiph2_clk), + TEGRA_PIN_FUNCTION(extperiph1_clk), + TEGRA_PIN_FUNCTION(i2c12_clk), + TEGRA_PIN_FUNCTION(i2c12_dat), + TEGRA_PIN_FUNCTION(nv_therm_fan_tach0), + TEGRA_PIN_FUNCTION(gp_pwm9), + TEGRA_PIN_FUNCTION(uartj_cts), + TEGRA_PIN_FUNCTION(uartj_rts), + TEGRA_PIN_FUNCTION(uartj_rxd), + TEGRA_PIN_FUNCTION(uartj_txd), + TEGRA_PIN_FUNCTION(i2c0_clk), + TEGRA_PIN_FUNCTION(i2c0_dat), + TEGRA_PIN_FUNCTION(i2c1_clk), + TEGRA_PIN_FUNCTION(i2c1_dat), + TEGRA_PIN_FUNCTION(i2s2_lrck), + TEGRA_PIN_FUNCTION(i2s2_sclk), + TEGRA_PIN_FUNCTION(i2s2_sdata_out), + TEGRA_PIN_FUNCTION(i2s2_sdata_in), + TEGRA_PIN_FUNCTION(gp_pwm10), + TEGRA_PIN_FUNCTION(uarte_cts), + TEGRA_PIN_FUNCTION(uarte_rts), + TEGRA_PIN_FUNCTION(uarte_rxd), + TEGRA_PIN_FUNCTION(uarte_txd), + TEGRA_PIN_FUNCTION(i2c5_dat), + TEGRA_PIN_FUNCTION(i2c5_clk), + TEGRA_PIN_FUNCTION(i2s6_sdata_in), + TEGRA_PIN_FUNCTION(i2s6_sdata_out), + TEGRA_PIN_FUNCTION(i2s6_lrck), + TEGRA_PIN_FUNCTION(i2s6_sclk), + TEGRA_PIN_FUNCTION(i2s4_sdata_out), + TEGRA_PIN_FUNCTION(i2s4_sclk), + TEGRA_PIN_FUNCTION(i2s4_sdata_in), + TEGRA_PIN_FUNCTION(i2s4_lrck), + TEGRA_PIN_FUNCTION(spi5_cs0), + TEGRA_PIN_FUNCTION(spi5_din), + TEGRA_PIN_FUNCTION(spi5_dout), + TEGRA_PIN_FUNCTION(spi5_sck), + TEGRA_PIN_FUNCTION(aud_mclk), + TEGRA_PIN_FUNCTION(i2s1_sclk), + TEGRA_PIN_FUNCTION(i2s1_sdata_in), + TEGRA_PIN_FUNCTION(i2s1_sdata_out), + TEGRA_PIN_FUNCTION(i2s1_lrck), + TEGRA_PIN_FUNCTION(i2c11_clk), + TEGRA_PIN_FUNCTION(i2c11_dat), + TEGRA_PIN_FUNCTION(xhalt_trig), + TEGRA_PIN_FUNCTION(gp_pwm1), + TEGRA_PIN_FUNCTION(gp_pwm6), + TEGRA_PIN_FUNCTION(gp_pwm7), + TEGRA_PIN_FUNCTION(gp_pwm8), + TEGRA_PIN_FUNCTION(ufs0), + TEGRA_PIN_FUNCTION(pe1_clkreq_l), + TEGRA_PIN_FUNCTION(pe1_rst_l), + TEGRA_PIN_FUNCTION(pe2_rst_l), + TEGRA_PIN_FUNCTION(pe2_clkreq_l), + TEGRA_PIN_FUNCTION(pe3_clkreq_l), + TEGRA_PIN_FUNCTION(pe3_rst_l), + TEGRA_PIN_FUNCTION(sgmii0_sma_mdio), + TEGRA_PIN_FUNCTION(sgmii0_sma_mdc), + TEGRA_PIN_FUNCTION(usb_vbus_en0), + TEGRA_PIN_FUNCTION(usb_vbus_en1), + TEGRA_PIN_FUNCTION(eth1_mdio), + TEGRA_PIN_FUNCTION(pe4_clkreq_l), + TEGRA_PIN_FUNCTION(pe4_rst_l), + TEGRA_PIN_FUNCTION(pe5_clkreq_l), + TEGRA_PIN_FUNCTION(pe5_rst_l), + TEGRA_PIN_FUNCTION(eth0_mdio), + TEGRA_PIN_FUNCTION(eth0_mdc), + TEGRA_PIN_FUNCTION(eth1_mdc), + TEGRA_PIN_FUNCTION(eth2_mdio), + TEGRA_PIN_FUNCTION(eth2_mdc), + TEGRA_PIN_FUNCTION(eth3_mdio), + TEGRA_PIN_FUNCTION(eth3_mdc), + TEGRA_PIN_FUNCTION(qspi0_cs_n), + TEGRA_PIN_FUNCTION(qspi0_io0), + TEGRA_PIN_FUNCTION(qspi0_io1), + TEGRA_PIN_FUNCTION(qspi0_io2), + TEGRA_PIN_FUNCTION(qspi0_io3), + TEGRA_PIN_FUNCTION(qspi0_sck), + TEGRA_PIN_FUNCTION(sdmmc1_clk), + TEGRA_PIN_FUNCTION(sdmmc1_cmd), + TEGRA_PIN_FUNCTION(sdmmc1_comp), + TEGRA_PIN_FUNCTION(sdmmc1_dat3), + TEGRA_PIN_FUNCTION(sdmmc1_dat2), + TEGRA_PIN_FUNCTION(sdmmc1_dat1), + TEGRA_PIN_FUNCTION(sdmmc1_dat0), + TEGRA_PIN_FUNCTION(qspi3_sck), + TEGRA_PIN_FUNCTION(qspi3_cs0), + TEGRA_PIN_FUNCTION(qspi3_io0), + TEGRA_PIN_FUNCTION(qspi3_io1), + TEGRA_PIN_FUNCTION(dcb_vsync), + TEGRA_PIN_FUNCTION(dcb_hsync), + TEGRA_PIN_FUNCTION(dsa_lspii), + TEGRA_PIN_FUNCTION(dce_vsync), + TEGRA_PIN_FUNCTION(dce_hsync), + TEGRA_PIN_FUNCTION(dch_vsync), + TEGRA_PIN_FUNCTION(dch_hsync), + TEGRA_PIN_FUNCTION(bl_en), + TEGRA_PIN_FUNCTION(bl_pwm_dim0), + TEGRA_PIN_FUNCTION(rsvd1), + TEGRA_PIN_FUNCTION(soc_therm_oc3), + TEGRA_PIN_FUNCTION(i2s5_sclk), + TEGRA_PIN_FUNCTION(i2s5_sdata_in), + TEGRA_PIN_FUNCTION(extperiph3_clk), + TEGRA_PIN_FUNCTION(extperiph4_clk), + TEGRA_PIN_FUNCTION(i2s5_sdata_out), + TEGRA_PIN_FUNCTION(i2s5_lrck), + TEGRA_PIN_FUNCTION(sdmmc1_cd), + TEGRA_PIN_FUNCTION(i2s7_sdata_in), + TEGRA_PIN_FUNCTION(spi4_sck), + TEGRA_PIN_FUNCTION(spi4_din), + TEGRA_PIN_FUNCTION(spi4_dout), + TEGRA_PIN_FUNCTION(spi4_cs0), + TEGRA_PIN_FUNCTION(spi4_cs1), + TEGRA_PIN_FUNCTION(gp_pwm5), + TEGRA_PIN_FUNCTION(i2c14_clk), + TEGRA_PIN_FUNCTION(i2c14_dat), + TEGRA_PIN_FUNCTION(i2s8_sclk), + TEGRA_PIN_FUNCTION(i2s8_sdata_out), + TEGRA_PIN_FUNCTION(i2s8_lrck), + TEGRA_PIN_FUNCTION(i2s8_sdata_in), + TEGRA_PIN_FUNCTION(i2c16_clk), + TEGRA_PIN_FUNCTION(i2c16_dat), + TEGRA_PIN_FUNCTION(i2s3_sclk), + TEGRA_PIN_FUNCTION(i2s3_sdata_out), + TEGRA_PIN_FUNCTION(i2s3_sdata_in), + TEGRA_PIN_FUNCTION(i2s3_lrck), + TEGRA_PIN_FUNCTION(pm_trig1), + TEGRA_PIN_FUNCTION(pm_trig0), + TEGRA_PIN_FUNCTION(qspi2_sck), + TEGRA_PIN_FUNCTION(qspi2_cs0), + TEGRA_PIN_FUNCTION(qspi2_io0), + TEGRA_PIN_FUNCTION(qspi2_io1), + TEGRA_PIN_FUNCTION(dcc_vsync), + TEGRA_PIN_FUNCTION(dcc_hsync), + TEGRA_PIN_FUNCTION(rsvd2), + TEGRA_PIN_FUNCTION(dcf_vsync), + TEGRA_PIN_FUNCTION(dcf_hsync), + TEGRA_PIN_FUNCTION(soundwire1_clk), + TEGRA_PIN_FUNCTION(soundwire1_dat0), + TEGRA_PIN_FUNCTION(soundwire1_dat1), + TEGRA_PIN_FUNCTION(soundwire1_dat2), + TEGRA_PIN_FUNCTION(dmic2_clk), + TEGRA_PIN_FUNCTION(dmic2_dat), + TEGRA_PIN_FUNCTION(nv_therm_fan_tach1), + TEGRA_PIN_FUNCTION(i2c15_clk), + TEGRA_PIN_FUNCTION(i2c15_dat), + TEGRA_PIN_FUNCTION(i2s7_lrck), + TEGRA_PIN_FUNCTION(ccla_la_trigger_mux), + TEGRA_PIN_FUNCTION(i2s7_sclk), + TEGRA_PIN_FUNCTION(i2s7_sdata_out), + TEGRA_PIN_FUNCTION(dmic1_dat), + TEGRA_PIN_FUNCTION(dmic1_clk), + TEGRA_PIN_FUNCTION(dcd_vsync), + TEGRA_PIN_FUNCTION(dcd_hsync), + TEGRA_PIN_FUNCTION(rsvd3), + TEGRA_PIN_FUNCTION(dcg_vsync), + TEGRA_PIN_FUNCTION(dcg_hsync), + TEGRA_PIN_FUNCTION(dspk1_clk), + TEGRA_PIN_FUNCTION(dspk1_dat), + TEGRA_PIN_FUNCTION(soc_therm_oc2), + TEGRA_PIN_FUNCTION(istctrl_ist_done_n), + TEGRA_PIN_FUNCTION(soc_therm_oc1), + TEGRA_PIN_FUNCTION(tsc_edge_out0c), + TEGRA_PIN_FUNCTION(tsc_edge_out0d), + TEGRA_PIN_FUNCTION(tsc_edge_out0a), + TEGRA_PIN_FUNCTION(tsc_edge_out0b), + TEGRA_PIN_FUNCTION(touch_clk), + TEGRA_PIN_FUNCTION(hdmi_cec), + TEGRA_PIN_FUNCTION(i2c2_clk), + TEGRA_PIN_FUNCTION(i2c2_dat), + TEGRA_PIN_FUNCTION(i2c3_clk), + TEGRA_PIN_FUNCTION(i2c3_dat), + TEGRA_PIN_FUNCTION(gp_pwm4), + TEGRA_PIN_FUNCTION(uarta_txd), + TEGRA_PIN_FUNCTION(uarta_rxd), + TEGRA_PIN_FUNCTION(spi2_sck), + TEGRA_PIN_FUNCTION(spi2_din), + TEGRA_PIN_FUNCTION(spi2_dout), + TEGRA_PIN_FUNCTION(spi2_cs0), + TEGRA_PIN_FUNCTION(tsc_sync1), + TEGRA_PIN_FUNCTION(tsc_edge_out3), + TEGRA_PIN_FUNCTION(tsc_edge_out0), + TEGRA_PIN_FUNCTION(tsc_edge_out1), + TEGRA_PIN_FUNCTION(tsc_sync0), + TEGRA_PIN_FUNCTION(soundwire0_clk), + TEGRA_PIN_FUNCTION(soundwire0_dat0), + TEGRA_PIN_FUNCTION(l0l1_rst_out_n), + TEGRA_PIN_FUNCTION(l2_rst_out_n), + TEGRA_PIN_FUNCTION(uartl_txd), + TEGRA_PIN_FUNCTION(uartl_rxd), + TEGRA_PIN_FUNCTION(i2s9_sclk), + TEGRA_PIN_FUNCTION(i2s9_sdata_out), + TEGRA_PIN_FUNCTION(i2s9_sdata_in), + TEGRA_PIN_FUNCTION(i2s9_lrck), + TEGRA_PIN_FUNCTION(dmic5_dat), + TEGRA_PIN_FUNCTION(dmic5_clk), + TEGRA_PIN_FUNCTION(tsc_edge_out2), +}; + +#define PINGROUP_REG_Y(r) ((r)) +#define PINGROUP_REG_N(r) -1 + +#define DRV_PINGROUP_Y(r) ((r)) + +#define DRV_PINGROUP_ENTRY_N \ + .drv_reg = -1, \ + .drv_bank = -1, \ + .drvdn_bit = -1, \ + .drvup_bit = -1, \ + .slwr_bit = -1, \ + .slwf_bit = -1 + +#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \ + drvup_w, slwr_b, slwr_w, slwf_b, \ + slwf_w, bank) \ + .drv_reg = DRV_PINGROUP_Y(r), \ + .drv_bank = bank, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w + +#define PIN_PINGROUP_ENTRY_N \ + .mux_reg = -1, \ + .pupd_reg = -1, \ + .tri_reg = -1, \ + .einput_bit = -1, \ + .e_io_hv_bit = -1, \ + .odrain_bit = -1, \ + .lock_bit = -1, \ + .parked_bit = -1, \ + .lpmd_bit = -1, \ + .drvtype_bit = -1, \ + .lpdr_bit = -1, \ + .pbias_buf_bit = -1, \ + .preemp_bit = -1, \ + .rfu_in_bit = -1 + +#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \ + e_lpdr, e_pbias_buf, gpio_sfio_sel, \ + schmitt_b) \ + .mux_reg = PINGROUP_REG_Y(r), \ + .lpmd_bit = -1, \ + .lock_bit = -1, \ + .hsm_bit = -1, \ + .mux_bank = bank, \ + .mux_bit = 0, \ + .pupd_reg = PINGROUP_REG_##pupd(r), \ + .pupd_bank = bank, \ + .pupd_bit = 2, \ + .tri_reg = PINGROUP_REG_Y(r), \ + .tri_bank = bank, \ + .tri_bit = 4, \ + .einput_bit = e_input, \ + .sfsel_bit = gpio_sfio_sel, \ + .schmitt_bit = schmitt_b, \ + .drvtype_bit = 13, \ + .lpdr_bit = e_lpdr, + +#define drive_eth1_mdio_pe0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l4_clkreq_n_pd0 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l4_rst_n_pd1 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l5_clkreq_n_pd2 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l5_rst_n_pd3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_eth0_mdio_pd4 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_eth0_mdc_pd5 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_eth1_mdc_pe1 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_eth2_mdio_pe2 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_eth2_mdc_pe3 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_eth3_mdio_pd6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_eth3_mdc_pd7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l1_clkreq_n_pb0 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l1_rst_n_pb1 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_wake_n_pc2 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l2_rst_n_pb3 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l2_clkreq_n_pb2 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l3_clkreq_n_pb4 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pex_l3_rst_n_pb5 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_sgmii0_sma_mdio_pc0 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_sgmii0_sma_mdc_pc1 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio113_pb6 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio114_pb7 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwm1_pa0 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwm6_pa1 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwm7_pa2 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwm8_pa3 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_ufs0_ref_clk_pa4 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_ufs0_rst_n_pa5 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0) + +#define drive_cpu_pwr_req_ph0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gpu_pwr_req_ph1 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart10_cts_n_ph5 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart10_rts_n_ph4 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart10_rx_ph3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart10_tx_ph2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi3_cs0_pj1 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi3_cs3_pj2 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi3_miso_ph7 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi3_mosi_pj0 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi3_sck_ph6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart5_cts_n_pj6 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart5_rts_n_pj5 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart5_rx_pj4 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart5_tx_pj3 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi1_cs0_pk2 DRV_PINGROUP_ENTRY_Y(0x7c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi1_cs1_pk3 DRV_PINGROUP_ENTRY_Y(0x84, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi1_miso_pk0 DRV_PINGROUP_ENTRY_Y(0x8c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi1_mosi_pk1 DRV_PINGROUP_ENTRY_Y(0x94, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi1_sck_pj7 DRV_PINGROUP_ENTRY_Y(0x9c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_extperiph2_clk_pk5 DRV_PINGROUP_ENTRY_Y(0xa4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_extperiph1_clk_pk4 DRV_PINGROUP_ENTRY_Y(0xac, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen12_i2c_scl_pk6 DRV_PINGROUP_ENTRY_Y(0xb4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen12_i2c_sda_pk7 DRV_PINGROUP_ENTRY_Y(0xbc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio124_pl0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio125_pl1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_fan_tach0_pl2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio127_pl3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio128_pl4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio129_pl5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio130_pl6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio131_pl7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gp_pwm9_pm0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio133_pm1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart9_cts_n_pm5 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart9_rts_n_pm4 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart9_rx_pm3 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart9_tx_pm2 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N +#define drive_sdmmc1_clk_px0 DRV_PINGROUP_ENTRY_Y(0x2004, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_cmd_px1 DRV_PINGROUP_ENTRY_Y(0x200c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat3_px5 DRV_PINGROUP_ENTRY_Y(0x201c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat2_px4 DRV_PINGROUP_ENTRY_Y(0x2024, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat1_px3 DRV_PINGROUP_ENTRY_Y(0x202c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_sdmmc1_dat0_px2 DRV_PINGROUP_ENTRY_Y(0x2034, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_qspi0_cs_n_pt1 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_qspi0_io0_pt2 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_qspi0_io1_pt3 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_qspi0_io2_pt4 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_qspi0_io3_pt5 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_qspi0_sck_pt0 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio192_pt6 DRV_PINGROUP_ENTRY_Y(0x3034, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio138_pp0 DRV_PINGROUP_ENTRY_Y(0x5004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio139_pp1 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap6_din_pp4 DRV_PINGROUP_ENTRY_Y(0x5014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap6_dout_pp3 DRV_PINGROUP_ENTRY_Y(0x501c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap6_fs_pp5 DRV_PINGROUP_ENTRY_Y(0x5024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap6_sclk_pp2 DRV_PINGROUP_ENTRY_Y(0x502c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap4_dout_pp7 DRV_PINGROUP_ENTRY_Y(0x5034, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap4_sclk_pp6 DRV_PINGROUP_ENTRY_Y(0x503c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap4_din_pq0 DRV_PINGROUP_ENTRY_Y(0x5044, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap4_fs_pq1 DRV_PINGROUP_ENTRY_Y(0x504c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi5_cs0_pq5 DRV_PINGROUP_ENTRY_Y(0x5054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi5_miso_pq3 DRV_PINGROUP_ENTRY_Y(0x505c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi5_mosi_pq4 DRV_PINGROUP_ENTRY_Y(0x5064, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi5_sck_pq2 DRV_PINGROUP_ENTRY_Y(0x506c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio152_pq6 DRV_PINGROUP_ENTRY_Y(0x5074, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio153_pq7 DRV_PINGROUP_ENTRY_Y(0x507c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio155_pr1 DRV_PINGROUP_ENTRY_Y(0x5084, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_aud_mclk_pr0 DRV_PINGROUP_ENTRY_Y(0x508c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap1_sclk_pr2 DRV_PINGROUP_ENTRY_Y(0x5094, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap1_in_pr4 DRV_PINGROUP_ENTRY_Y(0x509c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap1_out_pr3 DRV_PINGROUP_ENTRY_Y(0x50a4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap1_fs_pr5 DRV_PINGROUP_ENTRY_Y(0x50ac, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen11_i2c_scl_pr6 DRV_PINGROUP_ENTRY_Y(0x50b4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen11_i2c_sda_pr7 DRV_PINGROUP_ENTRY_Y(0x50bc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio350_ps0 DRV_PINGROUP_ENTRY_Y(0x50c4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio351_ps1 DRV_PINGROUP_ENTRY_Y(0x50cc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen0_i2c_scl_pw4 DRV_PINGROUP_ENTRY_Y(0x6004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen0_i2c_sda_pw5 DRV_PINGROUP_ENTRY_Y(0x600c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen1_i2c_scl_pw2 DRV_PINGROUP_ENTRY_Y(0x6014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen1_i2c_sda_pw3 DRV_PINGROUP_ENTRY_Y(0x601c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap2_fs_pw1 DRV_PINGROUP_ENTRY_Y(0x6044, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap2_clk_pv6 DRV_PINGROUP_ENTRY_Y(0x604c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap2_din_pw0 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dap2_dout_pv7 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwm10_pv1 DRV_PINGROUP_ENTRY_Y(0x6064, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio170_pu0 DRV_PINGROUP_ENTRY_Y(0x606c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio171_pu1 DRV_PINGROUP_ENTRY_Y(0x6074, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio172_pu2 DRV_PINGROUP_ENTRY_Y(0x607c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio173_pu3 DRV_PINGROUP_ENTRY_Y(0x6084, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio174_pu4 DRV_PINGROUP_ENTRY_Y(0x608c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio175_pu5 DRV_PINGROUP_ENTRY_Y(0x6094, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio176_pu6 DRV_PINGROUP_ENTRY_Y(0x609c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio177_pu7 DRV_PINGROUP_ENTRY_Y(0x60a4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio178_pv0 DRV_PINGROUP_ENTRY_Y(0x60ac, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart4_cts_n_pv5 DRV_PINGROUP_ENTRY_Y(0x60b4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart4_rts_n_pv4 DRV_PINGROUP_ENTRY_Y(0x60bc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart4_rx_pv3 DRV_PINGROUP_ENTRY_Y(0x60c4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart4_tx_pv2 DRV_PINGROUP_ENTRY_Y(0x60cc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_sda_pw7 DRV_PINGROUP_ENTRY_Y(0x60d4, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_scl_pw6 DRV_PINGROUP_ENTRY_Y(0x60dc, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio250_pf0 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio251_pf1 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio252_pf2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dp_aux_ch0_hpd_pf3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dp_aux_ch1_hpd_pf4 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dp_aux_ch2_hpd_pf5 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_dp_aux_ch3_hpd_pf6 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwm2_pf7 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_pwm3_pg0 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen7_i2c_scl_pg1 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen7_i2c_sda_pg2 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen9_i2c_scl_pg3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen9_i2c_sda_pg4 DRV_PINGROUP_ENTRY_Y(0x7064, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio270_py0 DRV_PINGROUP_ENTRY_Y(0xa004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio271_py1 DRV_PINGROUP_ENTRY_Y(0xa00c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio272_py2 DRV_PINGROUP_ENTRY_Y(0xa014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio273_py3 DRV_PINGROUP_ENTRY_Y(0xa01c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio274_py4 DRV_PINGROUP_ENTRY_Y(0xa024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio275_py5 DRV_PINGROUP_ENTRY_Y(0xa02c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio276_py6 DRV_PINGROUP_ENTRY_Y(0xa034, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio277_py7 DRV_PINGROUP_ENTRY_Y(0xa03c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio278_pz0 DRV_PINGROUP_ENTRY_Y(0xa044, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio279_pz1 DRV_PINGROUP_ENTRY_Y(0xa04c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio282_pz4 DRV_PINGROUP_ENTRY_Y(0xa054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio283_pz5 DRV_PINGROUP_ENTRY_Y(0xa05c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio284_pz6 DRV_PINGROUP_ENTRY_Y(0xa064, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio285_pz7 DRV_PINGROUP_ENTRY_Y(0xa06c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio286_pal0 DRV_PINGROUP_ENTRY_Y(0xa074, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio287_pal1 DRV_PINGROUP_ENTRY_Y(0xa07c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio288_pal2 DRV_PINGROUP_ENTRY_Y(0xa084, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_xhalt_trig_pz2 DRV_PINGROUP_ENTRY_Y(0xa08c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio281_pz3 DRV_PINGROUP_ENTRY_Y(0xa094, 12, 4, 20, 4, -1, -1, -1, -1, 0) + +#define drive_ao_retention_n_paa2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_batt_oc_paa3 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_power_on_paa5 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_vcomp_alert_paa1 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_bootv_ctl_n_paa4 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio00_paa0 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio07_paa7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio08_pbb0 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio09_pbb1 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_hdmi_cec_paa6 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_scl_pcc0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_sda_pcc1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen3_i2c_scl_pcc2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gen3_i2c_sda_pcc3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_gp_pwm4_pcc4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart0_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_uart0_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi2_sck_pcc7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi2_miso_pdd0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi2_mosi_pdd1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_spi2_cs0_n_pdd2 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio21_pdd3 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio22_pdd4 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio23_pdd5 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio24_pdd6 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio25_pdd7 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio26_pee0 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio27_pee1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 4, 20, 4, -1, -1, -1, -1, 0) +#define drive_soc_gpio28_pee2 DRV_PINGROUP_ENTRY_N +#define drive_soc_gpio29_pee3 DRV_PINGROUP_ENTRY_N + +#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \ + gpio_sfio_sel, schmitt_b) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \ + e_input, e_lpdr, e_pbias_buf, \ + gpio_sfio_sel, schmitt_b) \ + drive_##pg_name, \ + } + +static const struct tegra_pingroup tegra264_uphy_groups[] = { + PINGROUP(eth1_mdio_pe0, ETH1_MDIO, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l4_clkreq_n_pd0, PE4_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l4_rst_n_pd1, PE4_RST_L, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l5_clkreq_n_pd2, PE5_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l5_rst_n_pd3, PE5_RST_L, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(eth0_mdio_pd4, ETH0_MDIO, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(eth0_mdc_pd5, ETH0_MDC, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(eth1_mdc_pe1, ETH1_MDC, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(eth2_mdio_pe2, ETH2_MDIO, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(eth2_mdc_pe3, ETH2_MDC, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(eth3_mdio_pd6, ETH3_MDIO, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(eth3_mdc_pd7, ETH3_MDC, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l1_clkreq_n_pb0, PE1_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l1_rst_n_pb1, PE1_RST_L, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_wake_n_pc2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l2_rst_n_pb3, PE2_RST_L, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l2_clkreq_n_pb2, PE2_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l3_clkreq_n_pb4, PE3_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pex_l3_rst_n_pb5, PE3_RST_L, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(sgmii0_sma_mdio_pc0, SGMII0_SMA_MDIO, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(sgmii0_sma_mdc_pc1, SGMII0_SMA_MDC, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio113_pb6, USB_VBUS_EN0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio114_pb7, USB_VBUS_EN1, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwm1_pa0, GP_PWM1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwm6_pa1, GP_PWM6, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwm7_pa2, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwm8_pa3, GP_PWM8, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(ufs0_ref_clk_pa4, UFS0, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(ufs0_rst_n_pa5, UFS0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11), +}; + +static const struct tegra_pingroup tegra264_main_groups[] = { + PINGROUP(cpu_pwr_req_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gpu_pwr_req_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart10_cts_n_ph5, UARTK_CTS, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart10_rts_n_ph4, UARTK_RTS, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart10_rx_ph3, UARTK_RXD, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart10_tx_ph2, UARTK_TXD, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi3_cs0_pj1, SPI3_CS0, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi3_cs3_pj2, SPI3_CS3, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi3_miso_ph7, SPI3_DIN, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi3_mosi_pj0, SPI3_DOUT, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi3_sck_ph6, SPI3_SCK, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart5_cts_n_pj6, UARTF_CTS, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart5_rts_n_pj5, UARTF_RTS, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart5_rx_pj4, UARTF_RXD, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart5_tx_pj3, UARTF_TXD, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi1_cs0_pk2, SPI1_CS0, RSVD1, RSVD2, RSVD3, 0x78, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi1_cs1_pk3, SPI1_CS1, RSVD1, RSVD2, RSVD3, 0x80, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi1_miso_pk0, SPI1_DIN, RSVD1, RSVD2, RSVD3, 0x88, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi1_mosi_pk1, SPI1_DOUT, RSVD1, RSVD2, RSVD3, 0x90, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi1_sck_pj7, SPI1_SCK, RSVD1, RSVD2, RSVD3, 0x98, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(extperiph2_clk_pk5, EXTPERIPH2_CLK, RSVD1, DMIC2_CLK, DSPK1_CLK, 0xa0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(extperiph1_clk_pk4, EXTPERIPH1_CLK, RSVD1, DMIC2_DAT, DSPK1_DAT, 0xa8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen12_i2c_scl_pk6, I2C12_CLK, RSVD1, RSVD2, RSVD3, 0xb0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen12_i2c_sda_pk7, I2C12_DAT, RSVD1, RSVD2, RSVD3, 0xb8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio124_pl0, RSVD0, SOC_THERM_OC3, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio125_pl1, RSVD0, I2S5_SCLK, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(fan_tach0_pl2, NV_THERM_FAN_TACH0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio127_pl3, RSVD0, RSVD1, NV_THERM_FAN_TACH1, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio128_pl4, RSVD0, I2S5_SDATA_IN, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio129_pl5, RSVD0, EXTPERIPH3_CLK, I2C15_CLK, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio130_pl6, RSVD0, EXTPERIPH4_CLK, I2C15_DAT, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio131_pl7, RSVD0, I2S5_SDATA_OUT, RSVD2, RSVD3, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gp_pwm9_pm0, GP_PWM9, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio133_pm1, RSVD0, I2S5_LRCK, RSVD2, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart9_cts_n_pm5, UARTJ_CTS, RSVD1, RSVD2, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart9_rts_n_pm4, UARTJ_RTS, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart9_rx_pm3, UARTJ_RXD, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart9_tx_pm2, UARTJ_TXD, RSVD1, RSVD2, RSVD3, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(sdmmc1_clk_px0, SDMMC1_CLK, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 5, 6, 13, -1, 10, -1), + PINGROUP(sdmmc1_cmd_px1, SDMMC1_CMD, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 5, 6, 13, -1, 10, -1), + PINGROUP(sdmmc1_comp, SDMMC1_COMP, RSVD1, RSVD2, RSVD3, 0x2010, 0, N, -1, -1, -1, -1, -1, -1, -1), + PINGROUP(sdmmc1_dat3_px5, SDMMC1_DAT3, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 5, 6, 13, -1, 10, -1), + PINGROUP(sdmmc1_dat2_px4, SDMMC1_DAT2, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, 5, 6, 13, -1, 10, -1), + PINGROUP(sdmmc1_dat1_px3, SDMMC1_DAT1, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, -1, 5, 6, 13, -1, 10, -1), + PINGROUP(sdmmc1_dat0_px2, SDMMC1_DAT0, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, 5, 6, 13, -1, 10, -1), + PINGROUP(qspi0_cs_n_pt1, QSPI0_CS_N, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(qspi0_io0_pt2, QSPI0_IO0, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(qspi0_io1_pt3, QSPI0_IO1, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(qspi0_io2_pt4, QSPI0_IO2, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(qspi0_io3_pt5, QSPI0_IO3, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(qspi0_sck_pt0, QSPI0_SCK, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio192_pt6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio138_pp0, RSVD0, I2C14_CLK, DMIC1_DAT, RSVD3, 0x5000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio139_pp1, RSVD0, I2C14_DAT, DMIC1_CLK, RSVD3, 0x5008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap6_din_pp4, I2S6_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap6_dout_pp3, I2S6_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap6_fs_pp5, I2S6_LRCK, RSVD1, RSVD2, RSVD3, 0x5020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap6_sclk_pp2, I2S6_SCLK, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap4_dout_pp7, I2S4_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap4_sclk_pp6, I2S4_SCLK, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap4_din_pq0, I2S4_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap4_fs_pq1, I2S4_LRCK, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi5_cs0_pq5, SPI5_CS0, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi5_miso_pq3, SPI5_DIN, RSVD1, RSVD2, RSVD3, 0x5058, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi5_mosi_pq4, SPI5_DOUT, RSVD1, RSVD2, RSVD3, 0x5060, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi5_sck_pq2, SPI5_SCK, RSVD1, RSVD2, RSVD3, 0x5068, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio152_pq6, RSVD0, I2S8_SCLK, RSVD2, RSVD3, 0x5070, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio153_pq7, RSVD0, I2S8_SDATA_OUT, RSVD2, RSVD3, 0x5078, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio155_pr1, RSVD0, I2S8_LRCK, RSVD2, RSVD3, 0x5080, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(aud_mclk_pr0, AUD_MCLK, RSVD1, RSVD2, RSVD3, 0x5088, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap1_sclk_pr2, I2S1_SCLK, RSVD1, RSVD2, RSVD3, 0x5090, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap1_in_pr4, I2S1_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5098, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap1_out_pr3, I2S1_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x50a0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap1_fs_pr5, I2S1_LRCK, RSVD1, RSVD2, RSVD3, 0x50a8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen11_i2c_scl_pr6, I2C11_CLK, RSVD1, RSVD2, RSVD3, 0x50b0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen11_i2c_sda_pr7, I2C11_DAT, RSVD1, RSVD2, RSVD3, 0x50b8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio350_ps0, RSVD0, I2S8_SDATA_IN, RSVD2, RSVD3, 0x50c0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio351_ps1, RSVD0, RSVD1, RSVD2, RSVD3, 0x50c8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen0_i2c_scl_pw4, I2C0_CLK, RSVD1, RSVD2, RSVD3, 0x6000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen0_i2c_sda_pw5, I2C0_DAT, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen1_i2c_scl_pw2, I2C1_CLK, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen1_i2c_sda_pw3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap2_fs_pw1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap2_clk_pv6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap2_din_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dap2_dout_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwm10_pv1, GP_PWM10, SDMMC1_CD, I2S7_LRCK, RSVD3, 0x6060, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio170_pu0, RSVD0, I2S7_SDATA_IN, CCLA_LA_TRIGGER_MUX, RSVD3, 0x6068, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio171_pu1, RSVD0, SPI4_SCK, RSVD2, RSVD3, 0x6070, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio172_pu2, RSVD0, SPI4_DIN, RSVD2, RSVD3, 0x6078, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio173_pu3, RSVD0, SPI4_DOUT, RSVD2, RSVD3, 0x6080, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio174_pu4, RSVD0, SPI4_CS0, RSVD2, RSVD3, 0x6088, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio175_pu5, RSVD0, SPI4_CS1, RSVD2, RSVD3, 0x6090, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio176_pu6, RSVD0, RSVD1, I2S7_SCLK, RSVD3, 0x6098, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio177_pu7, RSVD0, GP_PWM5, RSVD2, RSVD3, 0x60a0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio178_pv0, RSVD0, RSVD1, I2S7_SDATA_OUT, RSVD3, 0x60a8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart4_cts_n_pv5, UARTE_CTS, RSVD1, RSVD2, RSVD3, 0x60b0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart4_rts_n_pv4, UARTE_RTS, RSVD1, RSVD2, RSVD3, 0x60b8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart4_rx_pv3, UARTE_RXD, RSVD1, RSVD2, RSVD3, 0x60c0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart4_tx_pv2, UARTE_TXD, RSVD1, RSVD2, RSVD3, 0x60c8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwr_i2c_sda_pw7, I2C5_DAT, RSVD1, RSVD2, RSVD3, 0x60d0, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwr_i2c_scl_pw6, I2C5_CLK, RSVD1, RSVD2, RSVD3, 0x60d8, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio250_pf0, DCA_VSYNC, DCB_VSYNC, DCC_VSYNC, DCD_VSYNC, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio251_pf1, DCA_HSYNC, DCB_HSYNC, DCC_HSYNC, DCD_HSYNC, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio252_pf2, RSVD0, DSA_LSPII, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dp_aux_ch0_hpd_pf3, DP_AUX_CH0_HPD, DCE_VSYNC, DCF_VSYNC, DCG_VSYNC, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dp_aux_ch1_hpd_pf4, DP_AUX_CH1_HPD, DCE_HSYNC, DCF_HSYNC, DCG_HSYNC, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dp_aux_ch2_hpd_pf5, DP_AUX_CH2_HPD, DCH_VSYNC, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(dp_aux_ch3_hpd_pf6, DP_AUX_CH3_HPD, DCH_HSYNC, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwm2_pf7, GP_PWM2, BL_EN, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(pwm3_pg0, GP_PWM3, BL_PWM_DIM0, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen7_i2c_scl_pg1, I2C7_CLK, RSVD1, SOUNDWIRE1_CLK, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen7_i2c_sda_pg2, I2C7_DAT, RSVD1, SOUNDWIRE1_DAT0, RSVD3, 0x7050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen9_i2c_scl_pg3, I2C9_CLK, RSVD1, SOUNDWIRE1_DAT1, RSVD3, 0x7058, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen9_i2c_sda_pg4, I2C9_DAT, RSVD1, SOUNDWIRE1_DAT2, RSVD3, 0x7060, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio270_py0, RSVD0, I2C16_CLK, RSVD2, RSVD3, 0xa000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio271_py1, RSVD0, I2C16_DAT, RSVD2, RSVD3, 0xa008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio272_py2, RSVD0, I2S3_SCLK, RSVD2, RSVD3, 0xa010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio273_py3, RSVD0, I2S3_SDATA_OUT, RSVD2, RSVD3, 0xa018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio274_py4, RSVD0, I2S3_SDATA_IN, RSVD2, RSVD3, 0xa020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio275_py5, RSVD0, I2S3_LRCK, RSVD2, RSVD3, 0xa028, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio276_py6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa030, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio277_py7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa038, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio278_pz0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa040, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio279_pz1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa048, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio282_pz4, RSVD0, PM_TRIG1, RSVD2, RSVD3, 0xa050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio283_pz5, RSVD0, RSVD1, RSVD2, RSVD3, 0xa058, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio284_pz6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa060, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio285_pz7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa068, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio286_pal0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa070, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio287_pal1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa078, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio288_pal2, RSVD0, RSVD1, RSVD2, RSVD3, 0xa080, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(xhalt_trig_pz2, XHALT_TRIG, RSVD1, RSVD2, RSVD3, 0xa088, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio281_pz3, RSVD0, PM_TRIG0, RSVD2, RSVD3, 0xa090, 0, Y, 5, 7, 6, 8, -1, 10, 11), +}; + +static const struct tegra_pingroup tegra264_aon_groups[] = { + PINGROUP(ao_retention_n_paa2, RSVD0, RSVD1, RSVD2, ISTCTRL_IST_DONE_N, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(batt_oc_paa3, SOC_THERM_OC2, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(power_on_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(vcomp_alert_paa1, SOC_THERM_OC1, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(bootv_ctl_n_paa4, RSVD0, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio00_paa0, RSVD0, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio07_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio08_pbb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio09_pbb1, RSVD0, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(hdmi_cec_paa6, HDMI_CEC, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen2_i2c_scl_pcc0, I2C2_CLK, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen2_i2c_sda_pcc1, I2C2_DAT, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen3_i2c_scl_pcc2, I2C3_CLK, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gen3_i2c_sda_pcc3, I2C3_DAT, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(gp_pwm4_pcc4, GP_PWM4, TOUCH_CLK, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart0_tx_pcc5, UARTA_TXD, RSVD1, UARTL_TXD, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(uart0_rx_pcc6, UARTA_RXD, RSVD1, UARTL_RXD, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi2_sck_pcc7, SPI2_SCK, RSVD1, I2S9_SCLK, SOUNDWIRE0_CLK, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi2_miso_pdd0, SPI2_DIN, RSVD1, I2S9_SDATA_OUT, SOUNDWIRE0_DAT0, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi2_mosi_pdd1, SPI2_DOUT, RSVD1, I2S9_SDATA_IN, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(spi2_cs0_n_pdd2, SPI2_CS0, RSVD1, I2S9_LRCK, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio21_pdd3, RSVD0, TSC_SYNC1, DMIC5_DAT, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio22_pdd4, RSVD0, RSVD1, DMIC5_CLK, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio23_pdd5, RSVD0, RSVD1, TSC_EDGE_OUT2, TSC_EDGE_OUT0C, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio24_pdd6, RSVD0, TSC_EDGE_OUT3, RSVD2, TSC_EDGE_OUT0D, 0x1070, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio25_pdd7, RSVD0, TSC_EDGE_OUT0, RSVD2, TSC_EDGE_OUT0A, 0x1078, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio26_pee0, RSVD0, TSC_EDGE_OUT1, RSVD2, TSC_EDGE_OUT0B, 0x1080, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio27_pee1, RSVD0, TSC_SYNC0, RSVD2, RSVD3, 0x1088, 0, Y, 5, 7, 6, 8, -1, 10, 11), + PINGROUP(soc_gpio28_pee2, L0L1_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1090, 0, N, -1, -1, -1, -1, -1, 10, -1), + PINGROUP(soc_gpio29_pee3, L2_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1098, 0, N, -1, -1, -1, -1, -1, 10, -1), +}; + +static const struct tegra_pinctrl_soc_data tegra264_uphy_pinctrl = { + .pins = tegra264_uphy_pins, + .npins = ARRAY_SIZE(tegra264_uphy_pins), + .functions = tegra264_functions, + .nfunctions = ARRAY_SIZE(tegra264_functions), + .groups = tegra264_uphy_groups, + .ngroups = ARRAY_SIZE(tegra264_uphy_groups), + .hsm_in_mux = false, + .schmitt_in_mux = true, + .drvtype_in_mux = true, + .sfsel_in_mux = true, +}; + +static const struct tegra_pinctrl_soc_data tegra264_main_pinctrl = { + .pins = tegra264_main_pins, + .npins = ARRAY_SIZE(tegra264_main_pins), + .functions = tegra264_functions, + .nfunctions = ARRAY_SIZE(tegra264_functions), + .groups = tegra264_main_groups, + .ngroups = ARRAY_SIZE(tegra264_main_groups), + .hsm_in_mux = false, + .schmitt_in_mux = true, + .drvtype_in_mux = true, + .sfsel_in_mux = true, +}; + +static const struct tegra_pinctrl_soc_data tegra264_aon_pinctrl = { + .pins = tegra264_aon_pins, + .npins = ARRAY_SIZE(tegra264_aon_pins), + .functions = tegra264_functions, + .nfunctions = ARRAY_SIZE(tegra264_functions), + .groups = tegra264_aon_groups, + .ngroups = ARRAY_SIZE(tegra264_aon_groups), + .hsm_in_mux = false, + .schmitt_in_mux = true, + .drvtype_in_mux = true, + .sfsel_in_mux = true, +}; + +static int tegra264_pinctrl_probe(struct platform_device *pdev) +{ + const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev); + + return tegra_pinctrl_probe(pdev, soc); +} + +static const struct of_device_id tegra264_pinctrl_of_match[] = { + { .compatible = "nvidia,tegra264-pinmux-uphy", .data = &tegra264_uphy_pinctrl}, + { .compatible = "nvidia,tegra264-pinmux-main", .data = &tegra264_main_pinctrl}, + { .compatible = "nvidia,tegra264-pinmux-aon", .data = &tegra264_aon_pinctrl}, + { } +}; +MODULE_DEVICE_TABLE(of, tegra264_pinctrl_of_match); + +static struct platform_driver tegra264_pinctrl_driver = { + .driver = { + .name = "tegra264-pinctrl", + .of_match_table = tegra264_pinctrl_of_match, + }, + .probe = tegra264_pinctrl_probe, +}; + +static int __init tegra264_pinctrl_init(void) +{ + return platform_driver_register(&tegra264_pinctrl_driver); +} +module_init(tegra264_pinctrl_init); + +static void __exit tegra264_pinctrl_exit(void) +{ + platform_driver_unregister(&tegra264_pinctrl_driver); +} +module_exit(tegra264_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("NVIDIA Corporation"); +MODULE_DESCRIPTION("NVIDIA Tegra264 pinctrl driver"); diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig new file mode 100644 index 000000000000..80ac997f6c51 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_ULTRARISC + tristate + depends on OF + depends on ARCH_ULTRARISC || COMPILE_TEST + select GENERIC_PINCTRL + select PINMUX + +config PINCTRL_ULTRARISC_DP1000 + tristate "UltraRISC DP1000 SoC Pinctrl driver" + select PINCTRL_ULTRARISC + depends on OF && HAS_IOMEM + depends on ARCH_ULTRARISC || COMPILE_TEST + default ARCH_ULTRARISC + help + Say Y to select the pinctrl driver for UltraRISC DP1000 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-dp1000. diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile new file mode 100644 index 000000000000..5d49ce1c0af9 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o +obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-dp1000.o diff --git a/drivers/pinctrl/ultrarisc/pinctrl-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-dp1000.c new file mode 100644 index 000000000000..f9c85c8c4433 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/pinctrl-dp1000.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + * + * Author: Jia Wang <wangjia@ultrarisc.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-ultrarisc.h" + +/* Port indices. */ +#define UR_DP1000_PORT_A_IDX 0 +#define UR_DP1000_PORT_B_IDX 1 +#define UR_DP1000_PORT_C_IDX 2 +#define UR_DP1000_PORT_D_IDX 3 +#define UR_DP1000_PORT_LPC_IDX 4 + +/* Port mux register offsets. */ +#define UR_DP1000_PORTA_FUNC_OFFSET 0x2c0 +#define UR_DP1000_PORTB_FUNC_OFFSET 0x2c4 +#define UR_DP1000_PORTC_FUNC_OFFSET 0x2c8 +#define UR_DP1000_PORTD_FUNC_OFFSET 0x2cc +#define UR_DP1000_PORTLPC_FUNC_OFFSET 0x2d0 + +/* Port pinconf register offsets. */ +#define UR_DP1000_PORTA_CONF_OFFSET 0x310 +#define UR_DP1000_PORTB_CONF_OFFSET 0x318 +#define UR_DP1000_PORTC_CONF_OFFSET 0x31c +#define UR_DP1000_PORTD_CONF_OFFSET 0x320 +#define UR_DP1000_PORTLPC_CONF_OFFSET 0x324 + +/* Pin ranges for function descriptors. */ +#define UR_DP1000_PINS_ABCD GENMASK_ULL(39, 0) +#define UR_DP1000_PINS_LPC GENMASK_ULL(52, 40) + +/* Static table entry helpers. */ +#define UR_DP1000_PORT(_base, _npins, _func, _conf, _modes, _gpio) \ + { .pin_base = (_base), .npins = (_npins), .func_offset = (_func), \ + .conf_offset = (_conf), .supported_modes = (_modes), \ + .supports_gpio = (_gpio) } + +#define UR_DP1000_PIN(_nr, _name, _port) \ + { .number = (_nr), .name = (_name), .drv_data = (void *)&ur_dp1000_ports[_port] } + +static const struct ur_func_route ur_dp1000_routes[] = { + { "gpio", UR_FUNC_DEFAULT, UR_DP1000_PINS_ABCD }, + { "i2c", UR_FUNC_0, GENMASK_ULL(13, 12) }, + { "i2c", UR_FUNC_0, GENMASK_ULL(23, 22) }, + { "i2c", UR_FUNC_0, GENMASK_ULL(25, 24) }, + { "i2c", UR_FUNC_0, GENMASK_ULL(27, 26) }, + { "pwm", UR_FUNC_0, GENMASK_ULL(19, 16) }, + { "spi", UR_FUNC_1, GENMASK_ULL(39, 32) }, + { "spi", UR_FUNC_0, GENMASK_ULL(6, 0) }, + { "uart", UR_FUNC_1, GENMASK_ULL(9, 8) }, + { "uart", UR_FUNC_0, GENMASK_ULL(21, 20) }, + { "uart", UR_FUNC_0, GENMASK_ULL(29, 28) }, + { "uart", UR_FUNC_0, GENMASK_ULL(31, 30) }, + { "lpc", UR_FUNC_DEFAULT, UR_DP1000_PINS_LPC }, + { "espi", UR_FUNC_0, UR_DP1000_PINS_LPC }, +}; + +static const struct ur_port_desc ur_dp1000_ports[] = { + UR_DP1000_PORT(0, 16, UR_DP1000_PORTA_FUNC_OFFSET, + UR_DP1000_PORTA_CONF_OFFSET, + UR_FUNC_0 | UR_FUNC_1, true), + UR_DP1000_PORT(16, 8, UR_DP1000_PORTB_FUNC_OFFSET, + UR_DP1000_PORTB_CONF_OFFSET, + UR_FUNC_0 | UR_FUNC_1, true), + UR_DP1000_PORT(24, 8, UR_DP1000_PORTC_FUNC_OFFSET, + UR_DP1000_PORTC_CONF_OFFSET, + UR_FUNC_0 | UR_FUNC_1, true), + UR_DP1000_PORT(32, 8, UR_DP1000_PORTD_FUNC_OFFSET, + UR_DP1000_PORTD_CONF_OFFSET, + UR_FUNC_0 | UR_FUNC_1, true), + UR_DP1000_PORT(40, 13, UR_DP1000_PORTLPC_FUNC_OFFSET, + UR_DP1000_PORTLPC_CONF_OFFSET, + UR_FUNC_0, false), +}; + +static const struct pinctrl_pin_desc ur_dp1000_pins[] = { + UR_DP1000_PIN(0, "PA0", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(1, "PA1", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(2, "PA2", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(3, "PA3", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(4, "PA4", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(5, "PA5", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(6, "PA6", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(7, "PA7", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(8, "PA8", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(9, "PA9", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(10, "PA10", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(11, "PA11", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(12, "PA12", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(13, "PA13", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(14, "PA14", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(15, "PA15", UR_DP1000_PORT_A_IDX), + UR_DP1000_PIN(16, "PB0", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(17, "PB1", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(18, "PB2", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(19, "PB3", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(20, "PB4", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(21, "PB5", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(22, "PB6", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(23, "PB7", UR_DP1000_PORT_B_IDX), + UR_DP1000_PIN(24, "PC0", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(25, "PC1", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(26, "PC2", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(27, "PC3", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(28, "PC4", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(29, "PC5", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(30, "PC6", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(31, "PC7", UR_DP1000_PORT_C_IDX), + UR_DP1000_PIN(32, "PD0", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(33, "PD1", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(34, "PD2", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(35, "PD3", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(36, "PD4", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(37, "PD5", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(38, "PD6", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(39, "PD7", UR_DP1000_PORT_D_IDX), + UR_DP1000_PIN(40, "LPC0", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(41, "LPC1", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(42, "LPC2", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(43, "LPC3", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(44, "LPC4", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(45, "LPC5", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(46, "LPC6", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(47, "LPC7", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(48, "LPC8", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(49, "LPC9", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(50, "LPC10", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(51, "LPC11", UR_DP1000_PORT_LPC_IDX), + UR_DP1000_PIN(52, "LPC12", UR_DP1000_PORT_LPC_IDX), +}; + +static const struct ur_pinctrl_data ur_dp1000_pinctrl_data = { + .pins = ur_dp1000_pins, + .npins = ARRAY_SIZE(ur_dp1000_pins), + .routes = ur_dp1000_routes, + .num_routes = ARRAY_SIZE(ur_dp1000_routes), +}; + +static const struct of_device_id ur_pinctrl_of_match[] = { + { .compatible = "ultrarisc,dp1000-pinctrl" }, + { } +}; +MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); + +static int ur_dp1000_pinctrl_probe(struct platform_device *pdev) +{ + return ur_pinctrl_probe(pdev, &ur_dp1000_pinctrl_data); +} + +static struct platform_driver ur_pinctrl_driver = { + .driver = { + .name = "ultrarisc-pinctrl-dp1000", + .of_match_table = ur_pinctrl_of_match, + }, + .probe = ur_dp1000_pinctrl_probe, +}; + +module_platform_driver(ur_pinctrl_driver); + +MODULE_DESCRIPTION("UltraRISC DP1000 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c new file mode 100644 index 000000000000..8fb5b0ea5b93 --- /dev/null +++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + * + * Author: Jia Wang <wangjia@ultrarisc.com> + */ + +#include <linux/bitfield.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../devicetree.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#include "pinctrl-ultrarisc.h" + +#define UR_CONF_BIT_PER_PIN 4 +#define UR_CONF_PIN_PER_REG (32 / UR_CONF_BIT_PER_PIN) +static const u32 ur_drive_strengths[] = { 20, 27, 33, 40 }; + +static const struct ur_port_desc *ur_get_pin_port(struct pinctrl_dev *pctldev, + unsigned int pin) +{ + const struct pin_desc *desc = pin_desc_get(pctldev, pin); + + if (!desc || !desc->drv_data) + return NULL; + + return desc->drv_data; +} + +static u32 ur_get_pin_conf_offset(const struct ur_port_desc *port_desc, u32 pin) +{ + return port_desc->conf_offset + + (pin / UR_CONF_PIN_PER_REG) * sizeof(u32); +} + +static int ur_read_pin_conf(struct ur_pinctrl *pctrl, unsigned int pin, u32 *conf) +{ + const struct ur_port_desc *port_desc; + u32 pin_offset; + u32 reg_offset; + u32 shift; + u32 mask; + + port_desc = ur_get_pin_port(pctrl->pctl_dev, pin); + if (!port_desc) + return -EINVAL; + + pin_offset = pin - port_desc->pin_base; + reg_offset = ur_get_pin_conf_offset(port_desc, pin_offset); + shift = (pin_offset % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; + mask = GENMASK(UR_CONF_BIT_PER_PIN - 1, 0) << shift; + *conf = field_get(mask, readl_relaxed(pctrl->base + reg_offset)); + + return 0; +} + +static int ur_write_pin_conf(struct ur_pinctrl *pctrl, unsigned int pin, u32 conf) +{ + const struct ur_port_desc *port_desc; + void __iomem *reg; + u32 pin_offset; + u32 reg_offset; + u32 shift; + u32 mask; + u32 val; + + port_desc = ur_get_pin_port(pctrl->pctl_dev, pin); + if (!port_desc) + return -EINVAL; + + pin_offset = pin - port_desc->pin_base; + reg_offset = ur_get_pin_conf_offset(port_desc, pin_offset); + reg = pctrl->base + reg_offset; + shift = (pin_offset % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; + mask = GENMASK(UR_CONF_BIT_PER_PIN - 1, 0) << shift; + + scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { + val = readl_relaxed(reg); + val = (val & ~mask) | field_prep(mask, conf); + writel_relaxed(val, reg); + } + + return 0; +} + +static int ur_set_pin_mux(struct ur_pinctrl *pctrl, + const struct ur_port_desc *port_desc, + u32 pin_offset, u32 mode) +{ + void __iomem *reg = pctrl->base + port_desc->func_offset; + u32 val; + + if (WARN_ON(pin_offset >= UR_MAX_PINS_PER_PORT)) + return -EINVAL; + + scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { + val = readl_relaxed(reg); + val &= ~((UR_FUNC_0 | UR_FUNC_1) << pin_offset); + val |= mode << pin_offset; + writel_relaxed(val, reg); + } + + return 0; +} + +static int ur_set_pin_mux_by_num(struct ur_pinctrl *pctrl, unsigned int pin, u32 mode) +{ + const struct ur_port_desc *port_desc = ur_get_pin_port(pctrl->pctl_dev, pin); + u32 pin_offset; + + if (!port_desc) + return -EINVAL; + + if (mode != UR_FUNC_DEFAULT && !(port_desc->supported_modes & mode)) + return -EINVAL; + + pin_offset = pin - port_desc->pin_base; + + return ur_set_pin_mux(pctrl, port_desc, pin_offset, mode); +} + +static int ur_hw_to_config(unsigned long *config, u32 conf) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + u32 drive = FIELD_GET(UR_DRIVE_MASK, conf); + u32 pull = FIELD_GET(UR_PULL_MASK, conf); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + if (pull != UR_PULL_DIS) + return -EINVAL; + *config = pinconf_to_config_packed(param, 1); + return 0; + case PIN_CONFIG_BIAS_PULL_UP: + if (pull != UR_PULL_UP) + return -EINVAL; + *config = pinconf_to_config_packed(param, 1); + return 0; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (pull != UR_PULL_DOWN) + return -EINVAL; + *config = pinconf_to_config_packed(param, 1); + return 0; + case PIN_CONFIG_DRIVE_STRENGTH: + if (drive >= ARRAY_SIZE(ur_drive_strengths)) + return -EINVAL; + *config = pinconf_to_config_packed(param, ur_drive_strengths[drive]); + return 0; + default: + return -EINVAL; + } +} + +static int ur_config_to_hw(unsigned long config, u32 *conf) +{ + enum pin_config_param param = pinconf_to_config_param(config); + u32 arg = pinconf_to_config_argument(config); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_DIS); + return 0; + case PIN_CONFIG_BIAS_PULL_UP: + FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_UP); + return 0; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + FIELD_MODIFY(UR_PULL_MASK, conf, UR_PULL_DOWN); + return 0; + case PIN_CONFIG_DRIVE_STRENGTH: + for (u32 i = 0; i < ARRAY_SIZE(ur_drive_strengths); i++) { + if (ur_drive_strengths[i] != arg) + continue; + FIELD_MODIFY(UR_DRIVE_MASK, conf, i); + return 0; + } + return -EINVAL; + case PIN_CONFIG_PERSIST_STATE: + /* + * For PIN_CONFIG_PERSIST_STATE, gpiolib only treats + * -ENOTSUPP as an optional unsupported result. + * Do not use -EOPNOTSUPP here. + */ + return -ENOTSUPP; + default: + return -EOPNOTSUPP; + } +} + +/** + * ur_find_group_route() - Find the route matching a function and pin set + * @pctrl: pin controller instance + * @function: mux function name + * @group_mask: bitmap of pins in the selected group + * @route_out: returned route entry on success + * + * A mux function may be associated with multiple hardware routing options, + * each valid for a specific set of pins. This helper finds the unique route + * whose valid_pins mask covers all pins in @group_mask. + * + * The routing table must guarantee that a given function plus pin set + * resolves to exactly one route. If multiple routes match, the routing + * description is considered ambiguous and the lookup fails. + * + * Return: 0 on success, or -EINVAL if no matching route exists or if the + * routing table contains ambiguous entries. + */ +static int ur_find_group_route(struct ur_pinctrl *pctrl, + const char *function, + u64 group_mask, + const struct ur_func_route **route_out) +{ + const struct ur_func_route *match = NULL; + + for (u32 i = 0; i < pctrl->data->num_routes; i++) { + const struct ur_func_route *route = &pctrl->data->routes[i]; + + if (strcmp(route->function, function)) + continue; + + if ((route->valid_pins & group_mask) != group_mask) + continue; + + if (match) { + dev_err(pctrl->dev, + "ambiguous route for function %s group_mask=%#llx\n", + function, (unsigned long long)group_mask); + return -EINVAL; + } + + match = route; + } + + if (match) { + *route_out = match; + return 0; + } + + return -EINVAL; +} + +static const char *ur_get_group_function(struct pinctrl_dev *pctldev, + unsigned int group_selector, + unsigned int pin_index) +{ + const struct group_desc *group; + const char * const *functions; + + group = pinctrl_generic_get_group(pctldev, group_selector); + if (!group || pin_index >= group->grp.npins || !group->data) + return NULL; + + functions = group->data; + + return functions[pin_index]; +} + +static int ur_resolve_group_mux(struct pinctrl_dev *pctldev, + struct ur_pinctrl *pctrl, + unsigned int group_selector, + const unsigned int *pins, + unsigned int npins, + const struct ur_func_route **route_out) +{ + const char *function; + u64 group_mask = 0; + + if (!npins) + return -EINVAL; + + function = ur_get_group_function(pctldev, group_selector, 0); + if (!function) + return -EINVAL; + + for (u32 i = 0; i < npins; i++) + group_mask |= BIT_ULL(pins[i]); + + return ur_find_group_route(pctrl, function, group_mask, route_out); +} + +static bool ur_function_is_gpio(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + const struct function_desc *function; + + function = pinmux_generic_get_function(pctldev, selector); + if (!function) + return false; + + for (u32 i = 0; i < function->func->ngroups; i++) { + const char *func_name; + int group_selector; + + group_selector = pinctrl_get_group_selector(pctldev, + function->func->groups[i]); + if (group_selector < 0) + return false; + + func_name = ur_get_group_function(pctldev, group_selector, 0); + if (!func_name || strcmp(func_name, "gpio")) + return false; + } + + return true; +} + +static const struct pinctrl_ops ur_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinctrl_generic_pins_function_dt_node_to_map, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static int ur_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct ur_port_desc *port_desc; + const struct ur_func_route *route; + int ret; + + (void)range; + + port_desc = ur_get_pin_port(pctldev, offset); + if (!port_desc || !port_desc->supports_gpio) + return -EINVAL; + + ret = ur_find_group_route(pctrl, "gpio", BIT_ULL(offset), &route); + if (ret) + return ret; + + return ur_set_pin_mux_by_num(pctrl, offset, route->mode); +} + +static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct ur_func_route *route; + const unsigned int *pins; + unsigned int npins; + int ret; + + (void)func_selector; + + ret = pinctrl_generic_get_group_pins(pctldev, group_selector, &pins, &npins); + if (ret) + return ret; + + ret = ur_resolve_group_mux(pctldev, pctrl, group_selector, pins, npins, + &route); + if (ret) + return ret; + + for (u32 i = 0; i < npins; i++) { + ret = ur_set_pin_mux_by_num(pctrl, pins[i], route->mode); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinmux_ops ur_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .function_is_gpio = ur_function_is_gpio, + .set_mux = ur_set_mux, + .gpio_request_enable = ur_gpio_request_enable, + .strict = true, +}; + +static int ur_pin_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + u32 conf; + int ret; + + ret = ur_read_pin_conf(pctrl, pin, &conf); + if (ret) + return ret; + + return ur_hw_to_config(config, conf); +} + +static int ur_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct ur_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + u32 conf; + int ret; + + ret = ur_read_pin_conf(pctrl, pin, &conf); + if (ret) + return ret; + + for (u32 i = 0; i < num_configs; i++) { + ret = ur_config_to_hw(configs[i], &conf); + if (ret) + return ret; + } + + return ur_write_pin_conf(pctrl, pin, conf); +} + +static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *config) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret || !npins) + return ret ?: -EINVAL; + + return ur_pin_config_get(pctldev, pins[0], config); +} + +static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret) + return ret; + + for (u32 i = 0; i < npins; i++) { + ret = ur_pin_config_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops ur_pinconf_ops = { + .pin_config_get = ur_pin_config_get, + .pin_config_set = ur_pin_config_set, + .pin_config_group_get = ur_pin_config_group_get, + .pin_config_group_set = ur_pin_config_group_set, + .is_generic = true, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +int ur_pinctrl_probe(struct platform_device *pdev, + const struct ur_pinctrl_data *data) +{ + struct pinctrl_desc *desc; + struct ur_pinctrl *pctrl; + int ret; + + if (!data) + return -ENODEV; + + desc = devm_kzalloc(&pdev->dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->base)) + return PTR_ERR(pctrl->base); + pctrl->dev = &pdev->dev; + pctrl->data = data; + + raw_spin_lock_init(&pctrl->lock); + + desc->name = dev_name(&pdev->dev); + desc->owner = THIS_MODULE; + desc->pins = data->pins; + desc->npins = data->npins; + desc->pctlops = &ur_pinctrl_ops; + desc->pmxops = &ur_pinmux_ops; + desc->confops = &ur_pinconf_ops; + + ret = devm_pinctrl_register_and_init(&pdev->dev, desc, pctrl, &pctrl->pctl_dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to register pinctrl\n"); + + platform_set_drvdata(pdev, pctrl); + + return pinctrl_enable(pctrl->pctl_dev); +} +EXPORT_SYMBOL_GPL(ur_pinctrl_probe); + +MODULE_DESCRIPTION("UltraRISC pinctrl core driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h new file mode 100644 index 000000000000..c874688aafca --- /dev/null +++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + * + * Author: Jia Wang <wangjia@ultrarisc.com> + */ + +#ifndef __PINCTRL_ULTRARISC_H__ +#define __PINCTRL_ULTRARISC_H__ + +#include <linux/io.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/spinlock.h> + +struct platform_device; + +#define UR_FUNC_DEFAULT 0U +#define UR_FUNC_0 1U +#define UR_FUNC_1 0x10000U + +#define UR_MAX_PINS_PER_PORT 16 + +#define UR_BIAS_MASK 0x0000000F +#define UR_PULL_MASK 0x0C +#define UR_PULL_DIS 0 +#define UR_PULL_UP 1 +#define UR_PULL_DOWN 2 +#define UR_DRIVE_MASK 0x03 + +struct ur_port_desc { + u32 pin_base; + u32 npins; + u32 func_offset; + u32 conf_offset; + u32 supported_modes; + bool supports_gpio; +}; + +struct ur_func_route { + const char *function; + u32 mode; + u64 valid_pins; +}; + +struct ur_pinctrl_data { + const struct pinctrl_pin_desc *pins; + u32 npins; + const struct ur_func_route *routes; + u32 num_routes; +}; + +struct ur_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl_dev; + const struct ur_pinctrl_data *data; + void __iomem *base; + raw_spinlock_t lock; /* Protects mux and conf registers */ +}; + +int ur_pinctrl_probe(struct platform_device *pdev, + const struct ur_pinctrl_data *data); + +#endif diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 65ed20bc1fa2..f1019f041f11 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index a68b21fbd0c7..bb52497d5fc4 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index 88fd68f86a85..3aebc77529ed 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 374c029ebc02..07706b57bc37 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c index 4fd3ec511d37..25a5e4db6e98 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c @@ -5,7 +5,6 @@ #include <linux/init.h> #include <linux/kernel.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index 4f63d7b1a252..bc20a2d0d64d 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 4277d494a348..39915be4128c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 2a9dbf969f0b..cd6429f58276 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index ab3bd2d9c6c7..d07788c785d4 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -5,7 +5,6 @@ #include <linux/init.h> #include <linux/kernel.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 087e8db8f11d..78d254070988 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -5,7 +5,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mod_devicetable.h> #include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> diff --git a/drivers/pinctrl/vt8500/Kconfig b/drivers/pinctrl/vt8500/Kconfig index 2ca00b54b7a8..1a40c153a82a 100644 --- a/drivers/pinctrl/vt8500/Kconfig +++ b/drivers/pinctrl/vt8500/Kconfig @@ -3,16 +3,17 @@ # VIA/Wondermedia PINCTRL drivers # -if ARCH_VT8500 +if ARCH_VT8500 || COMPILE_TEST config PINCTRL_WMT bool select PINMUX select GENERIC_PINCONF + select GPIOLIB config PINCTRL_VT8500 bool "VIA VT8500 pin controller driver" - depends on ARCH_WM8505 + depends on ARCH_WM8505 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -20,7 +21,7 @@ config PINCTRL_VT8500 config PINCTRL_WM8505 bool "Wondermedia WM8505 pin controller driver" - depends on ARCH_WM8505 + depends on ARCH_WM8505 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -28,7 +29,7 @@ config PINCTRL_WM8505 config PINCTRL_WM8650 bool "Wondermedia WM8650 pin controller driver" - depends on ARCH_WM8505 + depends on ARCH_WM8505 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -36,7 +37,7 @@ config PINCTRL_WM8650 config PINCTRL_WM8750 bool "Wondermedia WM8750 pin controller driver" - depends on ARCH_WM8750 + depends on ARCH_WM8750 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on @@ -44,7 +45,7 @@ config PINCTRL_WM8750 config PINCTRL_WM8850 bool "Wondermedia WM8850 pin controller driver" - depends on ARCH_WM8850 + depends on ARCH_WM8850 || COMPILE_TEST select PINCTRL_WMT help Say yes here to support the gpio/pin control module on |