diff options
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/axp20x.h | 3 | ||||
| -rw-r--r-- | include/linux/mfd/rk808.h | 118 | ||||
| -rw-r--r-- | include/linux/mfd/rohm-bd71828.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/rohm-bd72720.h | 634 | ||||
| -rw-r--r-- | include/linux/mfd/rohm-generic.h | 1 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/core.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/irq.h | 105 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/s2mpg10.h | 44 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/s2mpg11.h | 434 | ||||
| -rw-r--r-- | include/linux/mfd/tps6105x.h | 5 | ||||
| -rw-r--r-- | include/linux/mfd/tps65219.h | 2 | ||||
| -rw-r--r-- | include/linux/mfd/wm8350/core.h | 2 |
12 files changed, 1338 insertions, 14 deletions
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 3c5aecf1d4b5..b352661d99a1 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -174,6 +174,9 @@ enum axp20x_variants { #define AXP717_ADC_DATA_SEL 0xcd #define AXP717_ADC_DATA_H 0xce #define AXP717_ADC_DATA_L 0xcf +#define AXP717_TYPEC_CC_AA_EN 0xe1 +#define AXP717_TYPEC_CC_MODE_CONTROL 0xe3 +#define AXP717_TYPEC_CC_STATUS 0xe7 #define AXP806_STARTUP_SRC 0x00 #define AXP806_CHIP_ID 0x03 diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h index 28170ee08898..7ffc904c864c 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -340,6 +340,123 @@ enum rk818_reg { #define RK818_USB_ILMIN_2000MA 0x7 #define RK818_USB_CHG_SD_VSEL_MASK 0x70 +/* RK801 */ +enum rk801_reg { + RK801_ID_DCDC1, + RK801_ID_DCDC2, + RK801_ID_DCDC4, + RK801_ID_DCDC3, + RK801_ID_LDO1, + RK801_ID_LDO2, + RK801_ID_SWITCH, + RK801_ID_MAX, +}; + +#define RK801_SLP_REG_OFFSET 5 +#define RK801_NUM_REGULATORS 7 + +#define RK801_HW_SYNC_US 32 + +/* RK801 Register Definitions */ +#define RK801_ID_MSB 0x00 +#define RK801_ID_LSB 0x01 +#define RK801_OTP_VER_REG 0x02 +#define RK801_POWER_EN0_REG 0x03 +#define RK801_POWER_EN1_REG 0x04 +#define RK801_POWER_SLP_EN_REG 0x05 +#define RK801_POWER_FPWM_EN_REG 0x06 +#define RK801_SLP_LP_CONFIG_REG 0x07 +#define RK801_BUCK_CONFIG_REG 0x08 +#define RK801_BUCK1_ON_VSEL_REG 0x09 +#define RK801_BUCK2_ON_VSEL_REG 0x0a +#define RK801_BUCK4_ON_VSEL_REG 0x0b +#define RK801_LDO1_ON_VSEL_REG 0x0c +#define RK801_LDO2_ON_VSEL_REG 0x0d +#define RK801_BUCK1_SLP_VSEL_REG 0x0e +#define RK801_BUCK2_SLP_VSEL_REG 0x0f +#define RK801_BUCK4_SLP_VSEL_REG 0x10 +#define RK801_LDO1_SLP_VSEL_REG 0x11 +#define RK801_LDO2_SLP_VSEL_REG 0x12 +#define RK801_LDO_SW_IMAX_REG 0x13 +#define RK801_SYS_STS_REG 0x14 +#define RK801_SYS_CFG0_REG 0x15 +#define RK801_SYS_CFG1_REG 0x16 +#define RK801_SYS_CFG2_REG 0x17 +#define RK801_SYS_CFG3_REG 0x18 +#define RK801_SYS_CFG4_REG 0x19 +#define RK801_SLEEP_CFG_REG 0x1a +#define RK801_ON_SOURCE_REG 0x1b +#define RK801_OFF_SOURCE_REG 0x1c +#define RK801_PWRON_KEY_REG 0x1d +#define RK801_INT_STS0_REG 0x1e +#define RK801_INT_MASK0_REG 0x1f +#define RK801_INT_CONFIG_REG 0x20 +#define RK801_CON_BACK1_REG 0x21 +#define RK801_CON_BACK2_REG 0x22 +#define RK801_DATA_CON0_REG 0x23 +#define RK801_DATA_CON1_REG 0x24 +#define RK801_DATA_CON2_REG 0x25 +#define RK801_DATA_CON3_REG 0x26 +#define RK801_POWER_EXIT_SLP_SEQ0_REG 0x27 +#define RK801_POWER_EXIT_SLP_SEQ1_REG 0x28 +#define RK801_POWER_EXIT_SLP_SEQ2_REG 0x29 +#define RK801_POWER_EXIT_SLP_SEQ3_REG 0x2a +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ0_REG 0x2b +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ1_REG 0x2c +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ2_REG 0x2d +#define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ3_REG 0x2e +#define RK801_BUCK_DEBUG1_REG 0x2f +#define RK801_BUCK_DEBUG2_REG 0x30 +#define RK801_BUCK_DEBUG3_REG 0x31 +#define RK801_BUCK_DEBUG4_REG 0x32 +#define RK801_BUCK_DEBUG5_REG 0x33 +#define RK801_BUCK_DEBUG7_REG 0x34 +#define RK801_OTP_EN_CON_REG 0x35 +#define RK801_TEST_CON_REG 0x36 +#define RK801_EFUSE_CONTROL_REG 0x37 +#define RK801_SYS_CFG3_OTP_REG 0x38 + +/* RK801 IRQ Definitions */ +#define RK801_IRQ_PWRON_FALL 0 +#define RK801_IRQ_PWRON_RISE 1 +#define RK801_IRQ_PWRON 2 +#define RK801_IRQ_PWRON_LP 3 +#define RK801_IRQ_HOTDIE 4 +#define RK801_IRQ_VDC_RISE 5 +#define RK801_IRQ_VDC_FALL 6 +#define RK801_IRQ_PWRON_FALL_MSK BIT(0) +#define RK801_IRQ_PWRON_RISE_MSK BIT(1) +#define RK801_IRQ_PWRON_MSK BIT(2) +#define RK801_IRQ_PWRON_LP_MSK BIT(3) +#define RK801_IRQ_HOTDIE_MSK BIT(4) +#define RK801_IRQ_VDC_RISE_MSK BIT(5) +#define RK801_IRQ_VDC_FALL_MSK BIT(6) +/* RK801_SLP_LP_CONFIG_REG */ +#define RK801_BUCK_SLP_LP_EN BIT(3) +#define RK801_PLDO_SLP_LP_EN BIT(1) +#define RK801_SLP_LP_MASK (RK801_PLDO_SLP_LP_EN | RK801_BUCK_SLP_LP_EN) +/* RK801_SLEEP_CFG_REG */ +#define RK801_SLEEP_FUN_MSK 0x3 +#define RK801_NONE_FUN 0x0 +#define RK801_SLEEP_FUN 0x1 +#define RK801_SHUTDOWN_FUN 0x2 +#define RK801_RESET_FUN 0x3 +/* RK801_SYS_CFG2_REG */ +#define RK801_SLEEP_POL_MSK BIT(1) +#define RK801_SLEEP_ACT_H BIT(1) +#define RK801_SLEEP_ACT_L 0 +#define RK801_RST_MSK (0x3 << 4) +#define RK801_RST_RESTART_PMU (0x0 << 4) +#define RK801_RST_RESTART_REG (0x1 << 4) +#define RK801_RST_RESTART_REG_RESETB (0x2 << 4) +/* RK801_INT_CONFIG_REG */ +#define RK801_INT_POL_MSK BIT(1) +#define RK801_INT_ACT_H BIT(1) +#define RK801_INT_ACT_L 0 +#define RK801_FPWM_MODE 1 +#define RK801_AUTO_PWM_MODE 0 +#define RK801_PLDO_HRDEC_EN BIT(6) + /* RK805 */ enum rk805_reg { RK805_ID_DCDC1, @@ -1332,6 +1449,7 @@ enum { }; enum { + RK801_ID = 0x8010, RK805_ID = 0x8050, RK806_ID = 0x8060, RK808_ID = 0x0000, diff --git a/include/linux/mfd/rohm-bd71828.h b/include/linux/mfd/rohm-bd71828.h index 73a71ef69152..39fe275a8117 100644 --- a/include/linux/mfd/rohm-bd71828.h +++ b/include/linux/mfd/rohm-bd71828.h @@ -249,6 +249,8 @@ enum { #define BD71828_REG_BATCAP_MON_LIMIT_U 0xcc #define BD71828_REG_CONF 0x64 +#define BD71828_REG_ILIM_STAT 0x6d +#define BD71828_REG_DCIN_SET 0x70 #define BD71828_REG_DCIN_CLPS 0x71 #define BD71828_REG_MEAS_CLEAR 0xaf diff --git a/include/linux/mfd/rohm-bd72720.h b/include/linux/mfd/rohm-bd72720.h new file mode 100644 index 000000000000..ae7343bcab06 --- /dev/null +++ b/include/linux/mfd/rohm-bd72720.h @@ -0,0 +1,634 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2025 ROHM Semiconductors. + * + * Author: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> + */ + +#ifndef _MFD_BD72720_H +#define _MFD_BD72720_H + +#include <linux/regmap.h> + +enum { + BD72720_BUCK1, + BD72720_BUCK2, + BD72720_BUCK3, + BD72720_BUCK4, + BD72720_BUCK5, + BD72720_BUCK6, + BD72720_BUCK7, + BD72720_BUCK8, + BD72720_BUCK9, + BD72720_BUCK10, + BD72720_BUCK11, + BD72720_LDO1, + BD72720_LDO2, + BD72720_LDO3, + BD72720_LDO4, + BD72720_LDO5, + BD72720_LDO6, + BD72720_LDO7, + BD72720_LDO8, + BD72720_LDO9, + BD72720_LDO10, + BD72720_LDO11, + BD72720_REGULATOR_AMOUNT, +}; + +/* BD72720 interrupts */ +#define BD72720_INT_LONGPUSH_MASK BIT(0) +#define BD72720_INT_MIDPUSH_MASK BIT(1) +#define BD72720_INT_SHORTPUSH_MASK BIT(2) +#define BD72720_INT_PUSH_MASK BIT(3) +#define BD72720_INT_HALL_DET_MASK BIT(4) +#define BD72720_INT_HALL_TGL_MASK BIT(5) +#define BD72720_INT_WDOG_MASK BIT(6) +#define BD72720_INT_SWRESET_MASK BIT(7) +#define BD72720_INT_SEQ_DONE_MASK BIT(0) +#define BD72720_INT_PGFAULT_MASK BIT(4) +#define BD72720_INT_BUCK1_DVS_MASK BIT(0) +#define BD72720_INT_BUCK2_DVS_MASK BIT(1) +#define BD72720_INT_BUCK3_DVS_MASK BIT(2) +#define BD72720_INT_BUCK4_DVS_MASK BIT(3) +#define BD72720_INT_BUCK5_DVS_MASK BIT(4) +#define BD72720_INT_BUCK6_DVS_MASK BIT(5) +#define BD72720_INT_BUCK7_DVS_MASK BIT(6) +#define BD72720_INT_BUCK8_DVS_MASK BIT(7) +#define BD72720_INT_BUCK9_DVS_MASK BIT(0) +#define BD72720_INT_BUCK10_DVS_MASK BIT(1) +#define BD72720_INT_LDO1_DVS_MASK BIT(4) +#define BD72720_INT_LDO2_DVS_MASK BIT(5) +#define BD72720_INT_LDO3_DVS_MASK BIT(6) +#define BD72720_INT_LDO4_DVS_MASK BIT(7) +#define BD72720_INT_VBUS_RMV_MASK BIT(0) +#define BD72720_INT_VBUS_DET_MASK BIT(1) +#define BD72720_INT_VBUS_MON_RES_MASK BIT(2) +#define BD72720_INT_VBUS_MON_DET_MASK BIT(3) +#define BD72720_INT_VSYS_MON_RES_MASK BIT(0) +#define BD72720_INT_VSYS_MON_DET_MASK BIT(1) +#define BD72720_INT_VSYS_UV_RES_MASK BIT(2) +#define BD72720_INT_VSYS_UV_DET_MASK BIT(3) +#define BD72720_INT_VSYS_LO_RES_MASK BIT(4) +#define BD72720_INT_VSYS_LO_DET_MASK BIT(5) +#define BD72720_INT_VSYS_OV_RES_MASK BIT(6) +#define BD72720_INT_VSYS_OV_DET_MASK BIT(7) +#define BD72720_INT_BAT_ILIM_MASK BIT(0) +#define BD72720_INT_CHG_DONE_MASK BIT(1) +#define BD72720_INT_EXTEMP_TOUT_MASK BIT(2) +#define BD72720_INT_CHG_WDT_EXP_MASK BIT(3) +#define BD72720_INT_BAT_MNT_OUT_MASK BIT(4) +#define BD72720_INT_BAT_MNT_IN_MASK BIT(5) +#define BD72720_INT_CHG_TRNS_MASK BIT(7) +#define BD72720_INT_VBAT_MON_RES_MASK BIT(0) +#define BD72720_INT_VBAT_MON_DET_MASK BIT(1) +#define BD72720_INT_VBAT_SHT_RES_MASK BIT(2) +#define BD72720_INT_VBAT_SHT_DET_MASK BIT(3) +#define BD72720_INT_VBAT_LO_RES_MASK BIT(4) +#define BD72720_INT_VBAT_LO_DET_MASK BIT(5) +#define BD72720_INT_VBAT_OV_RES_MASK BIT(6) +#define BD72720_INT_VBAT_OV_DET_MASK BIT(7) +#define BD72720_INT_BAT_RMV_MASK BIT(0) +#define BD72720_INT_BAT_DET_MASK BIT(1) +#define BD72720_INT_DBAT_DET_MASK BIT(2) +#define BD72720_INT_BAT_TEMP_TRNS_MASK BIT(3) +#define BD72720_INT_LOBTMP_RES_MASK BIT(4) +#define BD72720_INT_LOBTMP_DET_MASK BIT(5) +#define BD72720_INT_OVBTMP_RES_MASK BIT(6) +#define BD72720_INT_OVBTMP_DET_MASK BIT(7) +#define BD72720_INT_OCUR1_RES_MASK BIT(0) +#define BD72720_INT_OCUR1_DET_MASK BIT(1) +#define BD72720_INT_OCUR2_RES_MASK BIT(2) +#define BD72720_INT_OCUR2_DET_MASK BIT(3) +#define BD72720_INT_OCUR3_RES_MASK BIT(4) +#define BD72720_INT_OCUR3_DET_MASK BIT(5) +#define BD72720_INT_CC_MON1_DET_MASK BIT(0) +#define BD72720_INT_CC_MON2_DET_MASK BIT(1) +#define BD72720_INT_CC_MON3_DET_MASK BIT(2) +#define BD72720_INT_GPIO1_IN_MASK BIT(4) +#define BD72720_INT_GPIO2_IN_MASK BIT(5) +#define BD72720_INT_VF125_RES_MASK BIT(0) +#define BD72720_INT_VF125_DET_MASK BIT(1) +#define BD72720_INT_VF_RES_MASK BIT(2) +#define BD72720_INT_VF_DET_MASK BIT(3) +#define BD72720_INT_RTC0_MASK BIT(4) +#define BD72720_INT_RTC1_MASK BIT(5) +#define BD72720_INT_RTC2_MASK BIT(6) + +enum { + /* + * The IRQs excluding GPIO1 and GPIO2 are ordered in a same way as the + * respective IRQ bits in status and mask registers are ordered. + * + * The BD72720_INT_GPIO1_IN and BD72720_INT_GPIO2_IN are IRQs which can + * be used by other devices. Let's have GPIO1 and GPIO2 as first IRQs + * here so we can use the regmap-IRQ with standard device tree xlate + * while devices connected to the BD72720 IRQ input pins can refer to + * the first two interrupt numbers in their device tree. If we placed + * BD72720_INT_GPIO1_IN and BD72720_INT_GPIO2_IN after the CC_MON_DET + * interrupts (like they are in the registers), the devices using + * BD72720 as an IRQ parent should refer the interrupts starting with + * an offset which might not be trivial to understand. + */ + BD72720_INT_GPIO1_IN, + BD72720_INT_GPIO2_IN, + BD72720_INT_LONGPUSH, + BD72720_INT_MIDPUSH, + BD72720_INT_SHORTPUSH, + BD72720_INT_PUSH, + BD72720_INT_HALL_DET, + BD72720_INT_HALL_TGL, + BD72720_INT_WDOG, + BD72720_INT_SWRESET, + BD72720_INT_SEQ_DONE, + BD72720_INT_PGFAULT, + BD72720_INT_BUCK1_DVS, + BD72720_INT_BUCK2_DVS, + BD72720_INT_BUCK3_DVS, + BD72720_INT_BUCK4_DVS, + BD72720_INT_BUCK5_DVS, + BD72720_INT_BUCK6_DVS, + BD72720_INT_BUCK7_DVS, + BD72720_INT_BUCK8_DVS, + BD72720_INT_BUCK9_DVS, + BD72720_INT_BUCK10_DVS, + BD72720_INT_LDO1_DVS, + BD72720_INT_LDO2_DVS, + BD72720_INT_LDO3_DVS, + BD72720_INT_LDO4_DVS, + BD72720_INT_VBUS_RMV, + BD72720_INT_VBUS_DET, + BD72720_INT_VBUS_MON_RES, + BD72720_INT_VBUS_MON_DET, + BD72720_INT_VSYS_MON_RES, + BD72720_INT_VSYS_MON_DET, + BD72720_INT_VSYS_UV_RES, + BD72720_INT_VSYS_UV_DET, + BD72720_INT_VSYS_LO_RES, + BD72720_INT_VSYS_LO_DET, + BD72720_INT_VSYS_OV_RES, + BD72720_INT_VSYS_OV_DET, + BD72720_INT_BAT_ILIM, + BD72720_INT_CHG_DONE, + BD72720_INT_EXTEMP_TOUT, + BD72720_INT_CHG_WDT_EXP, + BD72720_INT_BAT_MNT_OUT, + BD72720_INT_BAT_MNT_IN, + BD72720_INT_CHG_TRNS, + BD72720_INT_VBAT_MON_RES, + BD72720_INT_VBAT_MON_DET, + BD72720_INT_VBAT_SHT_RES, + BD72720_INT_VBAT_SHT_DET, + BD72720_INT_VBAT_LO_RES, + BD72720_INT_VBAT_LO_DET, + BD72720_INT_VBAT_OV_RES, + BD72720_INT_VBAT_OV_DET, + BD72720_INT_BAT_RMV, + BD72720_INT_BAT_DET, + BD72720_INT_DBAT_DET, + BD72720_INT_BAT_TEMP_TRNS, + BD72720_INT_LOBTMP_RES, + BD72720_INT_LOBTMP_DET, + BD72720_INT_OVBTMP_RES, + BD72720_INT_OVBTMP_DET, + BD72720_INT_OCUR1_RES, + BD72720_INT_OCUR1_DET, + BD72720_INT_OCUR2_RES, + BD72720_INT_OCUR2_DET, + BD72720_INT_OCUR3_RES, + BD72720_INT_OCUR3_DET, + BD72720_INT_CC_MON1_DET, + BD72720_INT_CC_MON2_DET, + BD72720_INT_CC_MON3_DET, + BD72720_INT_VF125_RES, + BD72720_INT_VF125_DET, + BD72720_INT_VF_RES, + BD72720_INT_VF_DET, + BD72720_INT_RTC0, + BD72720_INT_RTC1, + BD72720_INT_RTC2, +}; + +/* + * BD72720 Registers: + * The BD72720 has two sets of registers behind two different I2C slave + * addresses. "Common" registers being behind 0x4b, the charger registers + * being behind 0x4c. + */ +/* Registers behind I2C slave 0x4b */ +enum { + BD72720_REG_PRODUCT_ID, + BD72720_REG_MANUFACTURER_ID, + BD72720_REG_PMIC_REV_NUM, + BD72720_REG_NVM_REV_NUM, + BD72720_REG_BOOTSRC = 0x10, + BD72720_REG_RESETSRC_1, + BD72720_REG_RESETSRC_2, + BD72720_REG_RESETSRC_3, + BD72720_REG_RESETSRC_4, + BD72720_REG_RESETSRC_5, + BD72720_REG_RESETSRC_6, + BD72720_REG_RESETSRC_7, + BD72720_REG_POWER_STATE, + BD72720_REG_PS_CFG, + BD72720_REG_PS_CTRL_1, + BD72720_REG_PS_CTRL_2, + BD72720_REG_RCVCFG, + BD72720_REG_RCVNUM, + BD72720_REG_CRDCFG, + BD72720_REG_REX_CTRL, + + BD72720_REG_BUCK1_ON, + BD72720_REG_BUCK1_MODE, + /* Deep idle vsel */ + BD72720_REG_BUCK1_VSEL_DI, + /* Idle vsel */ + BD72720_REG_BUCK1_VSEL_I, + /* Suspend vsel */ + BD72720_REG_BUCK1_VSEL_S, + /* Run boot vsel */ + BD72720_REG_BUCK1_VSEL_RB, + /* Run0 ... run3 vsel */ + BD72720_REG_BUCK1_VSEL_RB0, + BD72720_REG_BUCK1_VSEL_RB1, + BD72720_REG_BUCK1_VSEL_RB2, + BD72720_REG_BUCK1_VSEL_RB3, + + BD72720_REG_BUCK2_ON, + BD72720_REG_BUCK2_MODE, + BD72720_REG_BUCK2_VSEL_DI, + BD72720_REG_BUCK2_VSEL_I, + BD72720_REG_BUCK2_VSEL_S, + /* Run vsel */ + BD72720_REG_BUCK2_VSEL_R, + + BD72720_REG_BUCK3_ON, + BD72720_REG_BUCK3_MODE, + BD72720_REG_BUCK3_VSEL_DI, + BD72720_REG_BUCK3_VSEL_I, + BD72720_REG_BUCK3_VSEL_S, + BD72720_REG_BUCK3_VSEL_R, + + BD72720_REG_BUCK4_ON, + BD72720_REG_BUCK4_MODE, + BD72720_REG_BUCK4_VSEL_DI, + BD72720_REG_BUCK4_VSEL_I, + BD72720_REG_BUCK4_VSEL_S, + BD72720_REG_BUCK4_VSEL_R, + + BD72720_REG_BUCK5_ON, + BD72720_REG_BUCK5_MODE, + BD72720_REG_BUCK5_VSEL, + + BD72720_REG_BUCK6_ON, + BD72720_REG_BUCK6_MODE, + BD72720_REG_BUCK6_VSEL, + + BD72720_REG_BUCK7_ON, + BD72720_REG_BUCK7_MODE, + BD72720_REG_BUCK7_VSEL, + + BD72720_REG_BUCK8_ON, + BD72720_REG_BUCK8_MODE, + BD72720_REG_BUCK8_VSEL, + + BD72720_REG_BUCK9_ON, + BD72720_REG_BUCK9_MODE, + BD72720_REG_BUCK9_VSEL, + + BD72720_REG_BUCK10_ON, + BD72720_REG_BUCK10_MODE, + BD72720_REG_BUCK10_VSEL, + + BD72720_REG_LDO1_ON, + BD72720_REG_LDO1_MODE1, + BD72720_REG_LDO1_MODE2, + BD72720_REG_LDO1_VSEL_DI, + BD72720_REG_LDO1_VSEL_I, + BD72720_REG_LDO1_VSEL_S, + BD72720_REG_LDO1_VSEL_RB, + BD72720_REG_LDO1_VSEL_R0, + BD72720_REG_LDO1_VSEL_R1, + BD72720_REG_LDO1_VSEL_R2, + BD72720_REG_LDO1_VSEL_R3, + + BD72720_REG_LDO2_ON, + BD72720_REG_LDO2_MODE, + BD72720_REG_LDO2_VSEL_DI, + BD72720_REG_LDO2_VSEL_I, + BD72720_REG_LDO2_VSEL_S, + BD72720_REG_LDO2_VSEL_R, + + BD72720_REG_LDO3_ON, + BD72720_REG_LDO3_MODE, + BD72720_REG_LDO3_VSEL_DI, + BD72720_REG_LDO3_VSEL_I, + BD72720_REG_LDO3_VSEL_S, + BD72720_REG_LDO3_VSEL_R, + + BD72720_REG_LDO4_ON, + BD72720_REG_LDO4_MODE, + BD72720_REG_LDO4_VSEL_DI, + BD72720_REG_LDO4_VSEL_I, + BD72720_REG_LDO4_VSEL_S, + BD72720_REG_LDO4_VSEL_R, + + BD72720_REG_LDO5_ON, + BD72720_REG_LDO5_MODE, + BD72720_REG_LDO5_VSEL, + + BD72720_REG_LDO6_ON, + BD72720_REG_LDO6_MODE, + BD72720_REG_LDO6_VSEL, + + BD72720_REG_LDO7_ON, + BD72720_REG_LDO7_MODE, + BD72720_REG_LDO7_VSEL, + + BD72720_REG_LDO8_ON, + BD72720_REG_LDO8_MODE, + BD72720_REG_LDO8_VSEL, + + BD72720_REG_LDO9_ON, + BD72720_REG_LDO9_MODE, + BD72720_REG_LDO9_VSEL, + + BD72720_REG_LDO10_ON, + BD72720_REG_LDO10_MODE, + BD72720_REG_LDO10_VSEL, + + BD72720_REG_LDO11_ON, + BD72720_REG_LDO11_MODE, + BD72720_REG_LDO11_VSEL, + + BD72720_REG_GPIO1_ON = 0x8b, + BD72720_REG_GPIO2_ON, + BD72720_REG_GPIO3_ON, + BD72720_REG_GPIO4_ON, + BD72720_REG_GPIO5_ON, + + BD72720_REG_GPIO1_CTRL, + BD72720_REG_GPIO2_CTRL, +#define BD72720_GPIO_IRQ_TYPE_MASK GENMASK(6, 4) +#define BD72720_GPIO_IRQ_TYPE_FALLING 0x0 +#define BD72720_GPIO_IRQ_TYPE_RISING 0x1 +#define BD72720_GPIO_IRQ_TYPE_BOTH 0x2 +#define BD72720_GPIO_IRQ_TYPE_HIGH 0x3 +#define BD72720_GPIO_IRQ_TYPE_LOW 0x4 + BD72720_REG_GPIO3_CTRL, + BD72720_REG_GPIO4_CTRL, + BD72720_REG_GPIO5_CTRL, +#define BD72720_GPIO_DRIVE_MASK BIT(1) +#define BD72720_GPIO_HIGH BIT(0) + + BD72720_REG_EPDEN_CTRL, + BD72720_REG_GATECNT_CTRL, + BD72720_REG_LED_CTRL, + + BD72720_REG_PWRON_CFG1, + BD72720_REG_PWRON_CFG2, + + BD72720_REG_OUT32K, + BD72720_REG_CONF, + BD72720_REG_HALL_STAT, + + BD72720_REG_RTC_SEC = 0xa0, +#define BD72720_REG_RTC_START BD72720_REG_RTC_SEC + BD72720_REG_RTC_MIN, + BD72720_REG_RTC_HOUR, + BD72720_REG_RTC_WEEK, + BD72720_REG_RTC_DAY, + BD72720_REG_RTC_MON, + BD72720_REG_RTC_YEAR, + + BD72720_REG_RTC_ALM0_SEC, +#define BD72720_REG_RTC_ALM_START BD72720_REG_RTC_ALM0_SEC + BD72720_REG_RTC_ALM0_MIN, + BD72720_REG_RTC_ALM0_HOUR, + BD72720_REG_RTC_ALM0_WEEK, + BD72720_REG_RTC_ALM0_MON, + BD72720_REG_RTC_ALM0_YEAR, + + BD72720_REG_RTC_ALM1_SEC, + BD72720_REG_RTC_ALM1_MIN, + BD72720_REG_RTC_ALM1_HOUR, + BD72720_REG_RTC_ALM1_WEEK, + BD72720_REG_RTC_ALM1_MON, + BD72720_REG_RTC_ALM1_YEAR, + + BD72720_REG_RTC_ALM0_EN, + BD72720_REG_RTC_ALM1_EN, + BD72720_REG_RTC_ALM2, + + BD72720_REG_INT_LVL1_EN = 0xc0, +#define BD72720_MASK_LVL1_EN_ALL GENMASK(7, 0) + BD72720_REG_INT_PS1_EN, + BD72720_REG_INT_PS2_EN, + BD72720_REG_INT_DVS1_EN, + BD72720_REG_INT_DVS2_EN, + BD72720_REG_INT_VBUS_EN, + BD72720_REG_INT_VSYS_EN, + BD72720_REG_INT_CHG_EN, + BD72720_REG_INT_BAT1_EN, + BD72720_REG_INT_BAT2_EN, + BD72720_REG_INT_IBAT_EN, + BD72720_REG_INT_ETC1_EN, + BD72720_REG_INT_ETC2_EN, + + /* + * The _STAT registers inform IRQ line state, and are used to ack IRQ. + * The _SRC registers below indicate current state of the function + * connected to the line. + */ + BD72720_REG_INT_LVL1_STAT, + BD72720_REG_INT_PS1_STAT, + BD72720_REG_INT_PS2_STAT, + BD72720_REG_INT_DVS1_STAT, + BD72720_REG_INT_DVS2_STAT, + BD72720_REG_INT_VBUS_STAT, + BD72720_REG_INT_VSYS_STAT, + BD72720_REG_INT_CHG_STAT, + BD72720_REG_INT_BAT1_STAT, + BD72720_REG_INT_BAT2_STAT, + BD72720_REG_INT_IBAT_STAT, + BD72720_REG_INT_ETC1_STAT, + BD72720_REG_INT_ETC2_STAT, + + BD72720_REG_INT_LVL1_SRC, + BD72720_REG_INT_PS1_SRC, + BD72720_REG_INT_PS2_SRC, + BD72720_REG_INT_DVS1_SRC, + BD72720_REG_INT_DVS2_SRC, + BD72720_REG_INT_VBUS_SRC, +#define BD72720_MASK_DCIN_DET BIT(1) + BD72720_REG_INT_VSYS_SRC, + BD72720_REG_INT_CHG_SRC, + BD72720_REG_INT_BAT1_SRC, + BD72720_REG_INT_BAT2_SRC, + BD72720_REG_INT_IBAT_SRC, + BD72720_REG_INT_ETC1_SRC, + BD72720_REG_INT_ETC2_SRC, +}; + +/* Register masks */ +#define BD72720_MASK_DEEP_IDLE_EN BIT(0) +#define BD72720_MASK_IDLE_EN BIT(1) +#define BD72720_MASK_SUSPEND_EN BIT(2) +#define BD72720_MASK_RUN_B_EN BIT(3) +#define BD72720_MASK_RUN_0_EN BIT(4) +#define BD72720_MASK_RUN_1_EN BIT(5) +#define BD72720_MASK_RUN_2_EN BIT(6) +#define BD72720_MASK_RUN_3_EN BIT(7) + +#define BD72720_MASK_RAMP_UP_DELAY GENMASK(7, 6) +#define BD72720_MASK_BUCK_VSEL GENMASK(7, 0) +#define BD72720_MASK_LDO12346_VSEL GENMASK(6, 0) +#define BD72720_MASK_LDO_VSEL GENMASK(7, 0) + +#define BD72720_I2C4C_ADDR_OFFSET 0x100 + +/* Registers behind I2C slave 0x4c */ +enum { + BD72720_REG_CHG_STATE = BD72720_I2C4C_ADDR_OFFSET, + BD72720_REG_CHG_LAST_STATE, + BD72720_REG_CHG_VBUS_STAT, + BD72720_REG_CHG_VSYS_STAT, + BD72720_REG_CHG_BAT_TEMP_STAT, + BD72720_REG_CHG_WDT_STAT, + BD72720_REG_CHG_ILIM_STAT, + BD72720_REG_CHG_CHG_STAT, + BD72720_REG_CHG_EN, + BD72720_REG_CHG_INIT, + BD72720_REG_CHG_CTRL, + BD72720_REG_CHG_SET_1, + BD72720_REG_CHG_SET_2, + BD72720_REG_CHG_SET_3, + BD72720_REG_CHG_VPRE, + BD72720_REG_CHG_VBAT_1, + BD72720_REG_CHG_VBAT_2, + BD72720_REG_CHG_VBAT_3, + BD72720_REG_CHG_VBAT_4, + BD72720_REG_CHG_BAT_SET_1, + BD72720_REG_CHG_BAT_SET_2, + BD72720_REG_CHG_BAT_SET_3, + BD72720_REG_CHG_IPRE, + BD72720_REG_CHG_IFST_TERM, + BD72720_REG_CHG_VSYS_REG, + BD72720_REG_CHG_VBUS_SET, + BD72720_REG_CHG_WDT_PRE, + BD72720_REG_CHG_WDT_FST, + BD72720_REG_CHG_LED_CTRL, + BD72720_REG_CHG_CFG_1, + BD72720_REG_CHG_IFST_1, + BD72720_REG_CHG_IFST_2, + BD72720_REG_CHG_IFST_3, + BD72720_REG_CHG_IFST_4, + BD72720_REG_CHG_S_CFG_1, + BD72720_REG_CHG_S_CFG_2, + BD72720_REG_RS_VBUS, + BD72720_REG_RS_IBUS, + BD72720_REG_RS_VSYS, + BD72720_REG_VSYS_STATE_STAT, /* 0x27 + offset*/ + + BD72720_REG_VM_VBAT_U = BD72720_I2C4C_ADDR_OFFSET + 0x30, + BD72720_REG_VM_VBAT_L, + BD72720_REG_VM_OCV_PRE_U, + BD72720_REG_VM_OCV_PRE_L, + BD72720_REG_VM_OCV_PST_U, + BD72720_REG_VM_OCV_PST_L, + BD72720_REG_VM_OCV_PWRON_U, + BD72720_REG_VM_OCV_PWRON_L, + BD72720_REG_VM_DVBAT_IMP_U, + BD72720_REG_VM_DVBAT_IMP_L, + BD72720_REG_VM_SA_VBAT_U, + BD72720_REG_VM_SA_VBAT_L, + BD72720_REG_VM_SA_VBAT_MIN_U, + BD72720_REG_VM_SA_VBAT_MIN_L, + BD72720_REG_VM_SA_VBAT_MAX_U, + BD72720_REG_VM_SA_VBAT_MAX_L, + BD72720_REG_REX_SA_VBAT_U, + BD72720_REG_REX_SA_VBAT_L, + BD72720_REG_VM_VSYS_U, + BD72720_REG_VM_VSYS_L, + BD72720_REG_VM_SA_VSYS_U, + BD72720_REG_VM_SA_VSYS_L, + BD72720_REG_VM_SA_VSYS_MIN_U, + BD72720_REG_VM_SA_VSYS_MIN_L, + BD72720_REG_VM_SA_VSYS_MAX_U, + BD72720_REG_VM_SA_VSYS_MAX_L, + BD72720_REG_VM_SA2_VSYS_U, + BD72720_REG_VM_SA2_VSYS_L, + BD72720_REG_VM_VBUS_U, +#define BD72720_MASK_VDCIN_U GENMASK(3, 0) + BD72720_REG_VM_VBUS_L, + BD72720_REG_VM_BATID_U, + BD72720_REG_VM_BATID_L, + BD72720_REG_VM_BATID_NOLOAD_U, + BD72720_REG_VM_BATID_NOLOAD_L, + BD72720_REG_VM_BATID_OFS_U, + BD72720_REG_VM_BATID_OFS_L, + BD72720_REG_VM_VTH_U, + BD72720_REG_VM_VTH_L, + BD72720_REG_VM_VTH_CORR_U, + BD72720_REG_VM_VTH_CORR_L, + BD72720_REG_VM_BTMP_U, + BD72720_REG_VM_BTMP_L, + BD72720_REG_VM_BTMP_IMP_U, + BD72720_REG_VM_BTMP_IMP_L, + BD72720_REG_VM_VF_U, + BD72720_REG_VM_VF_L, + BD72720_REG_VM_BATID_TH_U, + BD72720_REG_VM_BATID_TH_L, + BD72720_REG_VM_BTMP_OV_THR, + BD72720_REG_VM_BTMP_OV_DUR, + BD72720_REG_VM_BTMP_LO_THR, + BD72720_REG_VM_BTMP_LO_DUR, + BD72720_REG_ALM_VBAT_TH_U, + BD72720_REG_ALM_VBAT_TH_L, + BD72720_REG_ALM_VSYS_TH, + BD72720_REG_ALM_VBUS_TH, + BD72720_REG_ALM_VF_TH, + BD72720_REG_VSYS_MAX, + BD72720_REG_VSYS_MIN, + BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, + BD72720_REG_VM_SA_CFG, /* 0x6c + offset*/ + + BD72720_REG_CC_CURCD_U = BD72720_I2C4C_ADDR_OFFSET + 0x70, + BD72720_REG_CC_CURCD_L, + BD72720_REG_CC_CURCD_IMP_U, + BD72720_REG_CC_CURCD_IMP_L, + BD72720_REG_CC_SA_CURCD_U, + BD72720_REG_CC_SA_CURCD_L, + BD72720_REG_CC_OCUR_MON, + BD72720_REG_CC_CCNTD_3, + BD72720_REG_CC_CCNTD_2, + BD72720_REG_CC_CCNTD_1, + BD72720_REG_CC_CCNTD_0, + BD72720_REG_REX_CCNTD_3, + BD72720_REG_REX_CCNTD_2, + BD72720_REG_REX_CCNTD_1, + BD72720_REG_REX_CCNTD_0, + BD72720_REG_FULL_CCNTD_3, + BD72720_REG_FULL_CCNTD_2, + BD72720_REG_FULL_CCNTD_1, + BD72720_REG_FULL_CCNTD_0, + BD72720_REG_CCNTD_CHG_3, + BD72720_REG_CCNTD_CHG_2, + BD72720_REG_CC_STAT, + BD72720_REG_CC_CTRL, + BD72720_REG_CC_OCUR_THR_1, + BD72720_REG_CC_OCUR_THR_2, + BD72720_REG_CC_OCUR_THR_3, + BD72720_REG_REX_CURCD_TH, + BD72720_REG_CC_BATCAP1_TH_U, + BD72720_REG_CC_BATCAP1_TH_L, + BD72720_REG_CC_BATCAP2_TH_U, + BD72720_REG_CC_BATCAP2_TH_L, + BD72720_REG_CC_BATCAP3_TH_U, + BD72720_REG_CC_BATCAP3_TH_L, + BD72720_REG_CC_CCNTD_CTRL, + BD72720_REG_CC_SA_CFG, /* 0x92 + offset*/ + BD72720_REG_IMPCHK_CTRL = BD72720_I2C4C_ADDR_OFFSET + 0xa0, +}; + +#endif /* __LINUX_MFD_BD72720_H */ diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index 579e8dcfcca4..0a284919a6c3 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -16,6 +16,7 @@ enum rohm_chip_type { ROHM_CHIP_TYPE_BD71828, ROHM_CHIP_TYPE_BD71837, ROHM_CHIP_TYPE_BD71847, + ROHM_CHIP_TYPE_BD72720, ROHM_CHIP_TYPE_BD96801, ROHM_CHIP_TYPE_BD96802, ROHM_CHIP_TYPE_BD96805, diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index d785e101fe79..4480c631110a 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -40,6 +40,7 @@ enum sec_device_type { S2DOS05, S2MPA01, S2MPG10, + S2MPG11, S2MPS11X, S2MPS13X, S2MPS14X, @@ -69,7 +70,6 @@ struct sec_pmic_dev { int device_type; int irq; - struct regmap_irq_chip_data *irq_data; }; struct sec_platform_data { diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h index 8402a5f8e18a..6eab95de6fa8 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -166,6 +166,111 @@ enum s2mpg10_irq { S2MPG10_IRQ_NR, }; +enum s2mpg11_common_irq { + /* Top-level (common) block */ + S2MPG11_COMMON_IRQ_PMIC, + S2MPG11_COMMON_IRQ_UNUSED, +}; + +enum s2mpg11_irq { + /* PMIC */ + S2MPG11_IRQ_PWRONF, + S2MPG11_IRQ_PWRONR, + S2MPG11_IRQ_PIF_TIMEOUT_MIF, + S2MPG11_IRQ_PIF_TIMEOUTS, + S2MPG11_IRQ_WTSR, + S2MPG11_IRQ_SPD_ABNORMAL_STOP, + S2MPG11_IRQ_SPD_PARITY_ERR, +#define S2MPG11_IRQ_PWRONF_MASK BIT(0) +#define S2MPG11_IRQ_PWRONR_MASK BIT(1) +#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK BIT(3) +#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK BIT(4) +#define S2MPG11_IRQ_WTSR_MASK BIT(5) +#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6) +#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK BIT(7) + + S2MPG11_IRQ_140C, + S2MPG11_IRQ_120C, + S2MPG11_IRQ_TSD, + S2MPG11_IRQ_WRST, + S2MPG11_IRQ_NTC_CYCLE_DONE, + S2MPG11_IRQ_PMETER_OVERF, +#define S2MPG11_IRQ_INT140C_MASK BIT(0) +#define S2MPG11_IRQ_INT120C_MASK BIT(1) +#define S2MPG11_IRQ_TSD_MASK BIT(2) +#define S2MPG11_IRQ_WRST_MASK BIT(5) +#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK BIT(6) +#define S2MPG11_IRQ_PMETER_OVERF_MASK BIT(7) + + S2MPG11_IRQ_OCP_B1S, + S2MPG11_IRQ_OCP_B2S, + S2MPG11_IRQ_OCP_B3S, + S2MPG11_IRQ_OCP_B4S, + S2MPG11_IRQ_OCP_B5S, + S2MPG11_IRQ_OCP_B6S, + S2MPG11_IRQ_OCP_B7S, + S2MPG11_IRQ_OCP_B8S, +#define S2MPG11_IRQ_OCP_B1S_MASK BIT(0) +#define S2MPG11_IRQ_OCP_B2S_MASK BIT(1) +#define S2MPG11_IRQ_OCP_B3S_MASK BIT(2) +#define S2MPG11_IRQ_OCP_B4S_MASK BIT(3) +#define S2MPG11_IRQ_OCP_B5S_MASK BIT(4) +#define S2MPG11_IRQ_OCP_B6S_MASK BIT(5) +#define S2MPG11_IRQ_OCP_B7S_MASK BIT(6) +#define S2MPG11_IRQ_OCP_B8S_MASK BIT(7) + + S2MPG11_IRQ_OCP_B9S, + S2MPG11_IRQ_OCP_B10S, + S2MPG11_IRQ_OCP_BDS, + S2MPG11_IRQ_OCP_BAS, + S2MPG11_IRQ_OCP_BBS, + S2MPG11_IRQ_WLWP_ACC, + S2MPG11_IRQ_SPD_SRP_PKT_RST, +#define S2MPG11_IRQ_OCP_B9S_MASK BIT(0) +#define S2MPG11_IRQ_OCP_B10S_MASK BIT(1) +#define S2MPG11_IRQ_OCP_BDS_MASK BIT(2) +#define S2MPG11_IRQ_OCP_BAS_MASK BIT(3) +#define S2MPG11_IRQ_OCP_BBS_MASK BIT(4) +#define S2MPG11_IRQ_WLWP_ACC_MASK BIT(5) +#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK BIT(7) + + S2MPG11_IRQ_PWR_WARN_CH0, + S2MPG11_IRQ_PWR_WARN_CH1, + S2MPG11_IRQ_PWR_WARN_CH2, + S2MPG11_IRQ_PWR_WARN_CH3, + S2MPG11_IRQ_PWR_WARN_CH4, + S2MPG11_IRQ_PWR_WARN_CH5, + S2MPG11_IRQ_PWR_WARN_CH6, + S2MPG11_IRQ_PWR_WARN_CH7, +#define S2MPG11_IRQ_PWR_WARN_CH0_MASK BIT(0) +#define S2MPG11_IRQ_PWR_WARN_CH1_MASK BIT(1) +#define S2MPG11_IRQ_PWR_WARN_CH2_MASK BIT(2) +#define S2MPG11_IRQ_PWR_WARN_CH3_MASK BIT(3) +#define S2MPG11_IRQ_PWR_WARN_CH4_MASK BIT(4) +#define S2MPG11_IRQ_PWR_WARN_CH5_MASK BIT(5) +#define S2MPG11_IRQ_PWR_WARN_CH6_MASK BIT(6) +#define S2MPG11_IRQ_PWR_WARN_CH7_MASK BIT(7) + + S2MPG11_IRQ_NTC_WARN_CH0, + S2MPG11_IRQ_NTC_WARN_CH1, + S2MPG11_IRQ_NTC_WARN_CH2, + S2MPG11_IRQ_NTC_WARN_CH3, + S2MPG11_IRQ_NTC_WARN_CH4, + S2MPG11_IRQ_NTC_WARN_CH5, + S2MPG11_IRQ_NTC_WARN_CH6, + S2MPG11_IRQ_NTC_WARN_CH7, +#define S2MPG11_IRQ_NTC_WARN_CH0_MASK BIT(0) +#define S2MPG11_IRQ_NTC_WARN_CH1_MASK BIT(1) +#define S2MPG11_IRQ_NTC_WARN_CH2_MASK BIT(2) +#define S2MPG11_IRQ_NTC_WARN_CH3_MASK BIT(3) +#define S2MPG11_IRQ_NTC_WARN_CH4_MASK BIT(4) +#define S2MPG11_IRQ_NTC_WARN_CH5_MASK BIT(5) +#define S2MPG11_IRQ_NTC_WARN_CH6_MASK BIT(6) +#define S2MPG11_IRQ_NTC_WARN_CH7_MASK BIT(7) + + S2MPG11_IRQ_NR, +}; + enum s2mps11_irq { S2MPS11_IRQ_PWRONF, S2MPS11_IRQ_PWRONR, diff --git a/include/linux/mfd/samsung/s2mpg10.h b/include/linux/mfd/samsung/s2mpg10.h index 9f5919b89a3c..8e5cf21cbd5a 100644 --- a/include/linux/mfd/samsung/s2mpg10.h +++ b/include/linux/mfd/samsung/s2mpg10.h @@ -290,6 +290,30 @@ enum s2mpg10_pmic_reg { S2MPG10_PMIC_LDO_SENSE4, }; +/* Rail controlled externally, based on PCTRLSELx */ +#define S2MPG10_PMIC_CTRL_ENABLE_EXT BIT(0) + +/* For S2MPG10_PMIC_PCTRLSELx */ +#define S2MPG10_PCTRLSEL_PWREN 0x1 /* PWREN pin */ +#define S2MPG10_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */ +#define S2MPG10_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */ +#define S2MPG10_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */ +#define S2MPG10_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */ +#define S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */ +#define S2MPG10_PCTRLSEL_CPUCL1_EN 0x7 /* CPUCL1_EN pin */ +#define S2MPG10_PCTRLSEL_CPUCL1_EN2 0x8 /* CPUCL1_EN & PWREN pins */ +#define S2MPG10_PCTRLSEL_CPUCL2_EN 0x9 /* CPUCL2_EN pin */ +#define S2MPG10_PCTRLSEL_CPUCL2_EN2 0xa /* CPUCL2_E2 & PWREN pins */ +#define S2MPG10_PCTRLSEL_TPU_EN 0xb /* TPU_EN pin */ +#define S2MPG10_PCTRLSEL_TPU_EN2 0xc /* TPU_EN & ~AP_ACTIVE_N pins */ +#define S2MPG10_PCTRLSEL_TCXO_ON 0xd /* TCXO_ON pin */ +#define S2MPG10_PCTRLSEL_TCXO_ON2 0xe /* TCXO_ON & ~AP_ACTIVE_N pins */ + +/* For S2MPG10_PMIC_PCTRLSELx of LDO20M */ +#define S2MPG10_PCTRLSEL_LDO20M_EN2 0x1 /* VLDO20M_EN & LDO20M_SFR */ +#define S2MPG10_PCTRLSEL_LDO20M_EN 0x2 /* VLDO20M_EN pin */ +#define S2MPG10_PCTRLSEL_LDO20M_SFR 0x3 /* LDO20M_SFR bit in LDO_CTRL1 register */ + /* Meter registers (type 0xa00) */ enum s2mpg10_meter_reg { S2MPG10_METER_CTRL1, @@ -407,6 +431,16 @@ enum s2mpg10_meter_reg { /* S2MPG10 regulator IDs */ enum s2mpg10_regulators { + S2MPG10_BUCK1, + S2MPG10_BUCK2, + S2MPG10_BUCK3, + S2MPG10_BUCK4, + S2MPG10_BUCK5, + S2MPG10_BUCK6, + S2MPG10_BUCK7, + S2MPG10_BUCK8, + S2MPG10_BUCK9, + S2MPG10_BUCK10, S2MPG10_LDO1, S2MPG10_LDO2, S2MPG10_LDO3, @@ -438,16 +472,6 @@ enum s2mpg10_regulators { S2MPG10_LDO29, S2MPG10_LDO30, S2MPG10_LDO31, - S2MPG10_BUCK1, - S2MPG10_BUCK2, - S2MPG10_BUCK3, - S2MPG10_BUCK4, - S2MPG10_BUCK5, - S2MPG10_BUCK6, - S2MPG10_BUCK7, - S2MPG10_BUCK8, - S2MPG10_BUCK9, - S2MPG10_BUCK10, S2MPG10_REGULATOR_MAX, }; diff --git a/include/linux/mfd/samsung/s2mpg11.h b/include/linux/mfd/samsung/s2mpg11.h new file mode 100644 index 000000000000..66daa3bafa6e --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg11.h @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Samsung Electronics + * Copyright 2020 Google Inc + * Copyright 2025 Linaro Ltd. + */ + +#ifndef __LINUX_MFD_S2MPG11_H +#define __LINUX_MFD_S2MPG11_H + +/* Common registers (type 0x000) */ +enum s2mpg11_common_reg { + S2MPG11_COMMON_CHIPID, + S2MPG11_COMMON_INT, + S2MPG11_COMMON_INT_MASK, + S2MPG11_COMMON_SPD_CTRL1 = 0x0a, + S2MPG11_COMMON_SPD_CTRL2, + S2MPG11_COMMON_SPD_CTRL3, + S2MPG11_COMMON_MON1SEL = 0x1a, + S2MPG11_COMMON_MON2SEL, + S2MPG11_COMMON_MONR, + S2MPG11_COMMON_DEBUG_CTRL1, + S2MPG11_COMMON_DEBUG_CTRL2, + S2MPG11_COMMON_DEBUG_CTRL3, + S2MPG11_COMMON_DEBUG_CTRL4, + S2MPG11_COMMON_DEBUG_CTRL5, + S2MPG11_COMMON_DEBUG_CTRL6, + S2MPG11_COMMON_TEST_MODE1, + S2MPG11_COMMON_SPD_DEBUG1, + S2MPG11_COMMON_SPD_DEBUG2, + S2MPG11_COMMON_SPD_DEBUG3, + S2MPG11_COMMON_SPD_DEBUG4, +}; + +/* For S2MPG11_COMMON_INT and S2MPG11_COMMON_INT_MASK */ +#define S2MPG11_COMMON_INT_SRC GENMASK(2, 0) +#define S2MPG11_COMMON_INT_SRC_PMIC BIT(0) + +/* PMIC registers (type 0x100) */ +enum s2mpg11_pmic_reg { + S2MPG11_PMIC_INT1, + S2MPG11_PMIC_INT2, + S2MPG11_PMIC_INT3, + S2MPG11_PMIC_INT4, + S2MPG11_PMIC_INT5, + S2MPG11_PMIC_INT6, + S2MPG11_PMIC_INT1M, + S2MPG11_PMIC_INT2M, + S2MPG11_PMIC_INT3M, + S2MPG11_PMIC_INT4M, + S2MPG11_PMIC_INT5M, + S2MPG11_PMIC_INT6M, + S2MPG11_PMIC_STATUS1, + S2MPG11_PMIC_OFFSRC, + S2MPG11_PMIC_COMMON_CTRL1, + S2MPG11_PMIC_COMMON_CTRL2, + S2MPG11_PMIC_COMMON_CTRL3, + S2MPG11_PMIC_MIMICKING_CTRL, + S2MPG11_PMIC_B1S_CTRL, + S2MPG11_PMIC_B1S_OUT1, + S2MPG11_PMIC_B1S_OUT2, + S2MPG11_PMIC_B2S_CTRL, + S2MPG11_PMIC_B2S_OUT1, + S2MPG11_PMIC_B2S_OUT2, + S2MPG11_PMIC_B3S_CTRL, + S2MPG11_PMIC_B3S_OUT1, + S2MPG11_PMIC_B3S_OUT2, + S2MPG11_PMIC_B4S_CTRL, + S2MPG11_PMIC_B4S_OUT, + S2MPG11_PMIC_B5S_CTRL, + S2MPG11_PMIC_B5S_OUT, + S2MPG11_PMIC_B6S_CTRL, + S2MPG11_PMIC_B6S_OUT1, + S2MPG11_PMIC_B6S_OUT2, + S2MPG11_PMIC_B7S_CTRL, + S2MPG11_PMIC_B7S_OUT1, + S2MPG11_PMIC_B7S_OUT2, + S2MPG11_PMIC_B8S_CTRL, + S2MPG11_PMIC_B8S_OUT1, + S2MPG11_PMIC_B8S_OUT2, + S2MPG11_PMIC_B9S_CTRL, + S2MPG11_PMIC_B9S_OUT1, + S2MPG11_PMIC_B9S_OUT2, + S2MPG11_PMIC_B10S_CTRL, + S2MPG11_PMIC_B10S_OUT, + S2MPG11_PMIC_BUCKD_CTRL, + S2MPG11_PMIC_BUCKD_OUT, + S2MPG11_PMIC_BUCKA_CTRL, + S2MPG11_PMIC_BUCKA_OUT, + S2MPG11_PMIC_BB_CTRL, + S2MPG11_PMIC_BB_OUT1, + S2MPG11_PMIC_BB_OUT2, + S2MPG11_PMIC_BUCK1S_USONIC, + S2MPG11_PMIC_BUCK2S_USONIC, + S2MPG11_PMIC_BUCK3S_USONIC, + S2MPG11_PMIC_BUCK4S_USONIC, + S2MPG11_PMIC_BUCK5S_USONIC, + S2MPG11_PMIC_BUCK6S_USONIC, + S2MPG11_PMIC_BUCK7S_USONIC, + S2MPG11_PMIC_BUCK8S_USONIC, + S2MPG11_PMIC_BUCK9S_USONIC, + S2MPG11_PMIC_BUCK10S_USONIC, + S2MPG11_PMIC_BUCKD_USONIC, + S2MPG11_PMIC_BUCKA_USONIC, + S2MPG11_PMIC_BB_USONIC, + S2MPG11_PMIC_L1S_CTRL1, + S2MPG11_PMIC_L1S_CTRL2, + S2MPG11_PMIC_L2S_CTRL1, + S2MPG11_PMIC_L2S_CTRL2, + S2MPG11_PMIC_L3S_CTRL, + S2MPG11_PMIC_L4S_CTRL, + S2MPG11_PMIC_L5S_CTRL, + S2MPG11_PMIC_L6S_CTRL, + S2MPG11_PMIC_L7S_CTRL, + S2MPG11_PMIC_L8S_CTRL, + S2MPG11_PMIC_L9S_CTRL, + S2MPG11_PMIC_L10S_CTRL, + S2MPG11_PMIC_L11S_CTRL, + S2MPG11_PMIC_L12S_CTRL, + S2MPG11_PMIC_L13S_CTRL, + S2MPG11_PMIC_L14S_CTRL, + S2MPG11_PMIC_L15S_CTRL, + S2MPG11_PMIC_LDO_CTRL1, + S2MPG11_PMIC_LDO_DSCH1, + S2MPG11_PMIC_LDO_DSCH2, + S2MPG11_PMIC_DVS_RAMP1, + S2MPG11_PMIC_DVS_RAMP2, + S2MPG11_PMIC_DVS_RAMP3, + S2MPG11_PMIC_DVS_RAMP4, + S2MPG11_PMIC_DVS_RAMP5, + S2MPG11_PMIC_DVS_RAMP6, + /* Nothing @ 0x5a */ + S2MPG11_PMIC_DVS_SYNC_CTRL1 = 0x5c, + S2MPG11_PMIC_DVS_SYNC_CTRL2, + S2MPG11_PMIC_OFF_CTRL1, + S2MPG11_PMIC_OFF_CTRL2, + S2MPG11_PMIC_OFF_CTRL3, + S2MPG11_PMIC_SEQ_CTRL1, + S2MPG11_PMIC_SEQ_CTRL2, + S2MPG11_PMIC_SEQ_CTRL3, + S2MPG11_PMIC_SEQ_CTRL4, + S2MPG11_PMIC_SEQ_CTRL5, + S2MPG11_PMIC_SEQ_CTRL6, + S2MPG11_PMIC_SEQ_CTRL7, + S2MPG11_PMIC_SEQ_CTRL8, + S2MPG11_PMIC_SEQ_CTRL9, + S2MPG11_PMIC_SEQ_CTRL10, + S2MPG11_PMIC_SEQ_CTRL11, + S2MPG11_PMIC_SEQ_CTRL12, + S2MPG11_PMIC_SEQ_CTRL13, + S2MPG11_PMIC_SEQ_CTRL14, + S2MPG11_PMIC_SEQ_CTRL15, + S2MPG11_PMIC_SEQ_CTRL16, + S2MPG11_PMIC_SEQ_CTRL17, + S2MPG11_PMIC_SEQ_CTRL18, + S2MPG11_PMIC_SEQ_CTRL19, + S2MPG11_PMIC_SEQ_CTRL20, + S2MPG11_PMIC_SEQ_CTRL21, + S2MPG11_PMIC_SEQ_CTRL22, + S2MPG11_PMIC_SEQ_CTRL23, + S2MPG11_PMIC_SEQ_CTRL24, + S2MPG11_PMIC_SEQ_CTRL25, + S2MPG11_PMIC_SEQ_CTRL26, + S2MPG11_PMIC_SEQ_CTRL27, + S2MPG11_PMIC_OFF_SEQ_CTRL1, + S2MPG11_PMIC_OFF_SEQ_CTRL2, + S2MPG11_PMIC_OFF_SEQ_CTRL3, + S2MPG11_PMIC_OFF_SEQ_CTRL4, + S2MPG11_PMIC_OFF_SEQ_CTRL5, + S2MPG11_PMIC_OFF_SEQ_CTRL6, + S2MPG11_PMIC_OFF_SEQ_CTRL7, + S2MPG11_PMIC_OFF_SEQ_CTRL8, + S2MPG11_PMIC_OFF_SEQ_CTRL9, + S2MPG11_PMIC_OFF_SEQ_CTRL10, + S2MPG11_PMIC_OFF_SEQ_CTRL11, + S2MPG11_PMIC_OFF_SEQ_CTRL12, + S2MPG11_PMIC_OFF_SEQ_CTRL13, + S2MPG11_PMIC_OFF_SEQ_CTRL14, + S2MPG11_PMIC_OFF_SEQ_CTRL15, + S2MPG11_PMIC_OFF_SEQ_CTRL16, + S2MPG11_PMIC_OFF_SEQ_CTRL17, + S2MPG11_PMIC_PCTRLSEL1, + S2MPG11_PMIC_PCTRLSEL2, + S2MPG11_PMIC_PCTRLSEL3, + S2MPG11_PMIC_PCTRLSEL4, + S2MPG11_PMIC_PCTRLSEL5, + S2MPG11_PMIC_PCTRLSEL6, + S2MPG11_PMIC_DCTRLSEL1, + S2MPG11_PMIC_DCTRLSEL2, + S2MPG11_PMIC_DCTRLSEL3, + S2MPG11_PMIC_DCTRLSEL4, + S2MPG11_PMIC_DCTRLSEL5, + S2MPG11_PMIC_GPIO_CTRL1, + S2MPG11_PMIC_GPIO_CTRL2, + S2MPG11_PMIC_GPIO_CTRL3, + S2MPG11_PMIC_GPIO_CTRL4, + S2MPG11_PMIC_GPIO_CTRL5, + S2MPG11_PMIC_GPIO_CTRL6, + S2MPG11_PMIC_GPIO_CTRL7, + S2MPG11_PMIC_B2S_OCP_WARN, + S2MPG11_PMIC_B2S_OCP_WARN_X, + S2MPG11_PMIC_B2S_OCP_WARN_Y, + S2MPG11_PMIC_B2S_OCP_WARN_Z, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_X, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z, + S2MPG11_PMIC_BUCK_OCP_EN1, + S2MPG11_PMIC_BUCK_OCP_EN2, + S2MPG11_PMIC_BUCK_OCP_PD_EN1, + S2MPG11_PMIC_BUCK_OCP_PD_EN2, + S2MPG11_PMIC_BUCK_OCP_CTRL1, + S2MPG11_PMIC_BUCK_OCP_CTRL2, + S2MPG11_PMIC_BUCK_OCP_CTRL3, + S2MPG11_PMIC_BUCK_OCP_CTRL4, + S2MPG11_PMIC_BUCK_OCP_CTRL5, + S2MPG11_PMIC_BUCK_OCP_CTRL6, + S2MPG11_PMIC_BUCK_OCP_CTRL7, + S2MPG11_PMIC_PIF_CTRL, + S2MPG11_PMIC_BUCK_HR_MODE1, + S2MPG11_PMIC_BUCK_HR_MODE2, + S2MPG11_PMIC_FAULTOUT_CTRL, + S2MPG11_PMIC_LDO_SENSE1, + S2MPG11_PMIC_LDO_SENSE2, +}; + +/* For S2MPG11_PMIC_PCTRLSELx */ +#define S2MPG11_PCTRLSEL_PWREN 0x1 /* PWREN pin */ +#define S2MPG11_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */ +#define S2MPG11_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */ +#define S2MPG11_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */ +#define S2MPG11_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */ +#define S2MPG11_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */ +#define S2MPG11_PCTRLSEL_G3D_EN 0x7 /* G3D_EN pin */ +#define S2MPG11_PCTRLSEL_G3D_EN2 0x8 /* G3D_EN & ~AP_ACTIVE_N pins */ +#define S2MPG11_PCTRLSEL_AOC_VDD 0x9 /* AOC_VDD pin */ +#define S2MPG11_PCTRLSEL_AOC_RET 0xa /* AOC_RET pin */ +#define S2MPG11_PCTRLSEL_UFS_EN 0xb /* UFS_EN pin */ +#define S2MPG11_PCTRLSEL_LDO13S_EN 0xc /* VLDO13S_EN pin */ + +/* Meter registers (type 0xa00) */ +enum s2mpg11_meter_reg { + S2MPG11_METER_CTRL1, + S2MPG11_METER_CTRL2, + S2MPG11_METER_CTRL3, + S2MPG11_METER_CTRL4, + S2MPG11_METER_CTRL5, + S2MPG11_METER_BUCKEN1, + S2MPG11_METER_BUCKEN2, + S2MPG11_METER_MUXSEL0, + S2MPG11_METER_MUXSEL1, + S2MPG11_METER_MUXSEL2, + S2MPG11_METER_MUXSEL3, + S2MPG11_METER_MUXSEL4, + S2MPG11_METER_MUXSEL5, + S2MPG11_METER_MUXSEL6, + S2MPG11_METER_MUXSEL7, + S2MPG11_METER_LPF_C0_0, + S2MPG11_METER_LPF_C0_1, + S2MPG11_METER_LPF_C0_2, + S2MPG11_METER_LPF_C0_3, + S2MPG11_METER_LPF_C0_4, + S2MPG11_METER_LPF_C0_5, + S2MPG11_METER_LPF_C0_6, + S2MPG11_METER_LPF_C0_7, + S2MPG11_METER_NTC_LPF_C0_0, + S2MPG11_METER_NTC_LPF_C0_1, + S2MPG11_METER_NTC_LPF_C0_2, + S2MPG11_METER_NTC_LPF_C0_3, + S2MPG11_METER_NTC_LPF_C0_4, + S2MPG11_METER_NTC_LPF_C0_5, + S2MPG11_METER_NTC_LPF_C0_6, + S2MPG11_METER_NTC_LPF_C0_7, + S2MPG11_METER_PWR_WARN0, + S2MPG11_METER_PWR_WARN1, + S2MPG11_METER_PWR_WARN2, + S2MPG11_METER_PWR_WARN3, + S2MPG11_METER_PWR_WARN4, + S2MPG11_METER_PWR_WARN5, + S2MPG11_METER_PWR_WARN6, + S2MPG11_METER_PWR_WARN7, + S2MPG11_METER_NTC_L_WARN0, + S2MPG11_METER_NTC_L_WARN1, + S2MPG11_METER_NTC_L_WARN2, + S2MPG11_METER_NTC_L_WARN3, + S2MPG11_METER_NTC_L_WARN4, + S2MPG11_METER_NTC_L_WARN5, + S2MPG11_METER_NTC_L_WARN6, + S2MPG11_METER_NTC_L_WARN7, + S2MPG11_METER_NTC_H_WARN0, + S2MPG11_METER_NTC_H_WARN1, + S2MPG11_METER_NTC_H_WARN2, + S2MPG11_METER_NTC_H_WARN3, + S2MPG11_METER_NTC_H_WARN4, + S2MPG11_METER_NTC_H_WARN5, + S2MPG11_METER_NTC_H_WARN6, + S2MPG11_METER_NTC_H_WARN7, + S2MPG11_METER_PWR_HYS1, + S2MPG11_METER_PWR_HYS2, + S2MPG11_METER_PWR_HYS3, + S2MPG11_METER_PWR_HYS4, + S2MPG11_METER_NTC_HYS1, + S2MPG11_METER_NTC_HYS2, + S2MPG11_METER_NTC_HYS3, + S2MPG11_METER_NTC_HYS4, + /* Nothing @ 0x3f */ + S2MPG11_METER_ACC_DATA_CH0_1 = 0x40, + S2MPG11_METER_ACC_DATA_CH0_2, + S2MPG11_METER_ACC_DATA_CH0_3, + S2MPG11_METER_ACC_DATA_CH0_4, + S2MPG11_METER_ACC_DATA_CH0_5, + S2MPG11_METER_ACC_DATA_CH0_6, + S2MPG11_METER_ACC_DATA_CH1_1, + S2MPG11_METER_ACC_DATA_CH1_2, + S2MPG11_METER_ACC_DATA_CH1_3, + S2MPG11_METER_ACC_DATA_CH1_4, + S2MPG11_METER_ACC_DATA_CH1_5, + S2MPG11_METER_ACC_DATA_CH1_6, + S2MPG11_METER_ACC_DATA_CH2_1, + S2MPG11_METER_ACC_DATA_CH2_2, + S2MPG11_METER_ACC_DATA_CH2_3, + S2MPG11_METER_ACC_DATA_CH2_4, + S2MPG11_METER_ACC_DATA_CH2_5, + S2MPG11_METER_ACC_DATA_CH2_6, + S2MPG11_METER_ACC_DATA_CH3_1, + S2MPG11_METER_ACC_DATA_CH3_2, + S2MPG11_METER_ACC_DATA_CH3_3, + S2MPG11_METER_ACC_DATA_CH3_4, + S2MPG11_METER_ACC_DATA_CH3_5, + S2MPG11_METER_ACC_DATA_CH3_6, + S2MPG11_METER_ACC_DATA_CH4_1, + S2MPG11_METER_ACC_DATA_CH4_2, + S2MPG11_METER_ACC_DATA_CH4_3, + S2MPG11_METER_ACC_DATA_CH4_4, + S2MPG11_METER_ACC_DATA_CH4_5, + S2MPG11_METER_ACC_DATA_CH4_6, + S2MPG11_METER_ACC_DATA_CH5_1, + S2MPG11_METER_ACC_DATA_CH5_2, + S2MPG11_METER_ACC_DATA_CH5_3, + S2MPG11_METER_ACC_DATA_CH5_4, + S2MPG11_METER_ACC_DATA_CH5_5, + S2MPG11_METER_ACC_DATA_CH5_6, + S2MPG11_METER_ACC_DATA_CH6_1, + S2MPG11_METER_ACC_DATA_CH6_2, + S2MPG11_METER_ACC_DATA_CH6_3, + S2MPG11_METER_ACC_DATA_CH6_4, + S2MPG11_METER_ACC_DATA_CH6_5, + S2MPG11_METER_ACC_DATA_CH6_6, + S2MPG11_METER_ACC_DATA_CH7_1, + S2MPG11_METER_ACC_DATA_CH7_2, + S2MPG11_METER_ACC_DATA_CH7_3, + S2MPG11_METER_ACC_DATA_CH7_4, + S2MPG11_METER_ACC_DATA_CH7_5, + S2MPG11_METER_ACC_DATA_CH7_6, + S2MPG11_METER_ACC_COUNT_1, + S2MPG11_METER_ACC_COUNT_2, + S2MPG11_METER_ACC_COUNT_3, + S2MPG11_METER_LPF_DATA_CH0_1, + S2MPG11_METER_LPF_DATA_CH0_2, + S2MPG11_METER_LPF_DATA_CH0_3, + S2MPG11_METER_LPF_DATA_CH1_1, + S2MPG11_METER_LPF_DATA_CH1_2, + S2MPG11_METER_LPF_DATA_CH1_3, + S2MPG11_METER_LPF_DATA_CH2_1, + S2MPG11_METER_LPF_DATA_CH2_2, + S2MPG11_METER_LPF_DATA_CH2_3, + S2MPG11_METER_LPF_DATA_CH3_1, + S2MPG11_METER_LPF_DATA_CH3_2, + S2MPG11_METER_LPF_DATA_CH3_3, + S2MPG11_METER_LPF_DATA_CH4_1, + S2MPG11_METER_LPF_DATA_CH4_2, + S2MPG11_METER_LPF_DATA_CH4_3, + S2MPG11_METER_LPF_DATA_CH5_1, + S2MPG11_METER_LPF_DATA_CH5_2, + S2MPG11_METER_LPF_DATA_CH5_3, + S2MPG11_METER_LPF_DATA_CH6_1, + S2MPG11_METER_LPF_DATA_CH6_2, + S2MPG11_METER_LPF_DATA_CH6_3, + S2MPG11_METER_LPF_DATA_CH7_1, + S2MPG11_METER_LPF_DATA_CH7_2, + S2MPG11_METER_LPF_DATA_CH7_3, + /* Nothing @ 0x8b 0x8c */ + S2MPG11_METER_LPF_DATA_NTC0_1 = 0x8d, + S2MPG11_METER_LPF_DATA_NTC0_2, + S2MPG11_METER_LPF_DATA_NTC1_1, + S2MPG11_METER_LPF_DATA_NTC1_2, + S2MPG11_METER_LPF_DATA_NTC2_1, + S2MPG11_METER_LPF_DATA_NTC2_2, + S2MPG11_METER_LPF_DATA_NTC3_1, + S2MPG11_METER_LPF_DATA_NTC3_2, + S2MPG11_METER_LPF_DATA_NTC4_1, + S2MPG11_METER_LPF_DATA_NTC4_2, + S2MPG11_METER_LPF_DATA_NTC5_1, + S2MPG11_METER_LPF_DATA_NTC5_2, + S2MPG11_METER_LPF_DATA_NTC6_1, + S2MPG11_METER_LPF_DATA_NTC6_2, + S2MPG11_METER_LPF_DATA_NTC7_1, + S2MPG11_METER_LPF_DATA_NTC7_2, +}; + +/* S2MPG11 regulator IDs */ +enum s2mpg11_regulators { + S2MPG11_BUCKBOOST, + S2MPG11_BUCK1, + S2MPG11_BUCK2, + S2MPG11_BUCK3, + S2MPG11_BUCK4, + S2MPG11_BUCK5, + S2MPG11_BUCK6, + S2MPG11_BUCK7, + S2MPG11_BUCK8, + S2MPG11_BUCK9, + S2MPG11_BUCK10, + S2MPG11_BUCKD, + S2MPG11_BUCKA, + S2MPG11_LDO1, + S2MPG11_LDO2, + S2MPG11_LDO3, + S2MPG11_LDO4, + S2MPG11_LDO5, + S2MPG11_LDO6, + S2MPG11_LDO7, + S2MPG11_LDO8, + S2MPG11_LDO9, + S2MPG11_LDO10, + S2MPG11_LDO11, + S2MPG11_LDO12, + S2MPG11_LDO13, + S2MPG11_LDO14, + S2MPG11_LDO15, + S2MPG11_REGULATOR_MAX, +}; + +#endif /* __LINUX_MFD_S2MPG11_H */ diff --git a/include/linux/mfd/tps6105x.h b/include/linux/mfd/tps6105x.h index b1313411ef09..94e699896240 100644 --- a/include/linux/mfd/tps6105x.h +++ b/include/linux/mfd/tps6105x.h @@ -53,7 +53,7 @@ /** * enum tps6105x_mode - desired mode for the TPS6105x * @TPS6105X_MODE_SHUTDOWN: this instance is inactive, not used for anything - * @TPS61905X_MODE_TORCH: this instance is used as a LED, usually a while + * @TPS6105X_MODE_TORCH: this instance is used as a LED, usually a while * LED, for example as backlight or flashlight. If this is set, the * TPS6105X will register to the LED framework * @TPS6105X_MODE_TORCH_FLASH: this instance is used as a flashgun, usually @@ -82,7 +82,8 @@ struct tps6105x_platform_data { /** * struct tps6105x - state holder for the TPS6105x drivers - * @i2c_client: corresponding I2C client + * @pdata: associated platform data + * @client: corresponding I2C client * @regulator: regulator device if used in voltage mode * @regmap: used for i2c communcation on accessing registers */ diff --git a/include/linux/mfd/tps65219.h b/include/linux/mfd/tps65219.h index 55234e771ba7..3abf937191d0 100644 --- a/include/linux/mfd/tps65219.h +++ b/include/linux/mfd/tps65219.h @@ -149,6 +149,8 @@ enum pmic_id { #define TPS65215_ENABLE_LDO2_EN_MASK BIT(5) #define TPS65214_ENABLE_LDO1_EN_MASK BIT(5) #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) +/* Register Unlock */ +#define TPS65214_LOCK_ACCESS_CMD 0x5a /* power ON-OFF sequence slot */ #define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) #define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4) diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h index 5f70d3b5d1b1..097ef4dfcdac 100644 --- a/include/linux/mfd/wm8350/core.h +++ b/include/linux/mfd/wm8350/core.h @@ -667,7 +667,7 @@ static inline int wm8350_register_irq(struct wm8350 *wm8350, int irq, return -ENODEV; return request_threaded_irq(irq + wm8350->irq_base, NULL, - handler, flags, name, data); + handler, flags | IRQF_ONESHOT, name, data); } static inline void wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data) |