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Diffstat (limited to 'include/linux/mlx5')
-rw-r--r--include/linux/mlx5/device.h10
-rw-r--r--include/linux/mlx5/driver.h4
-rw-r--r--include/linux/mlx5/fs.h10
-rw-r--r--include/linux/mlx5/lag.h21
-rw-r--r--include/linux/mlx5/mlx5_ifc.h64
5 files changed, 93 insertions, 16 deletions
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index b37fe39cef27..07a25f264292 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -293,6 +293,7 @@ enum {
MLX5_UMR_INLINE = (1 << 7),
};
+#define MLX5_UMR_ALIGN (2048)
#define MLX5_UMR_FLEX_ALIGNMENT 0x40
#define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt))
#define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm))
@@ -1259,6 +1260,7 @@ enum mlx5_cap_type {
MLX5_CAP_PORT_SELECTION = 0x25,
MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
MLX5_CAP_ADV_RDMA = 0x28,
+ MLX5_CAP_TLP_EMULATION = 0x2a,
/* NUM OF CAP Types */
MLX5_CAP_NUM
};
@@ -1481,6 +1483,14 @@ enum mlx5_qcam_feature_groups {
MLX5_GET64(virtio_emulation_cap, \
(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
+#define MLX5_CAP_DEV_TLP_EMULATION(mdev, cap)\
+ MLX5_GET(tlp_dev_emu_capabilities, \
+ (mdev)->caps.hca[MLX5_CAP_TLP_EMULATION]->cur, cap)
+
+#define MLX5_CAP64_DEV_TLP_EMULATION(mdev, cap)\
+ MLX5_GET64(tlp_dev_emu_capabilities, \
+ (mdev)->caps.hca[MLX5_CAP_TLP_EMULATION]->cur, cap)
+
#define MLX5_CAP_IPSEC(mdev, cap)\
MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 04dcd09f7517..e1ded9cf0f70 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -550,7 +550,7 @@ struct mlx5_debugfs_entries {
};
enum mlx5_func_type {
- MLX5_PF,
+ MLX5_SELF,
MLX5_VF,
MLX5_SF,
MLX5_HOST_PF,
@@ -755,7 +755,6 @@ struct mlx5_core_dev {
} caps;
struct mlx5_timeouts *timeouts;
u64 sys_image_guid;
- phys_addr_t iseg_base;
struct mlx5_init_seg __iomem *iseg;
phys_addr_t bar_addr;
enum mlx5_device_state state;
@@ -798,6 +797,7 @@ struct mlx5_core_dev {
enum mlx5_wc_state wc_state;
/* sync write combining state */
struct mutex wc_state_lock;
+ struct devlink *shd;
};
struct mlx5_db {
diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h
index 9cadb1d5e6df..d8f3b7ef319e 100644
--- a/include/linux/mlx5/fs.h
+++ b/include/linux/mlx5/fs.h
@@ -55,6 +55,7 @@ enum mlx5_flow_destination_type {
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM,
MLX5_FLOW_DESTINATION_TYPE_RANGE,
MLX5_FLOW_DESTINATION_TYPE_TABLE_TYPE,
+ MLX5_FLOW_DESTINATION_TYPE_VHCA_RX,
};
enum {
@@ -190,6 +191,9 @@ struct mlx5_flow_destination {
struct mlx5_flow_table *ft;
struct mlx5_fc *counter;
struct {
+ u16 id;
+ } vhca;
+ struct {
u16 num;
u16 vhca_id;
struct mlx5_pkt_reformat *pkt_reformat;
@@ -248,9 +252,9 @@ mlx5_create_auto_grouped_flow_table(struct mlx5_flow_namespace *ns,
struct mlx5_flow_table *
mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
struct mlx5_flow_table_attr *ft_attr, u16 vport);
-struct mlx5_flow_table *mlx5_create_lag_demux_flow_table(
- struct mlx5_flow_namespace *ns,
- int prio, u32 level);
+struct mlx5_flow_table *
+mlx5_create_lag_demux_flow_table(struct mlx5_flow_namespace *ns,
+ struct mlx5_flow_table_attr *ft_attr);
int mlx5_destroy_flow_table(struct mlx5_flow_table *ft);
/* inbox should be set with the following values:
diff --git a/include/linux/mlx5/lag.h b/include/linux/mlx5/lag.h
new file mode 100644
index 000000000000..ab9f754664e5
--- /dev/null
+++ b/include/linux/mlx5/lag.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
+/* Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
+
+#ifndef __MLX5_LAG_API_H__
+#define __MLX5_LAG_API_H__
+
+#include <linux/types.h>
+
+struct mlx5_core_dev;
+struct mlx5_flow_table;
+struct mlx5_flow_table_attr;
+
+int mlx5_lag_demux_init(struct mlx5_core_dev *dev,
+ struct mlx5_flow_table_attr *ft_attr);
+void mlx5_lag_demux_cleanup(struct mlx5_core_dev *dev);
+int mlx5_lag_demux_rule_add(struct mlx5_core_dev *dev, u16 vport_num,
+ int vport_index);
+void mlx5_lag_demux_rule_del(struct mlx5_core_dev *dev, int vport_index);
+int mlx5_lag_get_dev_seq(struct mlx5_core_dev *dev);
+
+#endif /* __MLX5_LAG_API_H__ */
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 775cb0c56865..007f5138db2b 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -469,7 +469,8 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
u8 table_miss_action_domain[0x1];
u8 termination_table[0x1];
u8 reformat_and_fwd_to_table[0x1];
- u8 reserved_at_1a[0x2];
+ u8 forward_vhca_rx[0x1];
+ u8 reserved_at_1b[0x1];
u8 ipsec_encrypt[0x1];
u8 ipsec_decrypt[0x1];
u8 sw_owner_v2[0x1];
@@ -1389,6 +1390,26 @@ struct mlx5_ifc_virtio_emulation_cap_bits {
u8 reserved_at_1c0[0x640];
};
+struct mlx5_ifc_tlp_dev_emu_capabilities_bits {
+ u8 reserved_at_0[0x20];
+
+ u8 reserved_at_20[0x13];
+ u8 log_tlp_rsp_gw_page_stride[0x5];
+ u8 reserved_at_38[0x8];
+
+ u8 reserved_at_40[0xc0];
+
+ u8 reserved_at_100[0xc];
+ u8 tlp_rsp_gw_num_pages[0x4];
+ u8 reserved_at_110[0x10];
+
+ u8 reserved_at_120[0xa0];
+
+ u8 tlp_rsp_gw_pages_bar_offset[0x40];
+
+ u8 reserved_at_200[0x600];
+};
+
enum {
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
@@ -1633,6 +1654,11 @@ enum {
MLX5_STEERING_FORMAT_CONNECTX_8 = 3,
};
+enum {
+ MLX5_ID_MODE_FUNCTION_INDEX = 0,
+ MLX5_ID_MODE_FUNCTION_VHCA_ID = 1,
+};
+
struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_0[0x6];
u8 page_request_disable[0x1];
@@ -1895,7 +1921,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_280[0x10];
u8 max_wqe_sz_sq[0x10];
- u8 reserved_at_2a0[0x7];
+ u8 icm_mng_function_id_mode[0x1];
+ u8 reserved_at_2a1[0x6];
u8 mkey_pcie_tph[0x1];
u8 reserved_at_2a8[0x1];
u8 tis_tir_td_order[0x1];
@@ -1947,7 +1974,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_360[0x3];
u8 log_max_rq[0x5];
- u8 reserved_at_368[0x3];
+ u8 ft_alias_sw_vhca_id[0x1];
+ u8 reserved_at_369[0x2];
u8 log_max_sq[0x5];
u8 reserved_at_370[0x3];
u8 log_max_tir[0x5];
@@ -1961,7 +1989,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 log_max_rqt[0x5];
u8 reserved_at_390[0x3];
u8 log_max_rqt_size[0x5];
- u8 reserved_at_398[0x1];
+ u8 tlp_device_emulation_manager[0x1];
u8 vnic_env_cnt_bar_uar_access[0x1];
u8 vnic_env_cnt_odp_page_fault[0x1];
u8 log_max_tis_per_sq[0x5];
@@ -1992,12 +2020,14 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 disable_local_lb_mc[0x1];
u8 log_min_hairpin_wq_data_sz[0x5];
u8 reserved_at_3e8[0x1];
- u8 silent_mode[0x1];
+ u8 silent_mode_set[0x1];
u8 vhca_state[0x1];
u8 log_max_vlan_list[0x5];
u8 reserved_at_3f0[0x3];
u8 log_max_current_mc_list[0x5];
- u8 reserved_at_3f8[0x3];
+ u8 reserved_at_3f8[0x1];
+ u8 silent_mode_query[0x1];
+ u8 reserved_at_3fa[0x1];
u8 log_max_current_uc_list[0x5];
u8 general_obj_types[0x40];
@@ -2259,6 +2289,7 @@ enum mlx5_ifc_flow_destination_type {
MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
+ MLX5_IFC_FLOW_DESTINATION_TYPE_VHCA_RX = 0x4,
MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA,
@@ -3830,6 +3861,7 @@ union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_tls_cap_bits tls_cap;
struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
+ struct mlx5_ifc_tlp_dev_emu_capabilities_bits tlp_dev_emu_capabilities;
struct mlx5_ifc_macsec_cap_bits macsec_cap;
struct mlx5_ifc_crypto_cap_bits crypto_cap;
struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
@@ -6244,7 +6276,9 @@ struct mlx5_ifc_query_l2_table_entry_out_bits {
u8 reserved_at_40[0xa0];
- u8 reserved_at_e0[0x13];
+ u8 reserved_at_e0[0x11];
+ u8 silent_mode[0x1];
+ u8 reserved_at_f2[0x1];
u8 vlan_valid[0x1];
u8 vlan[0xc];
@@ -6260,7 +6294,10 @@ struct mlx5_ifc_query_l2_table_entry_in_bits {
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
- u8 reserved_at_40[0x60];
+ u8 reserved_at_40[0x40];
+
+ u8 silent_mode_query[0x1];
+ u8 reserved_at_81[0x1f];
u8 reserved_at_a0[0x8];
u8 table_index[0x18];
@@ -6927,7 +6964,9 @@ struct mlx5_ifc_create_match_definer_out_bits {
struct mlx5_ifc_alias_context_bits {
u8 vhca_id_to_be_accessed[0x10];
- u8 reserved_at_10[0xd];
+ u8 reserved_at_10[0xb];
+ u8 vhca_id_type[0x1];
+ u8 reserved_at_1c[0x1];
u8 status[0x3];
u8 object_id_to_be_accessed[0x20];
u8 reserved_at_40[0x40];
@@ -10824,7 +10863,9 @@ struct mlx5_ifc_pcam_enhanced_features_bits {
u8 fec_200G_per_lane_in_pplm[0x1];
u8 reserved_at_1e[0x2a];
u8 fec_100G_per_lane_in_pplm[0x1];
- u8 reserved_at_49[0xa];
+ u8 reserved_at_49[0x2];
+ u8 shp_pbmc_pbsr_support[0x1];
+ u8 reserved_at_4c[0x7];
u8 buffer_ownership[0x1];
u8 resereved_at_54[0x14];
u8 fec_50G_per_lane_in_pplm[0x1];
@@ -12069,8 +12110,9 @@ struct mlx5_ifc_pbmc_reg_bits {
u8 port_buffer_size[0x10];
struct mlx5_ifc_bufferx_reg_bits buffer[10];
+ struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool;
- u8 reserved_at_2e0[0x80];
+ u8 reserved_at_320[0x40];
};
struct mlx5_ifc_sbpr_reg_bits {
generated by cgit v1.2.3 (git 2.0.4) at 2026-05-08 12:26:24 +0000