diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/cxl/cxl.h | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 802b143de83d..1c04a7823f64 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -130,9 +130,30 @@ struct cxl_dpa_perf { int qos_class; }; +/* + * Partitions share one flat DPA space in a fixed order: + * + * DPA 0 end + * +---------------+---------------+---------------------------+ + * | ram | pmem | dynamic_ram_1 | + * +---------------+---------------+---------------------------+ + * part[0] part[1] part[2] + * + * The static ram and pmem partition order is mandated by CXL r4.0 + * 8.2.10.9.2.1 "Get Partition Info" (opcode 4100h), Table 8-310: volatile + * capacity starts at DPA 0 and persistent capacity starts at the DPA + * immediately following it. A dynamic partition has no such + * requirement -- 8.2.10.9.9.1 "Get Dynamic Capacity Configuration" + * (opcode 4800h), Table 8-347, only requires the DC Region Base to be + * 256MB aligned -- but Linux follows that precedent and requires it to + * start at the DPA immediately following static capacity: after pmem, + * after ram on a device with no pmem, or at DPA 0 on a device with no + * static capacity at all. cxl_configure_dcd() enforces it. + */ enum cxl_partition_mode { CXL_PARTMODE_RAM, CXL_PARTMODE_PMEM, + CXL_PARTMODE_DYNAMIC_RAM, }; /** @@ -140,14 +161,20 @@ enum cxl_partition_mode { * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res) * @perf: performance attributes of the partition from CDAT * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic... + * @handle: DSMAS handle that represents this partition + * @shareable: Is the partition shareable (from its CDAT DSMAS entry) + * @read_only: Is the partition read-only (from its CDAT DSMAS entry) */ struct cxl_dpa_partition { struct resource res; struct cxl_dpa_perf perf; enum cxl_partition_mode mode; + u8 handle; + bool shareable; + bool read_only; }; -#define CXL_NR_PARTITIONS_MAX 2 +#define CXL_NR_PARTITIONS_MAX 3 /** * struct cxl_dev_state - The driver device state |