diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/drm/bridge/dw_hdmi.h | 26 | ||||
| -rw-r--r-- | include/drm/drm_bridge.h | 3 | ||||
| -rw-r--r-- | include/drm/drm_dp_helper.h | 8 | ||||
| -rw-r--r-- | include/drm/drm_edid.h | 6 | ||||
| -rw-r--r-- | include/drm/drm_mipi_dbi.h | 5 | ||||
| -rw-r--r-- | include/uapi/drm/drm_fourcc.h | 34 |
6 files changed, 66 insertions, 16 deletions
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index 0b34a12c4a1c..ea34ca146b82 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -8,7 +8,7 @@ #include <sound/hdmi-codec.h> -struct drm_connector; +struct drm_display_info; struct drm_display_mode; struct drm_encoder; struct dw_hdmi; @@ -114,7 +114,8 @@ struct dw_hdmi_phy_config { struct dw_hdmi_phy_ops { int (*init)(struct dw_hdmi *hdmi, void *data, - struct drm_display_mode *mode); + const struct drm_display_info *display, + const struct drm_display_mode *mode); void (*disable)(struct dw_hdmi *hdmi, void *data); enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); void (*update_hpd)(struct dw_hdmi *hdmi, void *data, @@ -124,13 +125,22 @@ struct dw_hdmi_phy_ops { struct dw_hdmi_plat_data { struct regmap *regm; - enum drm_mode_status (*mode_valid)(struct drm_connector *connector, - const struct drm_display_mode *mode); - unsigned long input_bus_format; + unsigned long input_bus_encoding; bool use_drm_infoframe; bool ycbcr_420_allowed; + /* + * Private data passed to all the .mode_valid() and .configure_phy() + * callback functions. + */ + void *priv_data; + + /* Platform-specific mode validation (optional). */ + enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *info, + const struct drm_display_mode *mode); + /* Vendor PHY support */ const struct dw_hdmi_phy_ops *phy_ops; const char *phy_name; @@ -141,8 +151,7 @@ struct dw_hdmi_plat_data { const struct dw_hdmi_mpll_config *mpll_cfg; const struct dw_hdmi_curr_ctrl *cur_ctr; const struct dw_hdmi_phy_config *phy_config; - int (*configure_phy)(struct dw_hdmi *hdmi, - const struct dw_hdmi_plat_data *pdata, + int (*configure_phy)(struct dw_hdmi *hdmi, void *data, unsigned long mpixelclock); }; @@ -166,7 +175,8 @@ void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status); void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); -void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); +void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, + const struct drm_display_info *display); /* PHY configuration */ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h index ea2aa5ebae34..e3d7f36d8c39 100644 --- a/include/drm/drm_bridge.h +++ b/include/drm/drm_bridge.h @@ -35,6 +35,7 @@ struct drm_bridge; struct drm_bridge_timings; struct drm_connector; +struct drm_display_info; struct drm_panel; struct edid; struct i2c_adapter; @@ -112,6 +113,7 @@ struct drm_bridge_funcs { * drm_mode_status Enum */ enum drm_mode_status (*mode_valid)(struct drm_bridge *bridge, + const struct drm_display_info *info, const struct drm_display_mode *mode); /** @@ -836,6 +838,7 @@ bool drm_bridge_chain_mode_fixup(struct drm_bridge *bridge, struct drm_display_mode *adjusted_mode); enum drm_mode_status drm_bridge_chain_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, const struct drm_display_mode *mode); void drm_bridge_chain_disable(struct drm_bridge *bridge); void drm_bridge_chain_post_disable(struct drm_bridge *bridge); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1165ec105638..e47dc22ebf50 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) DP_ALTERNATE_SCRAMBLER_RESET_CAP; } +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + /* * DisplayPort AUX channel */ diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 34b15e3d070c..43254319ab19 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -361,11 +361,11 @@ drm_load_edid_firmware(struct drm_connector *connector) int drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, - struct drm_connector *connector, + const struct drm_connector *connector, const struct drm_display_mode *mode); int drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, - struct drm_connector *connector, + const struct drm_connector *connector, const struct drm_display_mode *mode); void @@ -378,7 +378,7 @@ drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, void drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, - struct drm_connector *connector, + const struct drm_connector *connector, const struct drm_display_mode *mode, enum hdmi_quantization_range rgb_quant_range); diff --git a/include/drm/drm_mipi_dbi.h b/include/drm/drm_mipi_dbi.h index 4d0e49c0ed2c..c2827ceaba0d 100644 --- a/include/drm/drm_mipi_dbi.h +++ b/include/drm/drm_mipi_dbi.h @@ -95,11 +95,6 @@ struct mipi_dbi_dev { struct drm_display_mode mode; /** - * @enabled: Pipeline is enabled - */ - bool enabled; - - /** * @tx_buf: Buffer used for transfer (copy clip rect area) */ u16 *tx_buf; diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 490143500a50..993c1b342315 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -236,6 +236,12 @@ extern "C" { #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +/* + * 2 plane YCbCr + * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian + * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian + */ +#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ /* * 2 plane YCbCr MSB aligned @@ -265,6 +271,22 @@ extern "C" { */ #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ +/* 3 plane non-subsampled (444) YCbCr + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cb plane, [15:0] Cb:x [10:6] little endian + * index 2: Cr plane, [15:0] Cr:x [10:6] little endian + */ +#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') + +/* 3 plane non-subsampled (444) YCrCb + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cr plane, [15:0] Cr:x [10:6] little endian + * index 2: Cb plane, [15:0] Cb:x [10:6] little endian + */ +#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y @@ -892,6 +914,18 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +/* AFBC uncompressed storage mode + * + * Indicates that the buffer is using AFBC uncompressed storage mode. + * In this mode all superblock payloads in the buffer use the uncompressed + * storage mode, which is usually only used for data which cannot be compressed. + * The buffer layout is the same as for AFBC buffers without USM set, this only + * affects the storage mode of the individual superblocks. Note that even a + * buffer without USM set may use uncompressed storage mode for some or all + * superblocks, USM just guarantees it for all. + */ +#define AFBC_FORMAT_MOD_USM (1ULL << 12) + /* * Arm 16x16 Block U-Interleaved modifier * |