linux-toradex.git - Linux kernel for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2019-07-08	Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...	Linus Torvalds
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner
2019-06-17	arm64/mm: Correct the cache line size warning with non coherent device	Masayoshi Mizuma
2019-06-04	arm64: cacheinfo: Update cache_line_size detected from DT or PPTT	Shaokun Zhang
2019-01-16	kasan, arm64: remove redundant ARCH_SLAB_MINALIGN define	Andrey Konovalov
2019-01-08	kasan, arm64: use ARCH_SLAB_MINALIGN instead of manual aligning	Andrey Konovalov
2018-10-16	arm64: cpufeature: Fix handling of CTR_EL0.IDC field	Suzuki K Poulose
2018-07-05	arm64: Fix mismatched cache line size detection	Suzuki K Poulose
2018-05-15	arm64: Increase ARCH_DMA_MINALIGN to 128	Catalin Marinas
2018-05-11	Revert "arm64: Increase the max granular size"	Catalin Marinas
2018-03-27	Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"	Will Deacon
2018-03-09	arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC	Shanker Donthineni
2018-03-06	arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)	Catalin Marinas
2017-03-20	arm64: cache: Identify VPIPT I-caches	Will Deacon
2017-03-20	arm64: cache: Merge cachetype.h into cache.h	Will Deacon
2015-10-28	arm64: Increase the max granular size	Tirumalesh Chalamarla
2014-12-03	arm64: Implement support for read-mostly sections	Jungseok Lee
2014-05-09	arm64: Implement cache_line_size() based on CTR_EL0.CWG	Catalin Marinas
2012-09-17	arm64: Cache maintenance routines	Catalin Marinas