| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-03-31 | MIPS: Fix gigaton of warning building with microMIPS. | Ralf Baechle |
| 2014-03-26 | MIPS: asm: r4kcache: Add EVA cache flushing functions | Leonid Yegoshin |
| 2014-03-26 | MIPS: asm: r4kcache: Add protected cache operation for EVA | Leonid Yegoshin |
| 2014-03-26 | MIPS: asm: r4kcache: Build flushing code for instruction cache | Leonid Yegoshin |
| 2014-01-15 | MIPS: fix blast_icache32 on loongson2 | Aaro Koskinen |
| 2014-01-15 | MIPS: fix case mismatch in local_r4k_flush_icache_range() | Huacai Chen |
| 2013-10-29 | MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips. | Ralf Baechle |
| 2013-02-01 | MIPS: Whitespace cleanup. | Ralf Baechle |
| 2011-04-06 | update David Miller's old email address | Justin P. Mattock |
| 2009-06-17 | MIPS: Support 64-byte D-cache line size | Kevin Cernekee |
| 2008-10-11 | MIPS: Move headfiles to new location below arch/mips/include | Ralf Baechle |
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index : linux-toradex.git | |
| Linux kernel for Apalis and Colibri modules | Toradex |
| summaryrefslogtreecommitdiff |