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2026-01-28Merge tag 'riscv-dt-for-v6.20' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.20 (or v7.0) Anlogic: Minor change to the extension information, to add the "b" extension that's a catch-all for 3 of the extensions already in the dts. Starfive: Append the jh7110 compatible to jh7110s devicetrees, as that will enable OpenSBI etc to run without adding support for this minor variant. The "s" device differs from the non "s" device only in thermal limits and voltage/frequency characteristics. Microchip: Redo the mpfs clock setup yet again, to something approaching correct. The original binding conjured up for the platform was wildly inaccurate, and even with the original improvements, a bigger change to using syscons was required to support several peripherals that also inhabit the memory regions that the clocks lie in. The damage to the dts isn't that bad in the end, and of course the whole thing has been done in a backwards compatible manner, with the code changes being merged a cycle or two ago in the kernel and like a year ago in U-Boot (the only other user that I am aware of). Generic: Additions to extensions.yaml, mainly for things in the "rva23" profile that appear for the first time on the Spacemit K3 SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: anlogic: dr1v90: Add "b" ISA extension dt-bindings: riscv: extensions: Drop unnecessary select schema dt-bindings: riscv: Add Sha and its comprised extensions dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm dt-bindings: riscv: Add B ISA extension description dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board riscv: dts: microchip: convert clock and reset to use syscon riscv: dts: microchip: fix mailbox description Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28Merge tag 'sunxi-dt-for-6.20' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt Allwinner device tree changes for 6.20 Not many changes this cycle. - The A523 family of SoCs gained support for SPI controllers. - Some cleanup of old ARM device tree files to fix DT binding validation errors. - D1 and A100 SoCs gained support for their LED controller. This was from a couple years ago. The driver made it in, but the DT patches were missed. - D1 and T113 SoCs gained support for the internal thermal sensor. * tag 'sunxi-dt-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: d1: Add CPU thermal sensor and zone ARM: dts: allwinner: Replace status "failed" with "fail" riscv: dts: allwinner: d1: Add RGB LEDs to boards riscv: dts: allwinner: d1: Add LED controller node arm64: dts: allwinner: a100: Add LED controller node ARM: dts: allwinner: sun5i-a13-utoo-p66: delete "power-gpios" property arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash arm64: dts: allwinner: sun55i: Add SPI controllers Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28Merge tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux ↵Arnd Bergmann
into soc/dt RISC-V SpacemiT DT changes for 6.20 - Disable Ethernet PHY auto sleep mode - Add pinctrl IO power support - Add K3 Pico-ITX board - Add support for K3 SoC - Add DWC USB support - Add reset for eMMC(sdhci)/I2C - Add PCIe support - Support PMIC for Jupiter board * tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi riscv: dts: spacemit: pinctrl: update register and IO power riscv: dts: spacemit: add K3 Pico-ITX board support riscv: dts: spacemit: add initial support for K3 SoC dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC dt-bindings: interrupt-controller: add SpacemiT K3 APLIC dt-bindings: timer: add SpacemiT K3 CLINT dt-bindings: riscv: add SpacemiT X100 CPU compatible riscv: dts: spacemit: k1: Add "b" ISA extension riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3 riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1 riscv: dts: spacemit: Add USB2 PHY node for K1 riscv: dts: spacemit: sdhci: add reset support riscv: dts: spacemit: add reset property riscv: dts: spacemit: PCIe and PHY-related updates riscv: dts: spacemit: Add a PCIe regulator riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28Merge tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux ↵Arnd Bergmann
into soc/dt RISC-V/Sophgo Devicetrees for v6.20 Sophgo: For CV18xx serials: Update RX/TX FIFO size to fix the USB transfer issue. For SG2042: Optimize the DTS file format, including moving PLIC/CLINT nodes into cpu dtsi and sorting peripheral nodes by address. In addition, we also enable RTC for Pioneerbox. For SG2044: Add "b" ISA extension to fix dtbs_check warnings. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux: riscv: dts: sophgo: sg2044: Add "b" ISA extension riscv: dts: sophgo: fix the node order of SG2042 peripheral riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V Pioneer riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-22riscv: dts: allwinner: d1: Add CPU thermal sensor and zoneAlex Studer
The sun20i THS (built in CPU thermal sensor) is supported in code, but was never added to the device tree. So, add it to the device tree, along with a thermal zone for the CPU. Signed-off-by: Alex Studer <alex@studer.dev> Changes since v1: - Move include before defines in sun20i-d1s.dtsi - Fix register size for thermal-sensor@2009400 - Move thermal-sensor@2009400 in SoC to match register address sorting - Add thermal-zone for sun8i-t113s.dtsi and fix missing cooling-cells Link: https://lore.kernel.org/r/20250218020629.1476126-1-alex@studer.dev Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li> Link: https://patch.msgid.link/20260113182951.1059690-1-lukas.schmid@netcube.li Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-01-21riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePiChukun Pan
On the SpacemiT K1 platform, the MAC can't read statistics when the PHY clock stops. Disable Link Down Power Saving Mode for the YT8531C PHY on OrangePi R2S and RV2 boards to avoid reading statistics timeout logs. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260120100001.1285624-2-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20riscv: dts: spacemit: pinctrl: update register and IO powerTroy Mitchell
Change the size of the reg register to 0x1000 to match the hardware. This register range covers the IO power domain's register addresses. The IO power domain registers are protected. In order to access the protected IO power domain registers, a valid unlock sequence must be performed by writing the required keys to the AIB Secure Access Register (ASAR). The ASAR register resides within the APBC register address space. A corresponding syscon property `spacemit,apbc` is added to allow the pinctrl driver to access this register. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Acked-by: Linus Walleij <linusw@kernel.org> Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20riscv: dts: spacemit: add K3 Pico-ITX board supportGuodong Xu
K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT K3 SoC. This minimal device tree enables booting into a serial console with UART output. Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20riscv: dts: spacemit: add initial support for K3 SoCGuodong Xu
SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. Add nodes of uarts, timer and interrupt-controllers. Also add M-mode APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware topology and ready for potential firmware usage. Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20riscv: dts: spacemit: k1: Add "b" ISA extensionGuodong Xu
"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update k1.dtsi to conform to this rule. Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-20riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3Ze Huang
Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the Banana Pi F3 board. The board utilizes a VLI VL817 hub, which requires two separate power supplies: one VBUS and one for hub itself. Add two GPIO-controlled fixed-regulators to manage this. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ze Huang <huang.ze@linux.dev> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-20riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1Ze Huang
Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC. The controller resides on the 'storage-bus' and uses its DMA translations. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ze Huang <huang.ze@linux.dev> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-20riscv: dts: spacemit: Add USB2 PHY node for K1Ze Huang
K1's DWC3 USB 3.0 controller requires two separate PHYs to function: the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed, Full-Speed, etc.). Add node for this second USB 2.0 PHY (usbphy2). Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ze Huang <huang.ze@linux.dev> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-20riscv: dts: spacemit: sdhci: add reset supportYixun Lan
Request two reset line explicitly for SDHCI controller. Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20251223-07-k1-sdhci-reset-v2-3-5b8248cfc522@gentoo.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-20riscv: dts: spacemit: add reset propertyEncrow Thorne
Add resets property to K1 I2C node. Signed-off-by: Encrow Thorne <jyc0019@gmail.com> Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2026-01-20riscv: dts: sophgo: sg2044: Add "b" ISA extensionGuodong Xu
"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update sg2044-cpus.dtsi to conform to this rule. Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2026-01-20riscv: dts: sophgo: fix the node order of SG2042 peripheralInochi Amaoto
In sg2042.dtsi, some peripheral device node does not follow the address order. Reorder them in ascending order by address. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2026-01-20riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsiInochi Amaoto
As we have a separate CPU dtsi file, move the PLIC and CLINT node to the CPU dtsi file. This will make the sg2042.dtsi focus on peripheral devices, and make the CPU dtsi force CPU related devices. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2026-01-19riscv: dts: anlogic: dr1v90: Add "b" ISA extensionGuodong Xu
"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update dr1v90.dtsi to conform to this rule. Line balancing is performed to improve readability. Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-01-15riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V PioneerMichael Orlitzky
These boards have a working hardware clock if you put a CR-1220 battery in them. We enable it using information from a 6.1.x vendor kernel. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Michael Orlitzky <michael@orlitzky.com> Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2026-01-14riscv: dts: allwinner: d1: Add RGB LEDs to boardsSamuel Holland
Some D1-based boards feature an onboard RGB LED. Enable them. Acked-by: Guo Ren <guoren@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://patch.msgid.link/20231029212738.7871-6-samuel@sholland.org Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-01-14riscv: dts: allwinner: d1: Add LED controller nodeSamuel Holland
Allwinner D1 contains an LED controller. Add its devicetree node, as well as the pinmux used by the reference board design. Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://patch.msgid.link/20231029212738.7871-5-samuel@sholland.org [wens@kernel.org: move "status" to end of properties] Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-01-08riscv: dts: renesas: r9a07g043f: Move interrupt-parent to top nodeGeert Uytterhoeven
Move the "interrupt-parent = <&plic>" property from the soc node to the top node, for consistency with arch/arm64/boot/dts/renesas/r9a07g043u.dtsi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/97d3d70e42832f4ffa3888bec792b692a7ab700f.1767719409.git.geert+renesas@glider.be
2025-12-24riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizesAnton D. Stavinskii
I've tested the current dwc2 FIFO configuration and found that USB device mode breaks in ECM mode when transmitting frames larger than 128 bytes. For example, large ICMP packets or iperf3 traffic cause the USB link to hang and eventually disconnect without any messages in dmesg. After switching to more conservative FIFO sizes, ECM becomes stable and no longer drops the connection. iperf3 now shows ~130 Mbit/s RX and ~100 Mbit/s TX on SG2002 (MilkV Duo 256M). Fix the FIFO sizes accordingly. Signed-off-by: Anton D. Stavinskii <stavinsky@gmail.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Fixes: e307248a3c2d ("riscv: dts: sophgo: Add USB support for cv18xx") Link: https://lore.kernel.org/r/20251126172115.1894190-2-stavinsky@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-12-24riscv: dts: spacemit: PCIe and PHY-related updatesAlex Elder
Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 board. The combo PHY is used for USB on this board, and that will be enabled when USB 3 support is accepted. The combo PHY must perform a calibration step to determine configuration values used by the PCIe-only PHYs. As a result, it must be enabled if either of the other two PHYs is enabled. Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Tested-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-24riscv: dts: spacemit: Add a PCIe regulatorAlex Elder
Define a 3.3v fixed voltage regulator to be used by PCIe on the Banana Pi BPI-F3. On this platform, this regulator is always on. Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Tested-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251218151235.454997-5-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-20riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite ↵E Shattow
eMMC board Append "starfive,jh7110" compatible to VisionFive 2 Lite eMMC board in the least-compatible end of the list. Appending "starfive,jh7110" reduces the number of compatible strings to check in the OpenSBI platform driver. JH-7110S SoC on this board is the same as JH-7110 SoC however rated for thermal, voltage, and frequency characteristics for a maximum of 1.25GHz operation. Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/ Suggested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-12-20riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite boardE Shattow
Append "starfive,jh7110" compatible to VisionFive 2 Lite board in the least-compatible end of the list. Appending "starfive,jh7110" reduces the number of compatible strings to check in the OpenSBI platform driver. JH-7110S SoC on this board is the same as JH-7110 SoC however rated for thermal, voltage, and frequency characteristics for a maximum of 1.25GHz operation. Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/ Suggested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-12-20riscv: dts: microchip: convert clock and reset to use sysconConor Dooley
The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-12-20riscv: dts: microchip: fix mailbox descriptionConor Dooley
When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-12-19riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V JupiterJavier Martinez Canillas
Define the SpacemiT P1 PMIC voltage regulators and their constraints. The power management hardware design on the Milk-V Jupiter is identical to the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-19riscv: dts: spacemit: Define fixed regulators for Milk-V JupiterJavier Martinez Canillas
Define the DC power input and the 4v power as fixed regulator supplies. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-19riscv: dts: spacemit: Enable i2c8 adapter for Milk-V JupiterJavier Martinez Canillas
The adapter is used to access the SpacemiT P1 PMIC present in this board. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-05Merge tag 'soc-newsoc-6.19' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new SoC families update from Arnd Bergmann: "These three new families of SoC are split out into a separate branch because they touch multiple parts of the source tree and are better left separate for the initial merge. - Black Sesame Technologies C1200 is an automotive SoC using Cortex-A78 CPU cores - Anlogic dr1v90 (not to be confused with Amlogic) is an FPGA platform using a single nuclei ux900 RISC-V core - Tenstorrent Blackhole is a Neural Processing Unit using custom "Tensix" cores for computation offload managed by Linux running on SiFive X280 RISC-V cores. Support for all three is rather rudimentary at the moment and will get improved as device drivers are merged through other tree" * tag 'soc-newsoc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits) MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support arm64: defconfig: enable BST platform support arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs dt-bindings: arm: add Black Sesame Technologies (bst) SoC dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd. MAINTAINERS: Setup support for Anlogic tree riscv: defconfig: Enable Anlogic SoC riscv: dts: anlogic: Add Milianke MLKPAI FS01 board riscv: dts: Add initial Anlogic DR1V90 SoC device tree riscv: Add Anlogic SoC famly Kconfig support dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER dt-bindings: riscv: Add Anlogic DR1V90 dt-bindings: riscv: Add Nuclei UX900 compatibles dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei riscv: defconfig: Enable Tenstorrent SoCs riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible ...
2025-12-05Merge tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "Three new SoCs got added in existing arm64 chip families: - Renesas R-Car X5H (R8A78000) is a new generation of automotive SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the currently highest-perforance embedded SoC. - TI AM62L is a new variant of the AM62 family of industrial SoCs, this one comes without a GPU. - Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip based on Cortex-A53, and closely related to MSM8917 (Snapdragn 425), which we already support. In addition, there are a good number of newly supported machines across SoC families: - Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers - Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124, Qualcomm MSM8937 and Qualcomm MSM8939, - Two Laptops based on Qualcomm SoCs: one using the older sdm850, the other using x1p42100. - One Router based on Rockchips RK3568 - 24 variants of the Enclustra Mercury system-on-module, all based on 32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit SocFPGA Agilex chips.. - 30 industrial/embedded boards and single-board computers, using various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm, Spacemit, and Starfive. In total there are 783 commits here, the majority of these improving hardware support and cleaning up devicetree files across the tree, with the majority of the changes going into the Qualcomm, NXP, Renesas and Rockchips platforms" * tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits) arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1 ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs arm64: dts: Add gpio_intc node for Amlogic S7D SoCs arm64: dts: Add gpio_intc node for Amlogic S7 SoCs arm64: dts: Add gpio_intc node for Amlogic S6 SoCs arm64: dts: amlogic: s7d: add ao secure node arm64: dts: amlogic: s7: add ao secure node arm64: dts: amlogic: s6: add ao secure node arm64: dts: amlogic: Fix the register name of the 'DBI' region dts: arm64: amlogic: add a5 pinctrl node arm64: dts: amlogic: s7d: add power domain controller node arm64: dts: amlogic: s7: add power domain controller node arm64: dts: amlogic: s6: add power domain controller node dts: arm64: amlogic: Add ISP related nodes for C3 arm64: dts: meson: add initial device-tree for Tanix TX9 Pro dt-bindings: arm: amlogic: add support for Tanix TX9 Pro ...
2025-11-27Merge tag 'riscv-dt-for-v6.19' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.19 MAINTAINERS: There's some re-jigging of things to reduce duplication, by moving me into the StarFive entry and my tree into the Microchip one. The other platforms that I look after (SiFive and Canaan) are marked as Odd Fixes to better represent their status. Nothing functionally changes. Microchip: Add adc and mmc nodes for the Beagle-V Fire. SiFive: Add pwm fans to the unmatched board. StarFive: Add the Orange PI RV board, another VisionFive 2 derived SBC. This required moving a mmc related nodes out of the common file, into <board>.dts. Yet more things moved out of the common file when the VisionFive 2 Lite boards were added, which use the JH7110S SoC instead of the JH7110. The difference here between SoCs is just temperature and frequency ranges, but the boards differ enough that the pool of common nodes decreases a little further. There's an eMMC and an SD variant here, that are different SKUs, bringing the total new StarFive boards to three. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: add Orange Pi RV dt-bindings: riscv: starfive: add xunlong,orangepi-rv riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree riscv: dts: starfive: Add VisionFive 2 Lite board device tree riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes MAINTAINERS: add tree to RISC-V Microchip entry MAINTAINERS: remove patchwork from RISC-V MISC SOC SUPPORT MAINTAINERS: add Conor to StarFive entry riscv: dts: sifive: unmatched: Add PWM controlled fans riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-25riscv: dts: starfive: add Orange Pi RVIcenowy Zheng
Orange Pi RV is a SBC based on the StarFive VisionFive 2 board. Orange Pi RV features: - StarFive JH7110 SoC - GbE port connected to JH7110 GMAC0 via YT8531 PHY - 4x USB ports via VL805 PCIe USB controller connected to JH7110 pcie0 - M.2 M-key slot connected to JH7110 pcie1 - HDMI video output - 3.5mm audio output - Ampak AP6256 SDIO Wi-Fi/Bluetooth module on mmc0 - microSD slot on mmc1 - SPI NOR flash memory - 24c02 EEPROM (read only by default) Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: E Shattow <e@freeshell.de> [conor: amend comment to say what's missing] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-25riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device treeHal Feng
VisionFive 2 Lite eMMC board uses a non-removable onboard 64GiB eMMC instead of the MicroSD slot. Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-25riscv: dts: starfive: Add VisionFive 2 Lite board device treeHal Feng
VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC. Board features: - JH7110S SoC - 4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 1x USB 3.0 host port - 3x USB 2.0 host port - 1x M.2 M-Key (size: 2242) - 1x MicroSD slot (optional non-removable 64GiB eMMC) - 1x QSPI Flash - 1x I2C EEPROM - 1x 1Gbps Ethernet port - SDIO-based Wi-Fi & UART-based Bluetooth - 1x HDMI port - 1x 2-lane DSI - 1x 2-lane CSI VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-25riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variantsHal Feng
Add a common board dtsi for use by VisionFive 2 Lite and VisionFive 2 Lite eMMC. Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-25riscv: dts: starfive: jh7110-common: Move out some nodes to the board dtsHal Feng
Some node in this file are not used by the upcoming VisionFive 2 Lite board. Move them to the board dts to prepare for adding the new VisionFive 2 Lite device tree. Tested-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-23riscv: dts: sifive: unmatched: Add PWM controlled fansRené Rebe
This adds the two PWM-controlled fans of the HiFive Unmatched board to the device tree. Signed-off-by: René Rebe <rene@exactco.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-22riscv: dts: allwinner: d1: fix vlenb propertySergey Matyukevich
According to [1], the C906 vector registers are 128 bits wide. The 'thead,vlenb' property specifies the vector register length in bytes, so its value must be set to 16. [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-21Merge tag 'anlogic-initial-6.19-v2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc Initial Anlogic Platform Support Add bindings for the serial and timer peripherals, and a basic soc dtsi for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board for this SoC. Add myself as maintainer for this platform for the time being. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: Setup support for Anlogic tree riscv: defconfig: Enable Anlogic SoC riscv: dts: anlogic: Add Milianke MLKPAI FS01 board riscv: dts: Add initial Anlogic DR1V90 SoC device tree riscv: Add Anlogic SoC famly Kconfig support dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER dt-bindings: riscv: Add Anlogic DR1V90 dt-bindings: riscv: Add Nuclei UX900 compatibles dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
2025-11-21Merge tag 'riscv-sophgo-dt-for-v6.19' of https://github.com/sophgo/linux ↵Arnd Bergmann
into soc/dt RISC-V Devicetrees for v6.19 Sophgo: For CV18xx serials: Add top syscon device related DTS change, the top system controller provides register access to configure some misc modules, such as usb2 phy and a dma multiplexer. For SG2042: There are two changes. The first one is to add DTS definition for PCIe controllers for SoC SG2042 and boards such as Pioneerbox/EVB_V1/EVB_V2 uses SG2042. The second one is to add DTS to support SPI-NOR flash controllers for this SoC and the same for related boards. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.19' of https://github.com/sophgo/linux: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 riscv: dts: sophgo: Enable SPI NOR node for PioneerBox riscv: dts: sophgo: Add SPI NOR node for SG2042 riscv: dts: sophgo: Add USB support for cv18xx riscv: dts: sophgo: Add syscon node for cv18xx dt-bindings: soc: sophgo: add TOP syscon for CV18XX/SG200X series SoC riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X riscv: sophgo: dts: enable PCIe for PioneerBox riscv: sophgo: dts: add PCIe controllers for SG2042 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-21Merge tag 'spacemit-dt-for-6.19-1' of https://github.com/spacemit-com/linux ↵Arnd Bergmann
into soc/dt RISC-V SpacemiT DT changes for 6.19 - Add Uart and I2C nodes - Add P1 PMIC nodes - Add MusePi Pro board support - Add OrangePi R2S board support - Enable eeprom for BPI-F3 - Enable QSPI on BPI-F3 - Enable Ethernet and PDMA on OrangePi RV2 * tag 'spacemit-dt-for-6.19-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: define all missing I2C controller nodes riscv: dts: spacemit: reorder i2c2 node riscv: dts: spacemit: Add OrangePi R2S board device tree dt-bindings: riscv: spacemit: Add OrangePi R2S board riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3 riscv: dts: spacemit: add MusePi Pro board device tree dt-bindings: riscv: spacemit: add MusePi Pro board riscv: dts: spacemit: add Ethernet and PDMA to OrangePi RV2 riscv: dts: spacemit: add i2c aliases on BPI-F3 riscv: dts: spacemit: add 24c02 eeprom on BPI-F3 riscv: dts: spacemit: enable the i2c2 adapter on BPI-F3 riscv: dts: spacemit: define regulator constraints riscv: dts: spacemit: define fixed regulators riscv: dts: spacemit: enable the i2c8 adapter riscv: dts: spacemit: add UART pinctrl combinations Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-18riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2Zixian Zeng
Enable SPI NOR node for SG2042_EVB_V2 device tree According to SG2042_EVB_V2 schematic, SPI-NOR Flash cannot support QSPI due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1. Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com> Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-4-b5d9024fe1c8@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-11-18riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1Zixian Zeng
Enable SPI NOR node for SG2042_EVB_V1 device tree According to SG2042_EVB_V1 schematic, SPI-NOR Flash cannot support QSPI due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1. Signed-off-by: Han Gao <rabenda.cn@gmail.com> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com> Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-3-b5d9024fe1c8@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-11-18riscv: dts: sophgo: Enable SPI NOR node for PioneerBoxZixian Zeng
Enable SPI NOR node for PioneerBox device tree According to PioneerBox schematic, SPI-NOR Flash cannot support QSPI due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com> Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-2-b5d9024fe1c8@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-11-18riscv: dts: sophgo: Add SPI NOR node for SG2042Zixian Zeng
Add SPI NOR controller node for SG2042 Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com> Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-1-b5d9024fe1c8@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
generated by cgit v1.2.3 (git 2.0.4) at 2026-02-19 12:12:48 +0000