| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-06-30 | riscv: add ASID-based tlbflushing methods | Guo Ren |
| 2021-02-18 | RISC-V: Implement ASID allocator | Anup Patel |
| 2020-10-27 | riscv: use asm-generic/mmu_context.h for no-op implementations | Nicholas Piggin |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
| 2019-05-16 | riscv: move switch_mm to its own file | Gary Guo |
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel |
| 2018-01-30 | riscv: inline set_pgdir into its only caller | Christoph Hellwig |
| 2018-01-30 | riscv: rename sptbr to satp | Christoph Hellwig |
| 2018-01-30 | riscv: remove the unused current_pgdir function | Christoph Hellwig |
| 2017-12-01 | RISC-V: Fixes for clean allmodconfig build | Palmer Dabbelt |
| 2017-11-30 | RISC-V: Flush I$ when making a dirty page executable | Andrew Waterman |
| 2017-11-30 | RISC-V: Add missing include | Olof Johansson |
| 2017-09-26 | RISC-V: Paging and MMU | Palmer Dabbelt |
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index : linux-toradex.git | |
| Linux kernel for Apalis and Colibri modules | Toradex |
| summaryrefslogtreecommitdiff |