linux-toradex.git - Linux kernel for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2024-04-29	riscv: Use IPIs for remote cache/TLB flushes by default	Samuel Holland
2024-01-04	riscv: Use the same CPU operations for all CPUs	Samuel Holland
2023-08-08	riscv: Fix CPU feature detection with SMP disabled	Samuel Holland
2023-07-04	RISC-V: drop error print from riscv_hartid_to_cpuid()	Conor Dooley
2023-04-28	Merge tag 'smp-core-2023-04-27' of git://git.kernel.org/pub/scm/linux/kernel/...	Linus Torvalds
2023-04-08	RISC-V: Allow marking IPIs as suitable for remote FENCEs	Anup Patel
2023-04-08	RISC-V: Treat IPIs as normal Linux IRQs	Anup Patel
2023-04-08	RISC-V: Clear SIP bit only when using SBI IPI operations	Anup Patel
2023-03-24	treewide: Trace IPIs sent via smp_send_reschedule()	Valentin Schneider
2022-11-29	riscv: kexec: Fixup crash_smp_send_stop without multi cores	Guo Ren
2022-08-07	Merge tag 'mm-nonmm-stable-2022-08-06-2' of git://git.kernel.org/pub/scm/linu...	Linus Torvalds
2022-07-29	profile: setup_profiling_timer() is moslty not implemented	Ben Dooks
2022-07-19	riscv: smp: Add 64bit hartid support on RV64	Sunil V L
2022-01-09	RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n	Sean Christopherson
2021-10-26	irq: riscv: perform irqentry in entry code	Mark Rutland
2021-05-01	RISC-V: Fix error code returned by riscv_hartid_to_cpuid()	Anup Patel
2021-04-26	riscv: Constify sbi_ipi_ops	Jisheng Zhang
2021-04-26	riscv: Mark some global variables __ro_after_init	Jisheng Zhang
2021-03-16	riscv: Enable generic clockevent broadcast	Guo Ren
2020-08-20	RISC-V: Remove CLINT related code from timer and arch	Anup Patel
2020-08-20	RISC-V: Add mechanism to provide custom IPI operations	Anup Patel
2020-07-30	riscv: Support irq_work via self IPIs	Greentime Hu
2020-06-09	RISC-V: self-contained IPI handling routine	Anup Patel
2020-05-04	RISC-V: Export riscv_cpuid_to_hartid_mask() API	Anup Patel
2020-03-18	riscv: fix the IPI missing issue in nommu mode	Greentime Hu
2019-11-17	riscv: provide native clint access for M-mode	Christoph Hellwig
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig
2019-10-28	riscv: add missing header file includes	Paul Walmsley
2019-09-20	RISC-V: Export kernel symbols for kvm	Atish Patra
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig
2019-09-05	riscv: optimize send_ipi_single	Christoph Hellwig
2019-09-05	riscv: cleanup send_ipi_mask	Christoph Hellwig
2019-09-05	riscv: refactor the IPI code	Christoph Hellwig
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner
2019-05-16	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel
2019-05-16	RISC-V: Fix minor checkpatch issues.	Atish Patra
2019-04-30	RISC-V: Add RISC-V specific arch_match_cpu_phys_id	Atish Patra
2019-03-04	RISC-V: Fixmap support and MM cleanups	Palmer Dabbelt
2019-03-04	RISC-V: Allow hartid-to-cpuid function to fail.	Atish Patra
2019-03-04	RISC-V: Move cpuid to hartid mapping to SMP.	Atish Patra
2019-01-07	riscv: don't stop itself in smp_send_stop	Andreas Schwab
2018-10-22	RISC-V: Show IPI stats	Anup Patel
2018-10-22	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra
2018-10-22	RISC-V: Add logical CPU indexing for RISC-V	Atish Patra
2018-08-13	RISC-V: simplify software interrupt / IPI code	Christoph Hellwig
2017-12-01	RISC-V: Fixes for clean allmodconfig build	Palmer Dabbelt
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman
2017-11-30	RISC-V: Provide stub of setup_profiling_timer()	Olof Johansson
2017-09-26	RISC-V: Init and Halt Code	Palmer Dabbelt