linux-toradex.git - Linux kernel for Apalis and Colibri modules

Age	Commit message (Expand)	Author
2024-08-31	riscv: misaligned: Restrict user access to kernel memory	Samuel Holland
2024-08-14	RISC-V: hwprobe: Add SCALAR to misaligned perf defines	Evan Green
2024-04-28	riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code	Clément Léger
2024-03-13	riscv: Set unaligned access speed at compile time	Charlie Jenkins
2024-03-13	riscv: Decouple emulated unaligned accesses from access speed	Charlie Jenkins
2024-03-13	riscv: Only check online cpus for emulated accesses	Charlie Jenkins
2024-01-09	Merge remote-tracking branch 'palmer/fixes' into for-next	Palmer Dabbelt
2024-01-09	riscv: fix __user annotation in traps_misaligned.c	Ben Dooks
2023-12-06	riscv: fix misaligned access handling of C.SWSP and C.SDSP	Clément Léger
2023-11-07	RISC-V: Remove __init on unaligned_emulation_finish()	Evan Green
2023-11-01	riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN	Clément Léger
2023-11-01	riscv: report misaligned accesses emulation to hwprobe	Clément Léger
2023-11-01	riscv: add support for sysctl unaligned_enabled control	Clément Léger
2023-11-01	riscv: add floating point insn support to misaligned access emulation	Clément Léger
2023-11-01	riscv: report perf event for misaligned fault	Clément Léger
2023-11-01	riscv: add support for misaligned trap handling in S-mode	Clément Léger
2023-11-01	riscv: remove unused functions in traps_misaligned.c	Clément Léger
2022-08-11	riscv: traps_misaligned: do not duplicate stringify	Krzysztof Kozlowski
2020-04-03	riscv: Unaligned load/store handling for M_MODE	Damien Le Moal