Age | Commit message (Expand) | Author |
---|---|---|
2019-05-25 | clk: mediatek: Disable tuner_en before change PLL rate | Owen Chen |
2017-11-02 | clk: mediatek: add the option for determining PLL source clock | Chen Zhong |
2017-11-02 | clk: mediatek: Add MT2712 clock support | weiyi.lu@mediatek.com |
2016-11-08 | clk: mediatek: Add MT2701 clock support | Shunli Wang |
2016-08-18 | clk: mediatek: remove __init from clk registration functions | James Liao |
2015-10-01 | clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS | James Liao |
2015-07-28 | clk: mediatek: Add MT8173 MMPLL change rate support | James Liao |
2015-07-28 | clk: mediatek: Fix calculation of PLL rate settings | James Liao |
2015-07-28 | clk: mediatek: Fix PLL registers setting flow | James Liao |
2015-05-19 | clk: mediatek: Initialize clk_init_data | Ricky Liang |
2015-05-05 | clk: mediatek: Add initial common clock support for Mediatek SoCs. | James Liao |