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Pull bitmap updates from Yury Norov:
- FIELD_PREP_WM16() consolidation (Nicolas)
- bitmaps for Rust (Burak)
- __fls() fix for arc (Kees)
* tag 'bitmap-for-6.18' of https://github.com/norov/linux: (25 commits)
rust: add dynamic ID pool abstraction for bitmap
rust: add find_bit_benchmark_rust module.
rust: add bitmap API.
rust: add bindings for bitops.h
rust: add bindings for bitmap.h
phy: rockchip-pcie: switch to FIELD_PREP_WM16 macro
clk: sp7021: switch to FIELD_PREP_WM16 macro
PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro
PCI: rockchip: Switch to FIELD_PREP_WM16* macros
net: stmmac: dwmac-rk: switch to FIELD_PREP_WM16 macro
ASoC: rockchip: i2s-tdm: switch to FIELD_PREP_WM16_CONST macro
drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros
phy: rockchip-usb: switch to FIELD_PREP_WM16 macro
drm/rockchip: inno-hdmi: switch to FIELD_PREP_WM16 macro
drm/rockchip: dw_hdmi_qp: switch to FIELD_PREP_WM16 macro
phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macro
drm/rockchip: vop2: switch to FIELD_PREP_WM16 macro
drm/rockchip: dsi: switch to FIELD_PREP_WM16* macros
phy: rockchip-emmc: switch to FIELD_PREP_WM16 macro
drm/rockchip: lvds: switch to FIELD_PREP_WM16 macro
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.
Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.
Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.
Driver updates in the cache controller, memory controller and reset
controller subsystems.
SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.
TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"
* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...
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Pull SoC dt updates from Arnd Bergmann:
"There are five sets of new SoCs that get added in existing families,
all of them being either upgrades or cut-down versions of the older
chips:
- Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation
of high-end workstations and laptops from Apple. Linux has been
working on these for a while but stil requires patches.
- Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
unlike the earlier Armv7 Artpec6 from the same company that was
part of a separate family of chips.
- NXP i.MX91 is a cut-down version of i.MX93, using only a single
Cortex-A55 core.
- Qualcomm Lemans Auto is a variant of the Lemans SoC that was
originally merged under the sa8775p name, the differences being
mostly the firmware configuration of the platform.
- Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial
bedded SoCs based on Cortex-A55 cores
In total, there are 65 new machines, including:
- Industrial embedded system and single-board computers based on NXP,
Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.
- Reference boards for the newly added Renesas, Qualcomm, NXP and
Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC
- Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1
chips.
- Several Samsung phones using Qualcomm Snapdragon chips
- Set-top boxes based on Allwinner H313
- Five BMC boards using 32-bit ASpeed SoCs
- Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
(ARMv7) SoCs
Two machines get phased out because they were available only in small
quantities but never made it into products: one STi407 based reference
board, and a Snapdragon 845 based Chromebook.
Aside from the newly added machines, a lot of work went into improving
hardware support on the existing machines and cleaning up contents for
validation"
* tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits)
arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
ARM: dts: microchip: sam9x7: Add qspi controller
arm64: dts: qcom: Add MST pixel streams for displayport
arm64: dts: qcom: sm6350: correct DP compatibility strings
arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
arm64: dts: allwinner: h313: Add Amediatech X96Q
dt-bindings: arm: sunxi: Add Amediatech X96Q
arm64: dts: apple: t8015: Add SPMI node
arm64: dts: apple: t8012: Add SPMI node
arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
arm64: dts: rockchip: update pinctrl names for Radxa E52C
arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
arm64: dts: apple: Add J474s, J475c and J475d device trees
arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
...
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The sp7021 clock driver has its own shifted high word mask macro,
similar to the ones many Rockchip drivers have.
Remove it, and replace instances of it with hw_bitfield.h's
FIELD_PREP_WM16 macro, which does the same thing except in a common
macro that also does compile-time error checking.
This was compile-tested with 32-bit ARM with Clang, no runtime tests
were performed as I lack the hardware. However, I verified that fix
commit 5c667d5a5a3e ("clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()")
is not regressed. No warning is produced.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull an Allwinner clk driver fix from Chen-Yu Tsai:
- One fix for the clock rate readback on the recently added dual
divider clocks
* tag 'sunxi-clk-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: mp: Fix dual-divider clock rate readback
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Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into
clk-tegra30 source.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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When dual-divider clock support was introduced, the P divider offset was
left out of the .recalc_rate readback function. This causes the clock
rate to become bogus or even zero (possibly due to the P divider being
1, leading to a divide-by-zero).
Fix this by incorporating the P divider offset into the calculation.
Fixes: 45717804b75e ("clk: sunxi-ng: mp: introduce dual-divider clock")
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250830170901.1996227-4-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/linux-clk/20250828-clk-round-rate-v2-v1-0-b97ec8ba6cc4@redhat.com/T/#mbb878a331cf0f8930257a356c1d9e2ab458e3efb
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The RP1 clock generator driver currently defines only the fundamental
clocks such as the front PLLs for system, audio and video subsystems
and the ethernet clock.
Add the remaining clocks to the tree so as to be completed, which means
that the following RP1 peripherals could now consume their specific clocks
and be enabled to work (provided that the relevant driver changes for each
specific peripheral, if any, are committed):
- ADC
- Audio IN/OUT
- DMA controller
- I2S
- MIPI DPI/DSI
- PWM
- SDIO
- UART
- Video Encoder
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/17e5c6e0c085cfa0bf4b63b639cdc92c6a4c1418.1750714412.git.andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Genpd OF providers must now be registered after genpd bus registration.
However, cpg_mstp_add_clk_domain() is only called from CLK_OF_DECLARE(),
which is too early. Hence on R-Car M1A, R-Car H1, and RZ/A1, the
CPG/MSTP Clock Domain fails to register, and any devices residing in
that clock domain fail to probe.
Fix this by splitting initialization into two steps:
- The first part keeps on registering the PM domain with genpd at
CLK_OF_DECLARE(),
- The second and new part moves the registration of the genpd OF
provider to a postcore_initcall().
See also commit c5ae5a0c61120d0c ("pmdomain: renesas: rcar-sysc: Add
genpd OF provider at postcore_initcall").
Fixes: 18a3a510ecfd0e50 ("pmdomain: core: Add the genpd->dev to the genpd provider bus")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/81ef5f8d5d31374b7852b05453c52d2f735062a2.1755073087.git.geert+renesas@glider.be
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This is the usual collection of primarily clk driver updates.
The big part of the diff is all the new Qualcomm clk drivers added for
a few SoCs they're working on. The other two vendors with significant
work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks
to existing drivers and supports some new SoCs while Amlogic is
starting a significant refactoring to simplify their code.
The core framework gained a pair of helpers to get the 'struct device'
or 'struct device_node' associated with a 'struct clk_hw'. Some
associated KUnit tests were added for these simple helpers as well.
Beyond that core change there are lots of little fixes throughout the
clk drivers for the stuff we see every day, wrong clk driver data that
affects tree topology or supported frequencies, etc. They're not found
until the clks are actually used by some consumer device driver.
New Drivers:
- Global, display, gpu, video, camera, tcsr, and rpmh clock
controller for the Qualcomm Milos SoC
- Camera, display, GPU, and video clock controllers for Qualcomm
QCS615
- Video clock controller driver for Qualcomm SM6350
- Camera clock controller driver for Qualcomm SC8180X
- I3C clocks and resets on Renesas RZ/G3E
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/V2H(P) and RZ/V2N
- SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
- SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
- Ethernet clocks and resets on Renesas RZ/G3E
- Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
(R9A09G087) SoCs
- Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
- Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
RZ/V2N
Updates:
- Support atomic PWMs in the PWM clk driver
- clk_hw_get_dev() and clk_hw_get_of_node() helpers
- Replace round_rate() with determine_rate() in various clk drivers
- Convert clk DT bindings to DT schema format for DT validation
- Various clk driver cleanups and refactorings from static analysis
tools and possibly real humans
- A lot of little fixes here and there to things like clk tree
topology, missing frequencies, flagging clks as critical, etc"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits)
clk: clocking-wizard: Fix the round rate handling for versal
clk: Fix typos
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
clk: tegra: periph: Make tegra_clk_periph_ops static
clk: tegra: periph: Fix error handling and resolve unsigned compare warning
clk: imx: scu: convert from round_rate() to determine_rate()
clk: imx: pllv4: convert from round_rate() to determine_rate()
clk: imx: pllv3: convert from round_rate() to determine_rate()
clk: imx: pllv2: convert from round_rate() to determine_rate()
clk: imx: pll14xx: convert from round_rate() to determine_rate()
clk: imx: pfd: convert from round_rate() to determine_rate()
clk: imx: frac-pll: convert from round_rate() to determine_rate()
clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
clk: imx: fixup-div: convert from round_rate() to determine_rate()
clk: imx: cpu: convert from round_rate() to determine_rate()
clk: imx: busy: convert from round_rate() to determine_rate()
clk: imx: composite-93: remove round_rate() in favor of determine_rate()
clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
...
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Resolve conflicts with i.MX95 changes 88768d6f8c13 ("clk:
imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx
and aacc875a448d ("clk: imx: Fix an out-of-bounds access in
dispmix_csr_clk_dev_data") in clk-fixes.
* clk-fixes:
clk: sunxi-ng: v3s: Fix TCON clock parents
clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
clk: sunxi-ng: v3s: Fix CSI SCLK clock name
dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
clk: scmi: Handle case where child clocks are initialized before their parents
clk: sunxi-ng: a523: Mark MBUS clock as critical
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* clk-pm:
clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
Documentation: PM: *_autosuspend() functions update last busy time
PM: runtime: Mark last busy stamp in pm_request_autosuspend()
PM: runtime: Mark last busy stamp in pm_runtime_autosuspend()
PM: runtime: Mark last busy stamp in pm_runtime_put_sync_autosuspend()
PM: runtime: Mark last busy stamp in pm_runtime_put_autosuspend()
PM: runtime: Document return values of suspend-related API functions
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'clk-qcom' into clk-next
* clk-rockchip:
clk: rockchip: rk3568: Add PLL rate for 132MHz
* clk-thead:
clk: thead: th1520-ap: Describe mux clocks with clk_mux
clk: thead: th1520-ap: Correctly refer the parent of osc_12m
clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED
* clk-microchip:
clk: at91: sam9x7: update pll clk ranges
* clk-imx:
MAINTAINERS: Update i.MX Clock Entry
clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
clk: imx95-blk-ctl: Rename lvds and displaymix csr blk
clk: imx95-blk-ctl: Fix synchronous abort
dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
* clk-qcom: (65 commits)
dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
dt-bindings: clock: qcom: Remove double colon from description
clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Video Clock Controller
clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos
dt-bindings: clock: qcom: document the Milos GPU Clock Controller
clk: qcom: Add Display Clock controller (DISPCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Display Clock Controller
clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Camera Clock Controller
clk: qcom: Add Global Clock controller (GCC) driver for Milos
dt-bindings: clock: qcom: document the Milos Global Clock Controller
clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe
clk: qcom: gcc-x1e80100: Add missing video resets
dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC
...
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and 'clk-amlogic' into clk-next
* clk-renesas: (42 commits)
clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
clk: renesas: r9a09g057: Add XSPI clock/reset
clk: renesas: r9a09g056: Add XSPI clock/reset
clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
clk: renesas: r9a09g057: Add support for xspi mux and divider
clk: renesas: r9a09g056: Add support for xspi mux and divider
clk: renesas: r9a09g077: Add RIIC module clocks
clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
clk: renesas: r9a09g057: Add entries for the RSPIs
dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
clk: renesas: rzv2h: Add missing include file
clk: renesas: rzv2h: Use devm_kmemdup_array()
clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
clk: renesas: r9a09g077: Add PCLKL core clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
...
* clk-samsung:
clk: samsung: exynosautov920: add block hsi2 clock support
dt-bindings: clock: exynosautov920: add hsi2 clock definitions
dt-bindings: clock: exynosautov920: sort clock definitions
clk: samsung: exynos850: fix a comment
clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD
* clk-spacemit:
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: mark K1 pll1_d8 as critical
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
* clk-allwinner:
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
clk: sunxi-ng: v3s: Fix de clock definition
clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
* clk-amlogic:
clk: amlogic: s4: remove unused data
clk: amlogic: drop clk_regmap tables
clk: amlogic: get regmap with clk_regmap_init
clk: amlogic: remove unnecessary headers
clk: amlogic: axg-audio: use the auxiliary reset driver
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'clk-xilinx' and 'clk-adi' into clk-next
- Support atomic PWMs in the PWM clk driver
- clk_hw_get_dev() and clk_hw_get_of_node() helpers
* clk-bindings: (30 commits)
dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
dt-bindings: clock: Convert qca,ath79-pll to DT schema
dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema
dt-bindings: clock: Convert moxa,moxart-clock to DT schema
dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema
dt-bindings: clock: Convert maxim,max9485 to DT schema
dt-bindings: clock: Convert qcom,krait-cc to DT schema
dt-bindings: clock: qcom: Remove double colon from description
dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema
dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema
dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema
dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
dt-bindings: clock: Convert marvell,berlin2-clk to DT schema
dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema
dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema
dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema
dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema
dt-bindings: clock: Convert lsi,axm5516-clks to DT schema
...
* clk-cleanup: (29 commits)
clk: clocking-wizard: Fix the round rate handling for versal
clk: Fix typos
clk: tegra: periph: Make tegra_clk_periph_ops static
clk: tegra: periph: Fix error handling and resolve unsigned compare warning
clk: imx: scu: convert from round_rate() to determine_rate()
clk: imx: pllv4: convert from round_rate() to determine_rate()
clk: imx: pllv3: convert from round_rate() to determine_rate()
clk: imx: pllv2: convert from round_rate() to determine_rate()
clk: imx: pll14xx: convert from round_rate() to determine_rate()
clk: imx: pfd: convert from round_rate() to determine_rate()
clk: imx: frac-pll: convert from round_rate() to determine_rate()
clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
clk: imx: fixup-div: convert from round_rate() to determine_rate()
clk: imx: cpu: convert from round_rate() to determine_rate()
clk: imx: busy: convert from round_rate() to determine_rate()
clk: imx: composite-93: remove round_rate() in favor of determine_rate()
clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
clk: bcm: bcm2835: convert from round_rate() to determine_rate()
MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry
clk: ti: Simplify ti_find_clock_provider()
...
* clk-pwm:
clk: pwm: Make use of non-sleeping PWMs
clk: pwm: Don't reconfigure running PWM at probe time
clk: pwm: Convert to use pwm_apply_might_sleep()
clk: pwm: Let .get_duty_cycle() return the real duty cycle
* clk-hw-device:
clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests
clk: tests: Make clk_register_clk_parent_data_device_driver() common
clk: add a clk_hw helpers to get the clock device or device_node
* clk-xilinx:
clk: xilinx: vcu: Update vcu init/reset sequence
clk: xilinx: vcu: unregister pll_post only if registered correctly
* clk-adi:
clk: clk-axi-clkgen: fix coding style issues
clk: clk-axi-clkgen move to min/max()
clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime
include: adi-axi-common: add new helper macros
include: linux: move adi-axi-common.h out of fpga
clk: clk-axi-clkgen: make sure to include mod_devicetable.h
clk: clk-axi-clkgen: fix fpfd_max frequency for zynq
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Changes are all over the place, but very little sticks out as
noteworthy.
There is a new misc driver for the Raspberry Pi 5's RP1 multifunction
I/O chip, along with hooking it up to the pinctrl and clk frameworks.
The reset controller and memory subsystems have mainly small updates,
but there are two new reset drivers for the K230 and VC1800B SoCs, and
new memory driver support for Tegra264.
The ARM SMCCC and SCMI firmware drivers gain a few more features that
should help them be supported across more environments. Similarly, the
SoC specific firmware on Tegra and Qualcomm get minor enhancements and
chip support.
In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an
overhaul for code robustness, the Tegra and Qualcomm and NXP drivers
grow to support more chips, while the Hisilicon, Mediatek and Renesas
drivers see mostly janitorial fixes"
* tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (100 commits)
bus: del unnecessary init var
soc: fsl: qe: convert set_multiple() to returning an integer
pinctrl: rp1: use new GPIO line value setter callbacks
soc: hisilicon: kunpeng_hccs: Fix incorrect log information
dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
soc: qcom: socinfo: Add support to retrieve APPSBL build details
soc: qcom: pmic_glink: fix OF node leak
soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs
soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs
soc: qcom: socinfo: Add SoC IDs for SM7635 family
dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
firmware: qcom: scm: request the waitqueue irq *after* initializing SCM
firmware: qcom: scm: initialize tzmem before marking SCM as available
firmware: qcom: scm: take struct device as argument in SHM bridge enable
firmware: qcom: scm: remove unused arguments from SHM bridge routines
soc: qcom: rpmh-rsc: Add RSC version 4 support
memory: tegra: Add Tegra264 MC and EMC support
firmware: tegra: bpmp: Fix build failure for tegra264-only config
...
|
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git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull power management updates from Rafael Wysocki:
"As is tradition, cpufreq is the part with the largest number of
updates that include core fixes and cleanups as well as updates of
several assorted drivers, but there are also quite a few updates
related to system sleep, mostly focused on asynchronous suspend and
resume of devices and on making the integration of system suspend
and resume with runtime PM easier.
Runtime PM is also updated to allow some code duplication in drivers
to be eliminated going forward and to work more consistently overall
in some cases.
Apart from that, there are some driver core updates related to PM
domains that should help to address ordering issues with devm_ cleanup
routines relying on PM domains, some assorted devfreq updates
including core fixes and cleanups, tooling updates, and documentation
and MAINTAINERS updates.
Specifics:
- Fix two initialization ordering issues in the cpufreq core and a
governor initialization error path in it, and clean it up (Lifeng
Zheng)
- Add Granite Rapids support in no-HWP mode to the intel_pstate
cpufreq driver (Li RongQing)
- Make intel_pstate always use HWP_DESIRED_PERF when operating in the
passive mode (Rafael Wysocki)
- Allow building the tegra124 cpufreq driver as a module (Aaron
Kling)
- Do minor cleanups for Rust cpufreq and cpumask APIs and fix
MAINTAINERS entry for cpu.rs (Abhinav Ananthu, Ritvik Gupta, Lukas
Bulwahn)
- Clean up assorted cpufreq drivers (Arnd Bergmann, Dan Carpenter,
Krzysztof Kozlowski, Sven Peter, Svyatoslav Ryhel, Lifeng Zheng)
- Add the NEED_UPDATE_LIMITS flag to the CPPC cpufreq driver
(Prashant Malani)
- Fix minimum performance state label error in the amd-pstate driver
documentation (Shouye Liu)
- Add the CPUFREQ_GOV_STRICT_TARGET flag to the userspace cpufreq
governor and explain HW coordination influence on it in the
documentation (Shashank Balaji)
- Fix opencoded for_each_cpu() in idle_state_valid() in the DT
cpuidle driver (Yury Norov)
- Remove info about non-existing QoS interfaces from the PM QoS
documentation (Ulf Hansson)
- Use c_* types via kernel prelude in Rust for OPP (Abhinav Ananthu)
- Add HiSilicon uncore frequency scaling driver to devfreq (Jie Zhan)
- Allow devfreq drivers to add custom sysfs ABIs (Jie Zhan)
- Simplify the sun8i-a33-mbus devfreq driver by using more devm
functions (Uwe Kleine-König)
- Fix an index typo in trans_stat() in devfreq (Chanwoo Choi)
- Check devfreq governor before using governor->name (Lifeng Zheng)
- Remove a redundant devfreq_get_freq_range() call from
devfreq_add_device() (Lifeng Zheng)
- Limit max_freq with scaling_min_freq in devfreq (Lifeng Zheng)
- Replace sscanf() with kstrtoul() in set_freq_store() (Lifeng Zheng)
- Extend the asynchronous suspend and resume of devices to handle
suppliers like parents and consumers like children (Rafael Wysocki)
- Make pm_runtime_force_resume() work for drivers that set the
DPM_FLAG_SMART_SUSPEND flag and allow PCI drivers and drivers that
collaborate with the general ACPI PM domain to set it (Rafael
Wysocki)
- Add kernel parameter to disable asynchronous suspend/resume of
devices (Tudor Ambarus)
- Drop redundant might_sleep() calls from some functions in the
device suspend/resume core code (Zhongqiu Han)
- Fix the handling of monitors connected right before waking up the
system from sleep (tuhaowen)
- Clean up MAINTAINERS entries for suspend and hibernation (Rafael
Wysocki)
- Fix error code path in the KEXEC_JUMP flow and drop a redundant
pm_restore_gfp_mask() call from it (Rafael Wysocki)
- Rearrange suspend/resume error handling in the core device suspend
and resume code (Rafael Wysocki)
- Fix up white space that does not follow coding style in the
hibernation core code (Darshan Rathod)
- Document return values of suspend-related API functions in the
runtime PM framework (Sakari Ailus)
- Mark last busy stamp in multiple autosuspend-related functions in
the runtime PM framework and update its documentation (Sakari
Ailus)
- Take active children into account in pm_runtime_get_if_in_use() for
consistency (Rafael Wysocki)
- Fix NULL pointer dereference in get_pd_power_uw() in the dtpm_cpu
power capping driver (Sivan Zohar-Kotzer)
- Add support for the Bartlett Lake platform to the Intel RAPL power
capping driver (Qiao Wei)
- Add PL4 support for Panther Lake to the intel_rapl_msr power
capping driver (Zhang Rui)
- Update contact information in the PM ABI docs and maintainer
information in the power domains DT binding (Rafael Wysocki)
- Update PM header inclusions to follow the IWYU (Include What You
Use) principle (Andy Shevchenko)
- Add flags to specify power on attach/detach for PM domains, make
the driver core detach PM domains in device_unbind_cleanup(), and
drop the dev_pm_domain_detach() call from the platform bus type
(Claudiu Beznea)
- Improve Python binding's Makefile for cpupower (John B. Wyatt IV)
- Fix printing of CORE, CPU fields in cpupower-monitor (Gautham
Shenoy)"
* tag 'pm-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (75 commits)
cpufreq: CPPC: Mark driver with NEED_UPDATE_LIMITS flag
PM: docs: Use my kernel.org address in ABI docs and DT bindings
PM: hibernate: Fix up white space that does not follow coding style
PM: sleep: Rearrange suspend/resume error handling in the core
Documentation: amd-pstate:fix minimum performance state label error
PM: runtime: Take active children into account in pm_runtime_get_if_in_use()
kexec_core: Drop redundant pm_restore_gfp_mask() call
kexec_core: Fix error code path in the KEXEC_JUMP flow
PM: sleep: Clean up MAINTAINERS entries for suspend and hibernation
drivers: cpufreq: add Tegra114 support
rust: cpumask: Replace `MaybeUninit` and `mem::zeroed` with `Opaque` APIs
cpufreq: Exit governor when failed to start old governor
cpufreq: Move the check of cpufreq_driver->get into cpufreq_verify_current_freq()
cpufreq: Init policy->rwsem before it may be possibly used
cpufreq: Initialize cpufreq-based frequency-invariance later
cpufreq: Remove duplicate check in __cpufreq_offline()
cpufreq: Contain scaling_cur_freq.attr in cpufreq_attrs
cpufreq: intel_pstate: Add Granite Rapids support in no-HWP mode
cpufreq: intel_pstate: Always use HWP_DESIRED_PERF in passive mode
PM / devfreq: Add HiSilicon uncore frequency scaling driver
...
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Fix the `clk_round_rate` implementation for Versal platforms by calling
the Versal-specific divider calculation helper. The existing code used
the generic divider routine, which results in incorrect round rate.
Fixes: 7681f64e6404 ("clk: clocking-wizard: calculate dividers fractional parts")
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20250625054114.28273-1-shubhrajyoti.datta@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and
uses updated).
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Return 0 instead of -EINVAL if function ccu_pll_recalc_rate() fails to
get correct rate entry. Follow .recalc_rate callback documentation
as mentioned in include/linux/clk-provider.h for error return value.
Signed-off-by: Akhilesh Patil <akhilesh@ee.iitb.ac.in>
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Reviewed-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/aIBzVClNQOBrjIFG@bhairav-test.ee.iitb.ac.in
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Reduce symbol visibility by converting tegra_clk_periph_ops to static.
Removed the extern declaration from clk.h as the symbol is now locally
scoped to clk-periph.c.
Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn>
Link: https://lore.kernel.org/r/bda59ad46afae6e7484edf8e2f7bf23ceafe51e9.1752046270.git.xiaopei01@kylinos.cn
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
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./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING:
Unsigned expression compared with zero: rate < 0
The unsigned long 'rate' variable caused:
- Incorrect handling of negative errors
- Compile warning: "Unsigned expression compared with zero"
Fix by changing to long type and adding req->rate cast.
Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn>
Link: https://lore.kernel.org/r/79c7f01e29876c612e90d6d0157fb1572ca8b3fb.1752046270.git.xiaopei01@kylinos.cn
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
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The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
This driver also implements both the determine_rate() and round_rate()
clk ops, and the round_rate() clk ops is deprecated. When both are
defined, clk_core_determine_round_nolock() from the clk core will only
use the determine_rate() clk ops, so let's remove the round_rate() clk
ops since it's unused.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-13-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-12-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-11-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-10-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-9-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-8-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-7-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-6-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
The change to call fixup_div->ops->determine_rate() instead of
fixup_div->ops->round_rate() was done by hand.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-5-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-4-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
The change to call busy->div_ops->determine_rate() instead of
busy->div_ops->round_rate() was done by hand.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-3-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
This driver implements both the determine_rate() and round_rate() clk
ops, and the round_rate() clk ops is deprecated. When both are defined,
clk_core_determine_round_nolock() from the clk core will only use the
determine_rate() clk ops, so let's remove the round_rate() clk ops since
it's unused.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-2-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
This driver implements both the determine_rate() and round_rate() clk
ops, and the round_rate() clk ops is deprecated. When both are defined,
clk_core_determine_round_nolock() from the clk core will only use the
determine_rate() clk ops, so let's remove the round_rate() clk ops since
it's unused.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250710-clk-imx-round-rate-v1-1-5726f98e6d8d@redhat.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
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pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(),
pm_runtime_autosuspend() and pm_request_autosuspend() now include a call
to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to
pm_runtime_mark_last_busy().
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Link: https://lore.kernel.org/r/20250704075401.3217179-1-sakari.ailus@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
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pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(),
pm_runtime_autosuspend() and pm_request_autosuspend() now include a call
to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to
pm_runtime_mark_last_busy().
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Link: https://lore.kernel.org/r/20250704075400.3217126-1-sakari.ailus@linux.intel.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-1-3a8da898367e@redhat.com
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Mux clocks are now described with a customized ccu_mux structure
consisting of ccu_internal and ccu_common substructures, and registered
later with devm_clk_hw_register_mux_parent_data_table(). As this helper
always allocates a new clk_hw structure, it's extremely hard to use mux
clocks as parents statically by clk_hw pointers, since CCF has no
knowledge about the clk_hw structure embedded in ccu_mux.
This scheme already causes issues for clock c910, which takes a mux
clock, c910-i0, as a possible parent. With mainline U-Boot that
reparents c910 to c910-i0 at boottime, c910 is considered as an orphan
by CCF.
This patch refactors handling of mux clocks, embeds a clk_mux structure
in ccu_mux directly. Instead of calling devm_clk_hw_register_mux_*(),
we could register mux clocks on our own without allocating any new
clk_hw pointer, fixing c910 clock's issue.
Fixes: ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
|
|
Merge miscellaneous power management updates and cpupower utility
updates for 6.17-rc1:
- Update contact information in the PM ABI docs and maintainer
information in the power domains DT binding (Rafael Wysocki)
- Update PM header inclusions to follow the IWYU (Include What You Use)
principle (Andy Shevchenko)
- Add flags to specify power on attach/detach for PM domains, make the
driver core detach PM domains in device_unbind_cleanup(), and drop
the dev_pm_domain_detach() call from the platform bus type (Claudiu
Beznea)
- Improve Python binding's Makefile for cpupower (John B. Wyatt IV)
- Fix printing of CORE, CPU fields in cpupower-monitor (Gautham Shenoy)
* pm-misc:
PM: docs: Use my kernel.org address in ABI docs and DT bindings
driver core: platform: Drop dev_pm_domain_detach() call
PM: domains: Detach on device_unbind_cleanup()
PM: domains: Add flags to specify power on attach/detach
PM: Don't use "proxy" headers
* pm-tools:
cpupower: Improve Python binding's Makefile
pm: cpupower: Fix printing of CORE, CPU fields in cpupower-monitor
pm: cpupower: Fix the snapshot-order of tsc,mperf, clock in mperf_stop()
|
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clock fixes from Chen-Yu Tsai:
- Mark A523 MBUS clock as critical
- Fix names of CSI related clocks on V3s
This includes changes to the driver, DT bindings and DT files.
- Fix parents of TCON clock on V3s
* tag 'sunxi-clk-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: v3s: Fix TCON clock parents
clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
clk: sunxi-ng: v3s: Fix CSI SCLK clock name
clk: sunxi-ng: a523: Mark MBUS clock as critical
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i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock
gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL
register controls the selection of the clock feeding the display engine.
Add clock gate support for the two CSRs.
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-4-c1b676ec13be@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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Rename i.MX95 lvds and displaymix csr blk drvdata in order to add
support for i.MX943.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-3-c1b676ec13be@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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When enabling runtime PM for clock suppliers that also belong to a power
domain, the following crash is thrown:
error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP
Workqueue: events_unbound deferred_probe_work_func
pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : clk_mux_get_parent+0x60/0x90
lr : clk_core_reparent_orphans_nolock+0x58/0xd8
Call trace:
clk_mux_get_parent+0x60/0x90
clk_core_reparent_orphans_nolock+0x58/0xd8
of_clk_add_hw_provider.part.0+0x90/0x100
of_clk_add_hw_provider+0x1c/0x38
imx95_bc_probe+0x2e0/0x3f0
platform_probe+0x70/0xd8
Enabling runtime PM without explicitly resuming the device caused
the power domain cut off after clk_register() is called. As a result,
a crash happens when the clock hardware provider is added and attempts
to access the BLK_CTL register.
Fix this by using devm_pm_runtime_enable() instead of pm_runtime_enable()
and getting rid of the pm_runtime_disable() in the cleanup path.
Fixes: 5224b189462f ("clk: imx: add i.MX95 BLK CTL clk driver")
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20250707-imx95-blk-ctl-7-1-v3-2-c1b676ec13be@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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When num_parents is 4, __clk_register() occurs an out-of-bounds
when accessing parent_names member. Use ARRAY_SIZE() instead of
hardcode number here.
BUG: KASAN: global-out-of-bounds in __clk_register+0x1844/0x20d8
Read of size 8 at addr ffff800086988e78 by task kworker/u24:3/59
Hardware name: NXP i.MX95 19X19 board (DT)
Workqueue: events_unbound deferred_probe_work_func
Call trace:
dump_backtrace+0x94/0xec
show_stack+0x18/0x24
dump_stack_lvl+0x8c/0xcc
print_report+0x398/0x5fc
kasan_report+0xd4/0x114
__asan_report_load8_noabort+0x20/0x2c
__clk_register+0x1844/0x20d8
clk_hw_register+0x44/0x110
__clk_hw_register_mux+0x284/0x3a8
imx95_bc_probe+0x4f4/0xa70
Fixes: 5224b189462f ("clk: imx: add i.MX95 BLK CTL clk driver")
Cc: stable@vger.kernel.org
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com>
Link: https://lore.kernel.org/r/20250619062108.2016511-1-xiaolei.wang@windriver.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Update the min, max ranges of the PLL clocks according to the latest
datasheet to be coherent in the driver. This patch solves the issues in
configuring the clocks related to peripherals with the desired frequency
within the range.
Fixes: 33013b43e271 ("clk: at91: sam9x7: add sam9x7 pmc driver")
Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Link: https://lore.kernel.org/r/20250714093512.29944-1-varshini.rajendran@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Add support for the video clock controller found on Milos (e.g. SM7635)
based devices.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-11-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add support for the graphics clock controller found on Milos (e.g.
SM7635) based devices.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-9-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add support for the display clock controller found on Milos (e.g.
SM7635) based devices.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-7-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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