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path: root/drivers/cxl
AgeCommit message (Expand)Author
2022-07-12cxl/port: Hold port reference until decoder releaseDan Williams
2022-04-08cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron
2022-04-08cxl/core: Fix cxl_probe_component_regs() error messageDan Williams
2022-01-27cxl/pmem: Fix reference counting for delayed workDan Williams
2021-11-18cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams
2021-09-09Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds
2021-09-07cxl/registers: Fix Documentation warningDan Williams
2021-09-07cxl/pmem: Fix Documentation warningDan Williams
2021-09-07cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)
2021-09-07cxl/pci: Fix lockdown levelDan Williams
2021-09-07cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge portsAlison Schofield
2021-08-10cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny
2021-08-10cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny
2021-08-07cxl/pci: Store memory capacity valuesIra Weiny
2021-08-06cxl/pci: Simplify register setupBen Widawsky
2021-08-06cxl/pci: Ignore unknown register block typesBen Widawsky
2021-08-06cxl/core: Move memdev management to coreBen Widawsky
2021-08-06cxl/pci: Introduce cdevm_file_operationsDan Williams
2021-08-06cxl/core: Move register mapping infrastructureDan Williams
2021-08-06cxl/core: Move pmem functionalityDan Williams
2021-08-06cxl/core: Improve CXL core kernel docsBen Widawsky
2021-08-06cxl: Move cxl_core to new directoryBen Widawsky
2021-07-21bus: Make remove callback return voidUwe Kleine-König
2021-06-17cxl/pci: Rename CXL REGLOC IDBen Widawsky
2021-06-17cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield
2021-06-17cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams
2021-06-15cxl/core: Add cxl-bus driver infrastructureDan Williams
2021-06-14cxl/pci: Add media provisioning required commandsBen Widawsky
2021-06-12cxl/component_regs: Fix offsetBen Widawsky
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams
2021-06-09cxl/acpi: Enumerate host bridge root portsDan Williams
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams
2021-06-09cxl/Kconfig: Default drivers to CONFIG_CXL_BUSDan Williams
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams
2021-06-05cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'Dan Williams
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky
2021-06-05cxl/pci: Reserve individual register block regionsIra Weiny
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny
2021-06-05cxl/pci: Reserve all device regions at onceIra Weiny
2021-06-05cxl/pci: Introduce cxl_decode_register_block()Ira Weiny
2021-05-26cxl/mem: Get rid of @cxlm.baseBen Widawsky
2021-05-26cxl/mem: Move register locator logic into reg setupBen Widawsky
2021-05-26cxl/mem: Split creation from mapping in probeBen Widawsky
2021-05-26cxl/mem: Use dev instead of pdev->devBen Widawsky
2021-05-26cxl/mem: Demarcate vendor specific capability IDsBen Widawsky
2021-05-26cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma
2021-05-26cxl: Rename mem to pciBen Widawsky
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