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path: root/drivers/gpu/drm/i915/display/skl_watermark.c
AgeCommit message (Expand)Author
2025-01-24drm/i915/dsc: Check if vblank is sufficient for dsc prefillMitul Golani
2025-01-24drm/i915/scaler: Check if vblank is sufficient for scalerMitul Golani
2025-01-23drm/i915/display: fix typos in i915/display filesNitin Gote
2025-01-07drm/i915/display: convert global state to struct intel_displayJani Nikula
2025-01-07drm/i915/display: Adjust Added Wake Time with PKG_C_LATENCYAnimesh Manna
2024-12-16drm/i915/xe3: do not configure auto min dbuf for cursor WMsVinod Govindapillai
2024-12-12drm/i915/xe3: Use hw support for min/interim ddb allocations for async flipStanislav Lisovskiy
2024-12-12drm/i915/display: add a gelper to relative data rate handlingVinod Govindapillai
2024-12-12drm/i915/display: update to plane_wm register access functionVinod Govindapillai
2024-12-05drm/i915/wm: Club initialized variables of same type togetherSuraj Kandpal
2024-12-05drm/i915/wm: Modify latency programmed into PKG_C_LATENCYSuraj Kandpal
2024-12-05drm/i915/display: Refactor DPKGC code to call it from atomic_commit_tailSuraj Kandpal
2024-12-05drm/i915/wm: Use intel_display structure in DPKGC codeSuraj Kandpal
2024-12-05drm/i915/wm: Refactor dpkgc value preprationSuraj Kandpal
2024-12-05drm/i915/wm: Initialize max_latency variable to appropriate valueSuraj Kandpal
2024-11-12drm/i915/display: convert HAS_HW_SAGV_WM() to struct intel_displayJani Nikula
2024-11-12drm/i915/display: convert HAS_SAGV() to struct intel_displayJani Nikula
2024-11-12drm/i915/display: convert HAS_MBUS_JOINING() to struct intel_displayJani Nikula
2024-11-06drm/i915: Simplify xelpdp_is_only_pipe_per_dbuf_bank()Ville Syrjälä
2024-11-06drm/i915: Sanitize MBUS joiningVille Syrjälä
2024-11-06drm/i915: Extract mbus_ctl_join_update()Ville Syrjälä
2024-11-06drm/i915: Extract pipe_mbus_dbox_ctl_update()Ville Syrjälä
2024-11-06drm/i915: Extract pipe_mbus_dbox_ctl()Ville Syrjälä
2024-11-06drm/i915: Relocate the SKL wm sanitation codeVille Syrjälä
2024-10-30drm/i915/display: use x100 version for full version and releaseJani Nikula
2024-10-11drm/i915/xe3lpd: Adjust watermark calculationsMatt Roper
2024-09-11drm/i915/cdclk: Convert CDCLK code to intel_displayVille Syrjälä
2024-09-05drm/i915/display: pass display to intel_crtc_for_pipe()Jani Nikula
2024-09-05drm/i915/display: include media/cec-notifier.h and linux/debugfs.h where neededJani Nikula
2024-08-01drm/i915/dpkgc: Add VRR condition for DPKGC EnablementSuraj Kandpal
2024-05-31drm/i915: Plumb the full atomic state into skl_ddb_add_affected_planes()Ville Syrjälä
2024-05-15drm/i915: Handle SKL+ WM/DDB registers next to all other plane registersVille Syrjälä
2024-05-15drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()Ville Syrjälä
2024-05-15drm/i915: Extract skl_plane_{wm,ddb}_reg_val()Ville Syrjälä
2024-05-15drm/i915: Move skl+ wm/ddb registers to proper headersVille Syrjälä
2024-05-15drm/i915: Extract skl_universal_plane_regs.hVille Syrjälä
2024-05-03drm/i915/xe2hpd: Do not program MBUS_DBOX BW creditsJosé Roberto de Souza
2024-05-03drm/i915: Reject async flips if we need to change DDB/watermarksVille Syrjälä
2024-04-19drm/i915/display: Disable SAGV on bw init, to force QGV point recalculationStanislav Lisovskiy
2024-04-08drm/i915: move i915_fixed.h to display/intel_fixed.hJani Nikula
2024-04-04drm/i915: Optimize out redundant dbuf slice updatesVille Syrjälä
2024-04-04drm/i915: Use a plain old int for the cdclk/mdclk ratioVille Syrjälä
2024-04-04drm/i915: Implement vblank synchronized MBUS join changesStanislav Lisovskiy
2024-04-04drm/i915: Use the correct mdclk/cdclk ratio in MBUS updatesVille Syrjälä
2024-04-04drm/i915: Add debugs for mbus joining and dbuf ratio programmingVille Syrjälä
2024-04-04drm/i915: Extract intel_dbuf_mdclk_min_tracker_update()Ville Syrjälä
2024-04-04drm/i915: Extract intel_dbuf_mbus_join_update()Ville Syrjälä
2024-04-04drm/i915: Relocate intel_mbus_dbox_update()Ville Syrjälä
2024-04-04drm/i915: Loop over all active pipes in intel_mbus_dbox_updateStanislav Lisovskiy
2024-03-13drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changesGustavo Sousa
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-13 13:44:44 +0000