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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2022-01-29drm/i915: Flush TLBs before releasing backing storeTvrtko Ursulin
2020-01-14drm/i915: Add Wa_1407352427:icl,ehlMatt Roper
2020-01-14drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehlMatt Roper
2019-11-05drm/i915/gen8+: Add RC6 CTX corruption WAImre Deak
2019-11-05drm/i915: Lower RM timeout to avoid DSI hard hangsUma Shankar
2019-11-05drm/i915: Add gen9 BCS cmdparsingJon Bloomfield
2019-08-20drm/i915/tgl: Updated Private PAT programmingMichel Thierry
2019-08-16drm/i915: Move gmbus definitions out of i915_reg.hDaniele Ceraolo Spurio
2019-08-16drm/i915: Move engine IDs out of i915_reg.hDaniele Ceraolo Spurio
2019-08-16drm/i915: Move i915_power_well_id out of i915_reg.hDaniele Ceraolo Spurio
2019-08-13drm/i915: Add _TRANS2()José Roberto de Souza
2019-08-13drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORTJosé Roberto de Souza
2019-08-08drm/i915/tgl: Fix the read of the DDI that transcoder is attached toJosé Roberto de Souza
2019-08-08drm/i915/tgl/dsi: Enable blanking packets during BLLP for video modeVandita Kulkarni
2019-08-01drm/i915/tgl: Add and use new DC5 and DC6 residency counter registersJosé Roberto de Souza
2019-07-31drm/i915/tgl: Tigerlake only has global MOCS registersMichel Thierry
2019-07-31drm/i915/tgl: Move fault registers to their new offsetLucas De Marchi
2019-07-30drm/i915/tgl: handle DP aux interruptsLucas De Marchi
2019-07-30drm/i915/tgl: Update north display hotplug detection to TGL connectionsJosé Roberto de Souza
2019-07-30drm/i915/tgl: Add hpd interrupt handlingLucas De Marchi
2019-07-26drm/i915/tgl: update ddi/tc clock_off bitsMahesh Kumar
2019-07-26drm/i915/tgl: select correct bit for port selectMahesh Kumar
2019-07-19drm/i915/icl: Add Wa_1409178092Tvrtko Ursulin
2019-07-13drm/i915/guc: unify guc irq handlingDaniele Ceraolo Spurio
2019-07-12drm/i915: Add modular FIAAnusha Srivatsa
2019-07-12drm/i915: Add test for invalid flag bits in whitelist entriesJohn Harrison
2019-07-11drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza
2019-07-11drm/i915/tgl: Add DPLL registersLucas De Marchi
2019-07-11drm/i915/tgl: Add gmbus gpio pin to port mappingMahesh Kumar
2019-07-11drm/i915/tgl: apply Display WA #1178 to fix type C donglesLucas De Marchi
2019-07-11drm/i915/tgl: Add power well to support 4th pipeMika Kahola
2019-07-11drm/i915/tgl: Add power well supportImre Deak
2019-07-11drm/i915/tgl: Check if pipe D is fusedJosé Roberto de Souza
2019-07-11drm/i915: Add 4th pipe and transcoderLucas De Marchi
2019-07-10drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespaceMatt Roper
2019-07-10drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHYMatt Roper
2019-07-10Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi
2019-07-05drm/i915: Program plane gamma rampsVille Syrjälä
2019-07-05drm/i915: Disable sprite gamma on ivb-bdwVille Syrjälä
2019-07-01drm/i915/ehl: Add third combo PHY offsetMatt Roper
2019-06-21Merge tag 'drm-intel-next-2019-06-19' of git://anongit.freedesktop.org/drm/dr...Dave Airlie
2019-06-20drm/i915/ehl/dsi: Enable AFE over PPI strapJosé Roberto de Souza
2019-06-20drm/i915/ehl/dsi: Set lane latency optimization for DW1Vandita Kulkarni
2019-06-19drm/i915/ehl: Allow combo PHY A to drive a third external displayMatt Roper
2019-06-19Merge v5.2-rc5 into drm-nextDaniel Vetter
2019-06-18drm/i915: Support flags in whitlist WAsJohn Harrison
2019-06-17drm/i915/icl: Add register definitions for Multi Segmented gammaUma Shankar
2019-06-14drm/i915: Add Wa_1409120013:icl,ehlMatt Roper
2019-06-12drm/i915: Improve WRPLL reference clock readout on HSW/BDWVille Syrjälä
2019-06-12drm/i915: Rename HSW/BDW PLL bitsVille Syrjälä
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